Add VHDL driver
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Roselyne Chotin-Avot
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#!/usr/bin/env python
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#
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# -*- mode:Python -*-
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#
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# This file is part of the Coriolis Software.
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# Copyright (c) UPMC/LIP6 2008-2017, All Rights Reserved
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#
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# +-----------------------------------------------------------------+
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# | C O R I O L I S |
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# | S t r a t u s - Netlists/Layouts Description |
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# | |
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# | Author : Roselyne CHOTIN-AVOT |
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# | E-mail : Roselyne.Chotin-Avot@lip6.fr |
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# | =============================================================== |
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# | Py Module : "./st_export.py" |
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# +-----------------------------------------------------------------+
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import os
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from st_model import Model
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from st_net import net
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sep = " "
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# the list of components is updated at each new model to avoid to re-create them
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COMPONENTS ={}
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def write(model,format,extraLibs = []):
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if format == 'vhd':
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# create component for virtual library
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BV2VHDComponents()
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# remove all previous generation of files
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os.system("rm -f *.vhd *.vst")
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# create the VHDL model of the cell
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obj = VHDModel(model,extraLibs)
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else:
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raise "Not yet implemented format %s" %(format)
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# write the file
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obj.write()
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# create component for virtual library
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def BV2VHDComponents():
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from st_parser import BV
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from st_getrealmodel import GetRealModel
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for model in BV:
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(realM,inout) = GetRealModel(model)
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component = sep + "component %s\n" %realM + sep + "port (\n"
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for pin in inout:
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# stratus makes the asumption that pin names depend of the direction
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if pin in ['q','nq','sout','cout']: direct = "OUT"
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else: direct = "IN"
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component += sep + "%s: %s std_logic;\n" %(pin,direct)
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COMPONENTS[realM] = component[0:-2] + "\n" + sep + ");\n"
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# Associated VHDL of stratus Model
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# Create associated VHDL for :
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# - libraries
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# - ports
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# - instances
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# - and internal signals
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class VHDModel():
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def __init__(self, cell, extraLibs = []):
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self._cell = cell
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self._extraLibs = extraLibs
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self._str = ""
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self.model2vhd()
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self.write()
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def model2vhd(self):
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self._str += self.librairies2vhd()
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self._str += "entity " + self._cell._name + " is\n"
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self._str += self.ports2vhd()
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self._str += "end " + self._cell._name + ";\n"
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self._str += "\narchitecture structural of %s is\n" %self._cell._name
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self.insts2vhd()
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self._str += self._components
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self._str += self.sig2vhd()
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self._str += "begin\n"
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self._str += self._insts
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self._str += "end structural;\n"
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COMPONENTS[self._cell._name] = sep + "component %s\n" %self._cell._name + self._ports + sep + "end component;\n"
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def librairies2vhd(self):
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self._libs = "library ieee;\n"
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self._libs += "use ieee.std_logic_1164.all;\n\n"
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# the model used standard cells
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if 'realModel' in self._cell._param :
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self._libs += "library sxlib;\n"
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self._libs += "use sxlib.all;\n\n"
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for lib in self._extraLibs:
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self._libs = self._libs + lib + ";\n"
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return self._libs
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def ports2vhd(self):
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self._ports = sep + "port(\n"
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for port in self._cell._st_ports + self._cell._st_cks:
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self._ports += sep + sep + VHDNet(port)._str
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self._ports = self._ports[0:-2]
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self._ports += "\n" + sep + ");\n"
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return self._ports
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def insts2vhd(self):
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self._insts = ""
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self._components = ""
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# list of the components of this model
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insts_components = []
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for inst in self._cell._st_insts:
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vhd_inst = VHDInst(inst)
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self._insts += vhd_inst._str
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# if it is not already present we add it
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if inst._model not in insts_components:
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insts_components.append(inst._model)
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self._components += COMPONENTS[inst._model]
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return self._insts
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def sig2vhd(self):
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self._sigs = ""
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for sig in self._cell._st_sigs:
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self._sigs += sep + "signal " + VHDNet(sig)._str
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return self._sigs
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def write(self):
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format = 'vhd'
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file = open(self._cell._name + "." + format, "w+")
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file.write( "--\n" )
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file.write( "-- Generated by Stratus export format %s\n" %format )
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file.write( "--\n" )
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file.write(self._str)
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file.close()
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# Associated VHDL of stratus Net
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class VHDNet():
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def __init__(self, net):
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direct = ""
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# only external signals have a direction
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if net._ext:
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direct = net._direct
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self._str = "%s : %s std_logic" %(net._name,direct)
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if net._arity != 1:
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self._str += "_vector(%d downto 0)" %net._arity
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self._str += ";\n"
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# Associated VHDL of stratus Inst
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class VHDInst():
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def __init__(self, inst):
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# if the model is not yet in the components list we have to create it
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if inst._model not in COMPONENTS:
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model = VHDModel(inst._st_masterCell)
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self._str = sep + inst._name + " : " + inst._model + "\n"
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self._str += sep + sep + "port map (\n"
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for (k,v) in inst._map.iteritems():
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# the alim are not present in VHDL
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if not v._h_type or v._h_type not in ["POWER", "GROUND"]:
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# change the stratus' slice [] in VHDL's one ()
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name = v._name.replace('[','(').replace(']',')')
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self._str += sep + sep + sep +"%s => %s,\n" %(k,name)
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self._str = self._str[0:-2]
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self._str += "\n" + sep + sep + ");\n"
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class VLog:
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def __init__(self, cell):
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raise "Not yet implemented"
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## class VLogModel(ExportModel):
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## def __init__(self):
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## Export.__init__(self)
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## def createEntity(self):
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## ports = createPorts()
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## res = "module " + self._cell._name + " (\n"
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## res += ports[0]
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## res += ");\n"
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## res += ports[1]
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## return res
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class Json:
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def __init__(self, cell):
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raise "Not yet implemented"
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@ -43,7 +43,7 @@ def setEditor ( editor ):
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#######################
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##### Class Model #####
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#######################
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class Model :
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class Model() :
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##########################
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##### Initialisation #####
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@ -447,16 +447,13 @@ class Model :
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if views == STRATUS :
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self.exportStratus ( fileName )
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elif netlistFormat in ['vst','vhd'] :
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elif netlistFormat == 'vst' :
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UpdateSession.open()
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hurCell = self._hur_cell
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if str ( hurCell.getName() ) != "__Scratch__" :
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if netlistFormat == 'vst' :
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FRAMEWORK.saveCell ( hurCell, views|CRL.Catalog.State.Logical )
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else :
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self.exportVHD()
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FRAMEWORK.saveCell ( hurCell, views|CRL.Catalog.State.Logical )
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if len ( CELLS ) == 0 :
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err = "\n[Stratus ERROR] Save : CELLS stack is empty.\n"
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@ -469,8 +466,8 @@ class Model :
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elif netlistFormat == 'stratus' :
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self.exportStratus ( fileName )
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elif netlistFormat == 'vlog' :
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raise Exception('Format %s not yet implemented' % netlistFormat)
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elif netlistFormat in ['vhd','vlog','json'] :
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self.export(netlistFormat)
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else :
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raise Exception('Unrecognized format %s' % netlistFormat)
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@ -722,6 +719,14 @@ class Model :
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##### End #####
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file.close ()
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##### Export the given database in the given format
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def export ( self, format):
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from st_export import write
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if format not in ['vhd','vlog','json']:
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raise "Unrecognized format %s" %(format)
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write(self,format)
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##### Create a IEEE VHDL file given the database #####
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def exportVHD ( self ) :
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@ -886,6 +886,7 @@ class net :
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self._to_cat = []
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self._real_net = None
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self._ext = extern
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self._h_type = hType
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if extern : self._direct = direction
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# Error :
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@ -894,7 +895,6 @@ class net :
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raise Exception ( err )
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if hType :
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self._h_type = hType
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if hType == "POWER" : self._st_cell._st_vdds.append ( self )
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elif hType == "GROUND" : self._st_cell._st_vsss.append ( self )
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elif hType == "CLOCK" : self._st_cell._st_cks.append ( self )
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