riscv
/
coriolis
mirror of https://gitlab.lip6.fr/vlsi-eda/coriolis.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Avoid possible min. width violations. 

For gf180mcu min. width violations were seen on the left pad to core
connection.
This commit is contained in:
Staf Verhaegen 2023-05-19 19:09:46 +02:00
parent f5421da02d
commit 6470c9ef94
1 changed files with 16 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
cumulus/src/plugins/chip/__init__.py
View File

@ -332,6 +332,14 @@ class CoreWire ( object ):
if self.padSegment.getLayer().isSymbolic():
vStrapBb.inflate( 0, -self.padSegment.getLayer().getExtentionCap()
, 0, -self.padSegment.getLayer().getExtentionCap() )
v = Vertical.create( self.chipNet
, self.symSegmentLayer
, vStrapBb.getCenter().getX()
, vStrapBb.getWidth()
, vStrapBb.getYMin()
, vStrapBb.getYMax()
)
trace( 550, '\tvChip={}\n'.format( v ))
v = Vertical.create( self.chipNet
, self.padSegment.getLayer()
, vStrapBb.getCenter().getX()
@ -437,6 +445,14 @@ class CoreWire ( object ):
if self.padSegment.getLayer().isSymbolic():
hStrapBb.inflate( -self.padSegment.getLayer().getExtentionCap(), 0
, -self.padSegment.getLayer().getExtentionCap(), 0 )
hStrap = Horizontal.create( self.chipNet
, self.symSegmentLayer
, hStrapBb.getCenter().getY()
, hStrapBb.getHeight()
, hStrapBb.getXMin()
, hStrapBb.getXMax()
)
trace( 550, '\thStrap={}\n'.format(hStrap) )
hStrap = Horizontal.create( self.chipNet
, self.padSegment.getLayer()
, hStrapBb.getCenter().getY()