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coriolis
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!! Adding support for subCircuits !!! 

* New <subCircuitsPathes> section in <circuit> that lists the pathes that contain subCircuits xml files

    * New Device object that inherits from simplified Instance object.
        - Instance has a name, a model, some connectors and optionnal parameters
        - Device has the same attributes plus mosType, sourceBulkConnected and transistors

    * Updated readFromFile and wrtieToFile methods to support these modifications

    * Updated parse and drive examples to support these modifications
        - Note: only C++ examples has been updated since my boost.python environment is actually totaly broken

    * New buffer.xml example that uses subCircuits.
This commit is contained in:
Damien Dupuis 2010-11-22 10:22:04 +00:00
parent 5887a0b59f
commit 501ac35b2b
5 changed files with 77 additions and 10 deletions
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6
vlsisapd/examples/openChams/CMakeLists.txt
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@ -1,4 +1,8 @@
ADD_SUBDIRECTORY(cplusplus)
ADD_SUBDIRECTORY(python)
INSTALL ( FILES inverter.xml DESTINATION share/doc/coriolis2/examples/vlsisapd/openChams )
SET ( XML_FILES inverter.xml
buffer.xml
)
INSTALL ( FILES ${XML_FILES} DESTINATION share/doc/coriolis2/examples/vlsisapd/openChams )

46
vlsisapd/examples/openChams/buffer.xml Normal file
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@ -0,0 +1,46 @@
<?xml version="1.0" encoding="UTF-8"?>
<circuit name="buffer" techno="myTech">
<subCircuitsPathes>
<path path="."/>
</subCircuitsPathes>
<netlist>
<instances>
<instance name="inv1" model="inverter">
<connectors>
<connector name="vdd"/>
<connector name="vss"/>
<connector name="in" />
<connector name="out"/>
</connectors>
</instance>
<instance name="inv2" model="inverter">
<connectors>
<connector name="vdd"/>
<connector name="vss"/>
<connector name="in" />
<connector name="out"/>
</connectors>
</instance>
</instances>
<nets>
<net name="vdd" type="power" isExternal="True">
<connector instance="inv1" name="vdd"/>
<connector instance="inv2" name="vdd"/>
</net>
<net name="vss" type="ground" isExternal="True">
<connector instance="inv1" name="vss"/>
<connector instance="inv2" name="vss"/>
</net>
<net name="in" type="logical" isExternal="True">
<connector instance="inv1" name="in"/>
</net>
<net name="out" type="logical" isExternal="True">
<connector instance="inv2" name="out"/>
</net>
<net name="internal" type="logical" isExternal="False">
<connector instance="inv1" name="out"/>
<connector instance="inv2" name="in"/>
</net>
</nets>
</netlist>
</circuit>

5
vlsisapd/examples/openChams/cplusplus/driveOpenChams.cpp
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@ -4,6 +4,7 @@ using namespace std;
#include "vlsisapd/openChams/Circuit.h"
#include "vlsisapd/openChams/Netlist.h"
#include "vlsisapd/openChams/Instance.h"
#include "vlsisapd/openChams/Device.h"
#include "vlsisapd/openChams/Transistor.h"
#include "vlsisapd/openChams/Net.h"
#include "vlsisapd/openChams/Schematic.h"
@ -27,7 +28,7 @@ int main(int argc, char * argv[]) {
OpenChams::Netlist* netlist = circuit->createNetlist();
// instances
// nmos1
OpenChams::Instance* inst_nmos1 = netlist->addInstance(OpenChams::Name("nmos1"), OpenChams::Name("Transistor"), OpenChams::Name("NMOS"), true);
OpenChams::Device* inst_nmos1 = netlist->addDevice(OpenChams::Name("nmos1"), OpenChams::Name("Transistor"), OpenChams::Name("NMOS"), true);
inst_nmos1->addConnector(OpenChams::Name("G"));
inst_nmos1->addConnector(OpenChams::Name("S"));
inst_nmos1->addConnector(OpenChams::Name("D"));
@ -37,7 +38,7 @@ int main(int argc, char * argv[]) {
tr_nmos1->setDrain (OpenChams::Name("D"));
tr_nmos1->setBulk (OpenChams::Name("S"));
// pmos1
OpenChams::Instance* inst_pmos1 = netlist->addInstance(OpenChams::Name("pmos1"), OpenChams::Name("Transistor"), OpenChams::Name("PMOS"), true);
OpenChams::Device* inst_pmos1 = netlist->addDevice(OpenChams::Name("pmos1"), OpenChams::Name("Transistor"), OpenChams::Name("PMOS"), true);
inst_pmos1->addConnector(OpenChams::Name("G"));
inst_pmos1->addConnector(OpenChams::Name("S"));
inst_pmos1->addConnector(OpenChams::Name("D"));

24
vlsisapd/examples/openChams/cplusplus/parseOpenChams.cpp
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@ -9,12 +9,14 @@ using namespace std;
#include "vlsisapd/openChams/Parameters.h"
#include "vlsisapd/openChams/Netlist.h"
#include "vlsisapd/openChams/Instance.h"
#include "vlsisapd/openChams/Device.h"
#include "vlsisapd/openChams/Net.h"
#include "vlsisapd/openChams/Transistor.h"
#include "vlsisapd/openChams/Schematic.h"
#include "vlsisapd/openChams/Sizing.h"
#include "vlsisapd/openChams/Operator.h"
#include "vlsisapd/openChams/Layout.h"
#include "vlsisapd/openChams/OpenChamsException.h"
int main(int argc, char * argv[]) {
string file = "";
@ -27,7 +29,13 @@ int main(int argc, char * argv[]) {
exit(1);
}
OpenChams::Circuit* circuit = OpenChams::Circuit::readFromFile(file);
OpenChams::Circuit* circuit = NULL;
try {
circuit = OpenChams::Circuit::readFromFile(file);
} catch (OpenChams::OpenChamsException& e) {
cerr << e.what() << endl;
exit(48);
}
cerr << circuit->getName().getString() << endl;
cerr << " + parameters" << endl;
@ -46,7 +54,13 @@ int main(int argc, char * argv[]) {
if (netlist && !netlist->hasNoInstances()) {
for (size_t i = 0 ; i < netlist->getInstances().size() ; i++) {
OpenChams::Instance* inst = netlist->getInstances()[i];
cerr << " | | + " << inst->getName().getString() << " : " << inst->getModel().getString() << " - " << inst->getMosType().getString() << " - " << (inst->isSourceBulkConnected()?"true":"false") << endl;
OpenChams::Device* dev = NULL;
if (dynamic_cast<OpenChams::Device*>(inst)) {
dev = static_cast<OpenChams::Device*>(inst);
cerr << " | | + " << dev->getName().getString() << " : " << dev->getModel().getString() << " - " << dev->getMosType().getString() << " - " << (dev->isSourceBulkConnected()?"true":"false") << endl;
} else {
cerr << " | | + " << inst->getName().getString() << " : " << inst->getModel().getString() << endl;
}
cerr << " | | | + connectors" << endl;
for (map<OpenChams::Name, OpenChams::Net*>::const_iterator cit = inst->getConnectors().begin() ; cit != inst->getConnectors().end() ; ++cit) {
if ((*cit).second)
@ -54,13 +68,15 @@ int main(int argc, char * argv[]) {
else
cerr << " | | | | " << ((*cit).first).getString() << endl; // no net connected !
}
if (dev) {
cerr << " | | | + transistors" << endl;
for (size_t j = 0 ; j < inst->getTransistors().size() ; j++) {
OpenChams::Transistor* tr = inst->getTransistors()[j];
for (size_t j = 0 ; j < dev->getTransistors().size() ; j++) {
OpenChams::Transistor* tr = dev->getTransistors()[j];
cerr << " | | | | name: " << tr->getName().getString() << " - gate: " << tr->getGate().getString() << " - source: " << tr->getSource().getString() << " - drain: " << tr->getDrain().getString() << " - bulk: " << tr->getBulk().getString() << endl;
}
}
}
}
cerr << " | + nets" << endl;
if (!netlist->hasNoNets()) {
for (size_t i = 0 ; i < netlist->getNets().size() ; i++) {

2
vlsisapd/examples/openChams/inverter.xml
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@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<circuit name="design" techno="myTech">
<circuit name="inverter" techno="myTech">
<parameters>
<parameter name="temp" value="27.0"/>
<parameter name="Vdd" value="1.2"/>