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Anlog integration part I. Atomic devices support (transistors). 

* Change: In boostrap, remove support for Chams.
* New: In Hurricane::Technology, added support for DTR rules, UnitRule,
    PhysicalRule and TwoLayersPhysicalrule. Added devices descriptors and
    models descriptors (for Spice). Spice description is not used yet
    but kept anyway in case of future use.
* New: Hurricane::Analog whole library and it's Python interface. This
    provides support for transistors, capacitors and resistors. Only
    transistor support is fully implemented as of now.
* New: In CRL/python/coriolisInit.py, read configuration files for the
    Analog extension (analog.conf & devices.conf). Thoses are optionals
    and a simple warning is issued if not found.
      Added helpers/AnalogTechno.py DTR loading helper.
      Add analog configuration files for 180/scn6m_deep_09.
* New: Oroshi tool that provides actual layout drawing for transistors.
This commit is contained in:
Jean-Paul Chaput 2018-10-01 16:52:17 +02:00
parent dc01b60d5c
commit 3f73b9d033
1236 changed files with 26246 additions and 1902 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.gitignore vendored
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@ -11,6 +11,7 @@ GRTAGS
.dir-locals.el
.projectile
lefdef/src/lef/lef/lef.tab.h
man/
rtf/

19
bootstrap/build.conf
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@ -17,9 +17,6 @@ projects = [
, "vlsisapd"
, "hurricane"
, "crlcore"
#, "nimbus"
#, "metis"
#, "mauka"
, "anabatic"
, "katana"
, "knik"
@ -29,6 +26,7 @@ projects = [
, "etesian"
, "equinox"
, "solstice"
, "oroshi"
, "unicorn"
, "tutorial"
#, "testbench"
@ -38,21 +36,6 @@ projects = [
, "documentation"
]
, 'repository': 'ssh://asim-t/users/largo2/git/coriolis.git' }
, { 'name' : "chams"
, 'tools' : [ "hurricaneAMS"
, "amsCore"
, "opSim"
#, "scribe"
, "graph"
, "pharos"
, "isis"
, "horus"
#, "schematic"
, "solver"
, "autoDTR"
]
, 'repository':"ssh://melon-t/users/outil/chams/chams.git" }
]
package = { 'name' : 'coriolis2'

4
bootstrap/ccb.py
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@ -159,12 +159,8 @@ def autoLocate ():
locations = [ os.path.abspath(os.path.dirname(sys.argv[0]))
, os.environ['HOME']+'/coriolis-2.x/src/coriolis/bootstrap'
, os.environ['HOME']+'/coriolis/src/coriolis/bootstrap'
, os.environ['HOME']+'/chams-1.x/src/coriolis/bootstrap'
, os.environ['HOME']+'/chams/src/coriolis/bootstrap'
, '/users/outil/coriolis/coriolis-2.x/src/coriolis/bootstrap'
, os.environ['HOME']+'/coriolis-2.x/'+osType+'/Release.Shared/install/'+libDir+'/'+sitePackage
, os.environ['HOME']+'/chams-1.x/'+osType+'/Release.Shared/install/'+libDir+'/'+sitePackage
, os.environ['HOME']+'/chams/'+osType+'/Release.Shared/install/'+libDir+'/'+sitePackage
, '/users/outil/coriolis/coriolis-2.x/'+osType+'/Release.Shared/install/'+libDir+'/'+sitePackage
]

1
bootstrap/coriolisEnv.py
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@ -185,7 +185,6 @@ if __name__ == "__main__":
parser.add_option ( "--devel" , action="store_true" , dest="devel" )
parser.add_option ( "--static" , action="store_true" , dest="static" )
parser.add_option ( "--shared" , action="store_true" , dest="shared" )
parser.add_option ( "--chams" , action="store_true" , dest="chams" )
parser.add_option ( "--no-python" , action="store_true" , dest="nopython" )
parser.add_option ( "--root" , action="store" , type="string", dest="rootDir" )
( options, args ) = parser.parse_args ()

6
bootstrap/socInstaller.py
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@ -220,7 +220,7 @@ class Configuration ( object ):
PrimaryNames = \
[ 'sender' , 'receivers'
, 'coriolisRepo', 'chamsRepo' , 'benchsRepo', 'supportRepos'
, 'coriolisRepo', 'benchsRepo', 'supportRepos'
, 'homeDir' , 'masterHost'
, 'debugArg' , 'nightlyMode'
, 'rmSource' , 'rmBuild', 'doGit', 'doBuild', 'doBenchs', 'doSendReport'
@ -235,7 +235,6 @@ class Configuration ( object ):
self._receivers = [ 'Jean-Paul.Chaput@lip6.fr', 'Eric.Lao@lip6.fr' ]
self._supportRepos = [ 'http://github.com/miloyip/rapidjson' ]
self._coriolisRepo = 'https://www-soc.lip6.fr/git/coriolis.git'
self._chamsRepo = 'file:///users/outil/chams/chams.git'
self._benchsRepo = 'https://www-soc.lip6.fr/git/alliance-check-toolkit.git'
self._homeDir = os.environ['HOME']
self._debugArg = ''
@ -458,7 +457,6 @@ try:
for supportRepo in conf.supportRepos:
gitSupports.append( GitRepository( supportRepo, conf.srcDir+'/support' ) )
gitCoriolis = GitRepository( conf.coriolisRepo, conf.srcDir, conf.fds['build'] )
gitChams = GitRepository( conf.chamsRepo , conf.srcDir, conf.fds['build'] )
gitBenchs = GitRepository( conf.benchsRepo , conf.srcDir, conf.fds['build'] )
if conf.doGit:
@ -492,7 +490,7 @@ try:
, ' <%s>' % ccbBin
] )
buildCommand = '%s --root=%s --project=support --project=coriolis --project=chams --make="-j%%d install" %%s' \
buildCommand = '%s --root=%s --project=support --project=coriolis --make="-j%%d install" %%s' \
% (ccbBin,conf.rootDir)
benchsCommand = 'cd %s/benchs && ./bin/go.sh clean && ./bin/go.sh lvx' \
% (gitBenchs.localRepoDir)

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# -*- Mode:Python; explicit-buffer-name: "analog.conf<scn6m_deep_09>" -*-
import helpers
execfile( helpers.ndaConfDir+'/common/analog.conf' )

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# -*- Mode:Python; explicit-buffer-name: "devices.conf<hcmos9gp>" -*-
import helpers
execfile( helpers.ndaConfDir+'/common/devices.conf' )

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# Name: dtr_scn6m_deep_09.py -- mosis scalable CMOS SCN6M_DEEP General Purpose with MIM capacitor
# Unit: micro
# version: rev.LIP6-1
#
# The MOSIS Scalable (SCMOS) design rules can be found here:
# https://www.mosis.com/files/scmos/scmos.pdf
#
# Used revision 8.00 of May 11, 2009.
from Hurricane import DbU
from helpers.AnalogTechno import Length
from helpers.AnalogTechno import Area
from helpers.AnalogTechno import Asymmetric
analogTechnologyTable = \
( ('Header', 'scmos6m_deep_09', DbU.UnitPowerMicro, 'rev.LIP6-1')
# ------------------------------------------------------------------------------------
# ( Rule name , [Layer1] , [Layer2] , Value, Rule flags , Reference )
, ('physicalGrid' , 0.09 , Length , 'N/A')
, ('transistorMinL' , 0.18 , Length , '2l rule 3.1 p.26')
, ('transistorMaxL' , 18 , Length , '200l arbitrary')
, ('transistorMinW' , 0.27 , Length , '3l arbitrary')
, ('transistorMaxW' , 270 , Length , '300l arbitrary')
, ('minWidth' , 'nWell' , 1.08 , Length , '12l rule 1.1 p.16')
, ('minSpacing' , 'nWell' , 1.62 , Length , '18l rule 1.2 p.16')
, ('minArea' , 'nWell' , 0 , Area , 'N/A')
, ('minWidth' , 'active' , 0.27 , Length , '3l rule 2.1 p.19')
, ('minSpacing' , 'active' , 0.27 , Length , '3l rule 2.2 p.19')
, ('minArea' , 'active' , 0 , Area , 'N/A')
, ('minEnclosure' , 'nWell' , 'active' , 0.54 , Length|Asymmetric, 'rule X.Y, p.Z')
, ('minEnclosure' , 'nImplant', 'nWell' , 0 , Length|Asymmetric, 'rule X.Y, p.Z')
, ('minWidth' , 'poly' , 0.18 , Length , '2l rule 3.1 p.26')
, ('minSpacing' , 'poly' , 0.27 , Length , '3l rule 3.2 p.26')
, ('minGateSpacing' , 'poly' , 0.36 , Length , '4l rule 3.2.a p.26')
, ('minArea' , 'poly' , 0 , Area , 'N/A')
, ('minGateExtension' , 'poly' , 'active' , 0.225, Length|Asymmetric, '2.5l rule 3.3 p.26')
, ('minGateExtension' , 'active' , 'poly' , 0.225, Length|Asymmetric, 'N/A')
, ('minExtension' , 'poly' , 'active' , 0.225, Length|Asymmetric, 'N/A')
, ('minExtension' , 'active' , 'poly' , 0.36 , Length|Asymmetric, '4l rule 3.4 p.26')
, ('minSpacing' , 'poly' , 'active' , 0.09 , Length , '1l rule 3.5 p.26')
, ('minGateSpacing' , 'nImplant', 'poly' , 0.27 , Length , '3l rule 4.1 N+ p.29')
, ('minEnclosure' , 'nImplant', 'active' , 0.18 , Length|Asymmetric, '2l rule 4.2 N+ p.29')
, ('minExtension' , 'nImplant', 'active' , 0.18 , Length|Asymmetric, 'dup. 4.2 N+' )
, ('minEnclosure' , 'nImplant', 'cut0' , 0.135, Length|Asymmetric, '1.5l rule 4.3 N+ p.29')
, ('minExtension' , 'nImplant', 'cut0' , 0.135, Length|Asymmetric, 'dup. 4.3 N+' )
, ('minWidth' , 'nImplant' , 0.36 , Length , '4l rule 4.4 N+ p.29')
, ('minSpacing' , 'nImplant' , 0.36 , Length , '4l rule 4.4 N+ p.29')
, ('minArea' , 'nImplant' , 0 , Area , 'N/A')
, ('minSpacing' , 'nImplant', 'active' , 0 , Length , 'N/A')
, ('minEnclosure' , 'nImplant', 'poly' , 0 , Length|Asymmetric, 'N/A')
, ('minLengthEnclosure', 'nImplant', 'active' , 0 , Length|Asymmetric, 'N/A')
, ('minWidthEnclosure' , 'nImplant', 'poly' , 0 , Length|Asymmetric, 'N/A')
, ('minGateEnclosure' , 'nImplant', 'poly' , 0 , Length|Asymmetric, 'N/A')
, ('minStrapEnclosure' , 'nImplant' , 0.135, Length , 'N/A')
, ('minSpacing' , 'nImplant', 'pImplant', 0 , Length , 'N/A')
, ('minGateSpacing' , 'pImplant', 'poly' , 0.27 , Length , '3l rule 4.1 P+ p.29')
, ('minEnclosure' , 'pImplant', 'active' , 0.18 , Length|Asymmetric, '2l rule 4.2 P+ p.29')
, ('minExtension' , 'pImplant', 'active' , 0.18 , Length|Asymmetric, 'dup. 4.2 P+' )
, ('minEnclosure' , 'pImplant', 'cut0' , 0.135, Length|Asymmetric, '1.5l rule 4.3 P+ p.29')
, ('minExtension' , 'pImplant', 'cut0' , 0.135, Length|Asymmetric, 'dup. 4.3 P-' )
, ('minWidth' , 'pImplant' , 0.36 , Length , '4l rule 4.4 P+ p.29')
, ('minSpacing' , 'pImplant' , 0.36 , Length , '4l rule 4.4 P+ p.29')
, ('minArea' , 'pImplant' , 0 , Area , 'N/A')
, ('minSpacing' , 'pImplant', 'active' , 0 , Length , 'N/A')
, ('minEnclosure' , 'pImplant', 'poly' , 0 , Length|Asymmetric, 'N/A')
, ('minLengthEnclosure', 'pImplant', 'active' , 0 , Length|Asymmetric, 'N/A')
, ('minWidthEnclosure' , 'pImplant', 'poly' , 0 , Length|Asymmetric, 'N/A')
, ('minGateEnclosure' , 'pImplant', 'poly' , 0 , Length|Asymmetric, 'N/A')
, ('minStrapEnclosure' , 'pImplant' , 0.135, Length , 'N/A')
, ('minWidth' , 'cut0' , 0.18 , Length , '2l rule 5.1 p.35')
, ('minEnclosure' , 'poly' , 'cut0' , 0.135, Length|Asymmetric, '1.5l rule 5.2 p.35')
, ('minExtension' , 'poly' , 'cut0' , 0.135, Length|Asymmetric, 'dup. 5.2' )
, ('minSpacing' , 'cut0' , 0.36 , Length , '4l rule 5.3 p.35')
, ('minGateSpacing' , 'cut0' , 'poly' , 0.18 , Length|Asymmetric, '2l rule 5.4 p.35')
, ('minSpacing' , 'cut0' , 'poly' , 0.18 , Length , 'dup. 5.4' )
, ('minSpacing' , 'cut0' , 'active' , 0.18 , Length , 'dup. 5.4' )
# Rule 6.1, 6.3 & 6.4 are the same as 5.1, 5.3 & 5.4.
, ('minEnclosure' , 'active' , 'cut0' , 0.135, Length|Asymmetric, '1.5l rule 6.2 p.37')
, ('minWidth' , 'metal1' , 0.27 , Length , '3l rule 7.1 p.39')
, ('minSpacing' , 'metal1' , 0.27 , Length , '3l rule 7.2 p.39')
, ('minArea' , 'metal1' , 0 , Area , 'N/A')
, ('minEnclosure' , 'metal1' , 'cut0' , 0.09 , Length|Asymmetric, '1l rule 7.3 p.39')
, ('minExtension' , 'metal1' , 'cut0' , 0.09 , Length|Asymmetric, 'dup. 7.3' )
, ('minWidth' , 'cut1' , 0.27 , Length , '3l rule 8.1 p.40')
, ('minSpacing' , 'cut1' , 0.27 , Length , '3l rule 8.2 p.40')
, ('minEnclosure' , 'metal1' , 'cut1' , 0.09 , Length|Asymmetric, '1l rule 8.3 p.40')
, ('lineExtension' , 'metal1' , 'cut1' , 0.09 , Length|Asymmetric, 'N/A')
, ('minWidth' , 'metal2' , 0.27 , Length , '3l rule 9.1 p.41')
, ('minSpacing' , 'metal2' , 0.36 , Length , '4l rule 9.2 p.41')
, ('minArea' , 'metal2' , 0 , Area , 'N/A')
, ('minExtension' , 'metal2' , 'cut1' , 0.09 , Length|Asymmetric, '1l rule 9.3 p.41')
, ('minEnclosure' , 'metal2' , 'cut1' , 0.09 , Length|Asymmetric, 'dup. 9.3' )
, ('minWidth' , 'cut2' , 0.27 , Length , '3l rule 14.1 p.42')
, ('minSpacing' , 'cut2' , 0.27 , Length , '3l rule 14.2 p.42')
, ('minEnclosure' , 'metal2' , 'cut2' , 0.09 , Length|Asymmetric, '1l rule 14.3 p.42')
, ('minWidth' , 'metal3' , 0.27 , Length , '3l rule 15.1 p.43')
, ('minSpacing' , 'metal3' , 0.36 , Length , '4l rule 15.2 p.43')
, ('minArea' , 'metal3' , 0 , Area , 'N/A')
, ('minExtension' , 'metal3' , 'cut2' , 0.09 , Length|Asymmetric, '1l rule 15.3 p.43')
, ('minEnclosure' , 'metal3' , 'cut2' , 0.09 , Length|Asymmetric, 'dup. 15.3' )
, ('minWidth' , 'cut3' , 0.27 , Length , '3l rule 21.1 p.44')
, ('minSpacing' , 'cut3' , 0.27 , Length , '3l rule 21.2 p.44')
, ('minEnclosure' , 'metal3' , 'cut3' , 0.09 , Length|Asymmetric, '1l rule 21.3 p.44')
, ('minWidth' , 'metal4' , 0.27 , Length , '3l rule 22.1 p.45')
, ('minSpacing' , 'metal4' , 0.36 , Length , '4l rule 22.2 p.45')
, ('minArea' , 'metal4' , 0 , Area , 'N/A')
, ('minExtension' , 'metal4' , 'cut3' , 0.09 , Length|Asymmetric, '1l rule 22.3 p.45')
, ('minEnclosure' , 'metal4' , 'cut3' , 0.09 , Length|Asymmetric, 'dup. 22.3' )
, ('minWidth' , 'cut4' , 0.27 , Length , '3l rule 25.1 p.49')
, ('minSpacing' , 'cut4' , 0.27 , Length , '3l rule 25.2 p.49')
, ('minEnclosure' , 'metal4' , 'cut4' , 0.09 , Length|Asymmetric, '1l rule 25.3 p.49')
, ('minWidth' , 'metal5' , 0.27 , Length , '3l rule 26.1 p.50')
, ('minSpacing' , 'metal5' , 0.36 , Length , '4l rule 26.2 p.50')
, ('minArea' , 'metal5' , 0 , Area , 'N/A')
, ('minExtension' , 'metal5' , 'cut4' , 0.09 , Length|Asymmetric, '1l rule 26.3 p.50')
, ('minEnclosure' , 'metal5' , 'cut4' , 0.09 , Length|Asymmetric, 'dup. 26.3' )
, ('minWidth' , 'cut5' , 0.36 , Length , '4l rule 29.1 p.51')
, ('minSpacing' , 'cut5' , 0.36 , Length , '4l rule 29.2 p.51')
, ('minEnclosure' , 'metal5' , 'cut5' , 0.09 , Length|Asymmetric, '1l rule 29.3 p.51')
, ('minWidth' , 'metal6' , 0.45 , Length , '5l rule 30.1 p.52')
, ('minSpacing' , 'metal6' , 0.45 , Length , '5l rule 30.2 p.52')
, ('minArea' , 'metal6' , 0 , Area , 'N/A')
, ('minExtension' , 'metal6' , 'cut5' , 0.18 , Length|Asymmetric, '2l rule 30.3 p.52')
, ('minEnclosure' , 'metal6' , 'cut5' , 0.18 , Length|Asymmetric, 'dup. 30.3' )
# MIM Rules (Metal In Metal Capacitor).
# In SCN6M_DEEP metbot is metal5 and metcap is *below* metal6.
# metbot can be accessed with cut4 (down) and via5 (up).
# metcap can only be accessed *from* up with cut5.
, ('minWidth' , 'metcap' , 4.05 , Length , '45l rule 28.1 p.46')
, ('minWidth' , 'metcapdum' , 0.45 , Length , '9l rule 28.8 p.47')
, ('maxWidth' , 'metcap' , 30.0 , Length , '30um rule 28.12 p.47')
, ('maxWidth' , 'metbot' , 35.0 , Length , '35um rule 28.13 p.47')
, ('minSpacing' , 'metcap' , 1.26 , Length , '14l rule 28.2 p.46')
, ('minSpacing' , 'metbot' , 0.81 , Length , '9l rule 28.9 p.47')
, ('minSpacing' , 'cut4' , 'metcap' , 0.45 , Length , '5l rule 28.5 D p.46')
, ('minSpacing' , 'cut5' , 'metcap' , 0.45 , Length , '5l rule 28.5 U p.46')
, ('minSpacingOnMetbot', 'cut5' , 4.05 , Length , '45l rule 28.11 p.47')
, ('minSpacingOnMetcap', 'cut5' , 2.07 , Length , '23l rule 28.10 p.47')
, ('minEnclosure' , 'metbot' , 'metcap' , 0.45 , Length|Asymmetric, '5l rule 28.3 p.46')
, ('minEnclosure' , 'metbot' , 'cut4' , 0.18 , Length|Asymmetric, '2l rule 28.6 D p.46')
, ('minEnclosure' , 'metbot' , 'cut5' , 0.18 , Length|Asymmetric, '2l rule 28.6 U p.46')
, ('minEnclosure' , 'metcap' , 'cut5' , 0.27 , Length|Asymmetric, '3l rule 28.4 p.46')
, ('minArea' , 'metcap' , 0 , Area , 'N/A')
, ('minAreaInMetcap' , 'cut5' , 0 , Area , 'N/A')
)

10
crlcore/etc/45/freepdk_45/analog.conf Normal file
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@ -0,0 +1,10 @@
# -*- Mode:Python; explicit-buffer-name: "analog.conf<common>" -*-
import helpers
parametersTable = \
( ('analog.techno' , TypeString, 'Analog_technology_is_disabled',
{ 'flags':Cfg.Parameter.Flags.NeedRestart|Cfg.Parameter.Flags.MustExist } )
, ('analog.devices', TypeString, helpers.technoDir+'/devices.conf' )
)

10
crlcore/etc/common/analog.conf Normal file
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@ -0,0 +1,10 @@
# -*- Mode:Python; explicit-buffer-name: "analog.conf<common>" -*-
import helpers
parametersTable = \
( ('analog.techno' , TypeString, 'Analog_technology_has_not_been_set',
{ 'flags':Cfg.Parameter.Flags.NeedRestart|Cfg.Parameter.Flags.MustExist } )
, ('analog.devices', TypeString, helpers.technoDir+'/devices.conf' )
)

117
crlcore/etc/common/devices.conf Normal file
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@ -0,0 +1,117 @@
# -*- Mode:Python; explicit-buffer-name: "devices.conf<common>" -*-
import helpers
analogDir = helpers.sysConfDir + '/share/coriolis2/analog'
spiceDir = analogDir + 'spice/'
devicesTable = \
( { 'name' : 'DifferentialPairBulkConnected'
, 'spice' : spiceDir+'DiffPairBulkConnected.spi'
, 'connectors' : ( 'D1', 'D2', 'G1', 'G2', 'S' )
, 'layouts' : ( ('Horizontal M2' , 'DP_horizontalM2.py' )
, ('Symmetrical' , 'DP_symmetrical.py' )
, ('Common centroid', 'DP_2DCommonCentroid.py')
, ('Interdigitated' , 'DP_interdigitated.py' )
, ('WIP DP' , 'WIP_DP.py' )
)
}
, { 'name' : 'DifferentialPairBulkUnconnected'
, 'spice' : spiceDir+'DiffPairBulkUnconnected.spi'
, 'connectors' : ( 'D1', 'D2', 'G1', 'G2', 'S', 'B' )
, 'layouts' : ( ('Horizontal M2' , 'DP_horizontalM2.py' )
, ('Symmetrical' , 'DP_symmetrical.py' )
, ('Common centroid', 'DP_2DCommonCentroid.py')
, ('Interdigitated' , 'DP_interdigitated.py' )
, ('WIP DP' , 'WIP_DP.py' )
)
}
, { 'name' : 'LevelShifterBulkUnconnected'
, 'spice' : spiceDir+'LevelShifterBulkUnconnected.spi'
, 'connectors' : ( 'D1', 'D2', 'S1', 'S2', 'B' )
, 'layouts' : ( ('Horizontal M2' , 'LS_horizontalM2.py' )
, ('Symmetrical' , 'LS_symmetrical.py' )
, ('Common centroid', 'LS_2DCommonCentroid.py')
, ('Interdigitated' , 'LS_interdigitated.py' )
)
}
, { 'name' : 'TransistorBulkConnected'
, 'spice' : spiceDir+'TransistorBulkConnected.spi'
, 'connectors' : ( 'D', 'G', 'S' )
, 'layouts' : ( ('Rotate transistor', 'Transistor_rotate.py' )
, ('Common transistor', 'Transistor_common.py' )
, ('WIP Transistor' , 'WIP_Transistor.py' )
)
}
, { 'name' : 'TransistorBulkUnconnected'
, 'spice' : spiceDir+'TransistorBulkUnconnected.spi'
, 'connectors' : ( 'D', 'G', 'S', 'B' )
, 'layouts' : ( ('Rotate transistor', 'Transistor_rotate.py' )
, ('Common transistor', 'Transistor_common.py' )
, ('WIP Transistor' , 'WIP_Transistor.py' )
)
}
, { 'name' : 'CrossCoupledPairBulkConnected'
, 'spice' : spiceDir+'CCPairBulkConnected.spi'
, 'connectors' : ( 'D1', 'D2', 'S' )
, 'layouts' : ( ('Horizontal M2' , 'CCP_horizontalM2.py' )
, ('Symmetrical' , 'CCP_symmetrical.py' )
, ('Common centroid', 'CCP_2DCommonCentroid.py')
, ('Interdigitated' , 'CCP_interdigitated.py' )
)
}
, { 'name' : 'CrossCoupledPairBulkUnconnected'
, 'spice' : spiceDir+'CCPairBulkUnconnected.spi'
, 'connectors' : ( 'D1', 'D2', 'S', 'B' )
, 'layouts' : ( ('Horizontal M2' , 'CCP_horizontalM2.py' )
, ('Symmetrical' , 'CCP_symmetrical.py' )
, ('Common centroid', 'CCP_2DCommonCentroid.py')
, ('Interdigitated' , 'CCP_interdigitated.py' )
)
}
, { 'name' : 'CommonSourcePairBulkConnected'
, 'spice' : spiceDir+'CommonSourcePairBulkConnected.spi'
, 'connectors' : ( 'D1', 'D2', 'S', 'G' )
, 'layouts' : ( ('Horizontal M2' , 'CSP_horizontalM2.py' )
, ('Symmetrical' , 'CSP_symmetrical.py' )
, ('Interdigitated' , 'CSP_interdigitated.py' )
, ('WIP CSP' , 'WIP_CSP.py' )
)
}
, { 'name' : 'CommonSourcePairBulkUnconnected'
, 'spice' : spiceDir+'CommonSourcePairBulkUnconnected.spi'
, 'connectors' : ( 'D1', 'D2', 'S', 'G', 'B' )
, 'layouts' : ( ('Horizontal M2' , 'CSP_horizontalM2.py' )
, ('Symmetrical' , 'CSP_symmetrical.py' )
, ('Interdigitated' , 'CSP_interdigitated.py' )
, ('WIP CSP' , 'WIP_CSP.py' )
)
}
, { 'name' : 'SimpleCurrentMirrorBulkConnected'
, 'spice' : spiceDir+'CurrMirBulkConnected.spi'
, 'connectors' : ( 'D1', 'D2', 'S' )
, 'layouts' : ( ('Horizontal M2' , 'SCM_horizontalM2.py' )
, ('Symmetrical' , 'SCM_symmetrical.py' )
, ('Common centroid', 'SCM_2DCommonCentroid.py')
, ('Interdigitated' , 'SCM_interdigitated.py' )
)
}
, { 'name' : 'SimpleCurrentMirrorBulkUnconnected'
, 'spice' : spiceDir+'CurrMirBulkUnconnected.spi'
, 'connectors' : ( 'D1', 'D2', 'S', 'B' )
, 'layouts' : ( ('Horizontal M2' , 'SCM_horizontalM2.py' )
, ('Symmetrical' , 'SCM_symmetrical.py' )
, ('Common centroid', 'SCM_2DCommonCentroid.py')
, ('Interdigitated' , 'SCM_interdigitated.py' )
)
}
, { 'name' : 'MIMCapacitor'
, 'spice' : spiceDir+'MIMCapacitor.spi'
, 'connectors' : ( 'P1', 'P2' )
, 'layouts' : ( ('SimpleMatrix' , 'MIM_simpleMatrix.py' )
,
)
}
)

10
crlcore/etc/symbolic/cmos/analog.conf Normal file
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@ -0,0 +1,10 @@
# -*- Mode:Python; explicit-buffer-name: "analog.conf<common>" -*-
import helpers
parametersTable = \
( ('analog.techno' , TypeString, 'Analog_technology_is_disabled',
{ 'flags':Cfg.Parameter.Flags.NeedRestart|Cfg.Parameter.Flags.MustExist } )
, ('analog.devices', TypeString, helpers.technoDir+'/devices.conf' )
)

2
crlcore/python/CMakeLists.txt
View File

@ -7,3 +7,5 @@
install( FILES helpers/Patterns.py DESTINATION ${PYTHON_SITE_PACKAGES}/crlcore/helpers )
install( FILES helpers/Technology.py DESTINATION ${PYTHON_SITE_PACKAGES}/crlcore/helpers )
install( FILES helpers/Debug.py DESTINATION ${PYTHON_SITE_PACKAGES}/crlcore/helpers )
install( FILES helpers/Devices.py DESTINATION ${PYTHON_SITE_PACKAGES}/crlcore/helpers )
install( FILES helpers/AnalogTechno.py DESTINATION ${PYTHON_SITE_PACKAGES}/crlcore/helpers )

66
crlcore/python/coriolisInit.py
View File

@ -13,6 +13,7 @@ try:
from helpers import Configuration
from helpers import ErrorMessage
from helpers import WarningMessage
#from helpers import Devices
from helpers.Configuration import TypeBool
from helpers.Configuration import TypeInt
from helpers.Configuration import TypeEnumerate
@ -33,6 +34,8 @@ try:
from helpers.Display import Drawing
from helpers import Alliance
from helpers import Technology
from helpers import AnalogTechno
from helpers import Devices
import helpers.Display
except ImportError, e:
serror = str(e)
@ -106,11 +109,12 @@ def coriolisConfigure():
, (helpers.technoDir+'/kite.conf' , SystemFile|ConfigurationHelper|KiteHelper)
, (helpers.technoDir+'/stratus1.conf' , SystemFile|ConfigurationHelper)
, (helpers.technoDir+'/plugins.conf' , SystemFile|ConfigurationHelper)
, (helpers.technoDir+'/analog.conf' , SystemFile|ConfigurationHelper)
]
if os.getenv('HOME'):
confFiles += [ (os.getenv('HOME')+'/.coriolis2/settings.py', 0) ]
else:
w = WarningMessage(['The <HOME> environment variable is not defined, this is most unusual.'
w = WarningMessage(['The "HOME" environment variable is not defined, this is most unusual.'
,'It prevents the loading of ${HOME}/.coriolis2/settings.py'])
print w
@ -123,11 +127,11 @@ def coriolisConfigure():
if not os.path.isfile(confFile):
if confFlags & SystemFile:
print '[ERROR] Missing mandatory Coriolis2 system file:'
print ' <%s>' % confFile
print ' "%s"' % helpers.truncPath(confFile)
print ' Your installation may be broken. Trying to continue anyway...'
continue
print ' - Loading \"%s\".' % helpers.truncPath(confFile)
print ' - Loading "%s".' % helpers.truncPath(confFile)
execfile(confFile,moduleGlobals)
except Exception, e:
helpers.showPythonTrace( confFile, e )
@ -139,8 +143,8 @@ def coriolisConfigure():
else:
if confFlags & loaderFlags & HelpersMask:
if confFlags & SystemFile and loaderFlags & SystemMandatory:
print '[ERROR] Mandatory symbol <%s> is missing in system configuration file:' % symbol
print ' <%s>' % confFile
print '[ERROR] Mandatory symbol "%s" is missing in system configuration file:' % symbol
print ' "%s"' % helpers.truncPath(confFile)
print ' Trying to continue anyway...'
if confFile.endswith('settings.py'):
@ -160,4 +164,56 @@ def coriolisConfigure():
parameter.setString( mappingFile )
parameter.flags = Cfg.Parameter.Flags.NeedRestart|Cfg.Parameter.Flags.MustExist
confFile = None
if Cfg.hasParameter('analog.techno'):
confFile = Cfg.getParamString('analog.techno').asString()
if confFile == 'Analog_technology_has_not_been_set': confFile = None
if confFile == 'Analog_technology_is_disabled': return
if not confFile:
vendorTech = helpers.techno.split('/')[-1]
confFile = os.path.join( helpers.technoDir, 'dtr_%s.py'%vendorTech )
Cfg.getParamString('analog.techno').setString( confFile )
if not os.path.isfile(confFile):
print '[WARNING] Analog technology file (aka DTR) has not been found:'
print ' "%s"' % helpers.truncPath(confFile)
print ' Use of Coriolis analog is disabled.'
return
try:
if not helpers.quiet: print ' - Loading \"%s\".' % helpers.truncPath(confFile)
execfile(confFile,moduleGlobals)
except Exception, e:
showPythonTrace( confFile, e )
if moduleGlobals.has_key('analogTechnologyTable'):
AnalogTechno.loadAnalogTechno( moduleGlobals['analogTechnologyTable'], confFile )
del moduleGlobals['analogTechnologyTable']
else:
print '[ERROR] Mandatory symbol <%s> is missing in technology configuration file:' % 'analogTechnologyTable'
print ' "%s"' % helpers.truncPath(confFile)
sys.exit( 1 )
confFile = Cfg.getParamString('analog.devices').asString()
if not os.path.isfile(confFile):
print '[ERROR] Missing mandatory analog devices description file:'
print ' "%s"' % helpers.truncPath(confFile)
print ' Please look for the "analog.devices" parameter in configuration files.'
sys.exit( 1 )
try:
if not helpers.quiet: print ' - Loading \"%s\".' % helpers.truncPath(confFile)
execfile(confFile,moduleGlobals)
except Exception, e:
showPythonTrace( confFile, e )
if moduleGlobals.has_key('devicesTable'):
Devices.loadDevices( moduleGlobals['devicesTable'], confFile )
del moduleGlobals['devicesTable']
else:
print '[ERROR] Mandatory symbol "%s" is missing in technology configuration file:' % 'devicesTable'
print ' "%s"' % helpers.truncPath(confFile)
sys.exit( 1 )
return

118
crlcore/python/helpers/AnalogTechno.py Normal file
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@ -0,0 +1,118 @@
# -*- Mode:Python; explicit-buffer-name: "AnalogTechno.py<crlcore/helpers>" -*-
#
# This file is part of the Coriolis Software.
# Copyright (c) UPMC 2015-2018, All Rights Reserved
#
# +-----------------------------------------------------------------+
# | C O R I O L I S |
# | Alliance / Hurricane Interface |
# | |
# | Author : Jean-Paul CHAPUT |
# | E-mail : Jean-Paul.Chaput@lip6.fr |
# | =============================================================== |
# | Python : "./crlcore/python/helpers/AnalogTechno.py" |
# +-----------------------------------------------------------------+
import os
import os.path
import sys
import Hurricane
from Hurricane import DbU
from Hurricane import DataBase
from Hurricane import Layer
from helpers import ErrorMessage
from helpers import Debug
technoFile = '<technoFile has not been set>'
Length = 0x0001
Area = 0x0002
Asymmetric = 0x0004
Unit = 0x0008
def valueToDbU ( value, unit, lengthType ):
length = DbU.fromPhysical( value, unit )
if lengthType & Length: return length
area = DbU.fromPhysical( float(length), unit )
return area
def checkEntry ( entry, entryNo ):
if not isinstance(entry,tuple):
raise ErrorMessage( 1, [ 'Entry %d is malformed in <analogTechnologyTable>.' % entryNo
, 'Not a tuple (a, b, c, ...) or (a,).'
, str(entry)
] )
if not len(entry) in (4, 5, 6):
raise ErrorMessage( 1, [ 'Entry %d is malformed in <analogTechnologyTable>.' % entryNo
, 'Tuple must have *4*, *5* or *6* items only.'
, str(entry)
] )
if not entry[-2] in (Length, Length|Asymmetric, Area, Unit):
raise ErrorMessage( 1, [ 'Entry %d is malformed in <analogTechnologyTable>.' % entryNo
, 'Beforelast item is neither Length, Length|Asymmetric nor Area.'
, str(entry)
] )
return
def _loadAnalogTechno ( techno, ruleTable ):
unit = None
entryNo = 0
for entry in ruleTable:
entryNo += 1
try:
if entryNo > 1:
checkEntry( entry, entryNo )
if entry[0] == 'Header':
unit = entry[2]
techno.setName( entry[1] )
continue
# Zero-layer rule.
if len(entry) == 4:
if entry[2] & Unit:
techno.addUnitRule( entry[0], entry[1], entry[3] )
else:
techno.addPhysicalRule( entry[0]
, valueToDbU( entry[1], unit, entry[2] )
, entry[3]
)
# One-layer rule.
if len(entry) == 5:
techno.addPhysicalRule( entry[0]
, entry[1]
, valueToDbU( entry[2], unit, entry[3] )
, entry[4]
)
# Two-layer rule.
if len(entry) == 6:
symmetric = True
if entry[4] & Asymmetric: symmetric = False
techno.addPhysicalRule( entry[0]
, entry[1]
, entry[2]
, symmetric
, valueToDbU( entry[3], unit, entry[4] )
, entry[5]
)
except Exception, e:
ErrorMessage.wrapPrint(e,'In %s:<analogTechnologyTable> at index %d.' % (technoFile,entryNo))
return
def loadAnalogTechno ( table, fromFile ):
global technoFile
technoFile = fromFile
techno = DataBase.getDB().getTechnology()
_loadAnalogTechno( techno, table )
return

102
crlcore/python/helpers/Devices.py Normal file
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@ -0,0 +1,102 @@
# -*- Mode:Python; explicit-buffer-name: "Devices.py<crlcore/helpers>" -*-
#
# This file is part of the Coriolis Software.
# Copyright (c) UPMC 2015-2018, All Rights Reserved
#
# +-----------------------------------------------------------------+
# | C O R I O L I S |
# | Alliance / Hurricane Interface |
# | |
# | Author : Jean-Paul CHAPUT |
# | E-mail : Jean-Paul.Chaput@asim.lip6.fr |
# | =============================================================== |
# | Python : "./crlcore/python/helpers/Devices.py" |
# +-----------------------------------------------------------------+
import os
import os.path
import sys
from Hurricane import DataBase
from helpers import ErrorMessage
from helpers import Debug
devicesFile = '<devicesFile has not been set>'
def checkEntry ( entry, entryNo ):
if not isinstance(entry,dict):
raise ErrorMessage( 1, [ 'Entry %d is malformed in <devicesTable>.' % entryNo
, 'Not a dictionnary { key1:value1, key2:value2 }.'
, str(entry)
] )
if not entry.has_key('name'):
raise ErrorMessage( 1, [ 'Entry %d is malformed in <devicesTable>.' % entryNo
, 'Dictionnary is missing the <name> key/value pair.'
, str(entry)
] )
if not entry.has_key('spice'):
raise ErrorMessage( 1, [ 'Entry %d is malformed in <devicesTable>.' % entryNo
, 'Dictionnary is missing the <spice> key/value pair.'
, str(entry)
] )
if not entry.has_key('connectors'):
raise ErrorMessage( 1, [ 'Entry %d is malformed in <devicesTable>.' % entryNo
, 'Dictionnary is missing the <connectors> key/value pair.'
, str(entry)
] )
if not entry.has_key('layouts'):
raise ErrorMessage( 1, [ 'Entry %d is malformed in <devicesTable>.' % entryNo
, 'Dictionnary is missing the <layouts> key/value pair.'
, str(entry)
] )
if not isinstance(entry['connectors'],tuple):
raise ErrorMessage( 1, [ 'Entry %d is malformed in <devicesTable>.' % entryNo
, 'The <connectors> value is not a *tuple*.'
, str(entry)
] )
layouts = entry['layouts']
if not isinstance(layouts,tuple):
raise ErrorMessage( 1, [ 'Entry %d is malformed in <devicesTable>.' % entryNo
, 'The <layout> value is not a *tuple*.'
, str(entry)
] )
for layout in layouts:
if not isinstance(layout,tuple) or len(layout) != 2:
raise ErrorMessage( 1, [ 'Entry %d is malformed in <devicesTable>.' % entryNo
, 'One <layout> item is not a two element *tuple*.'
, str(entry)
] )
return
def _loadDevices ( techno, ruleTable ):
unit = None
entryNo = 0
for entry in ruleTable:
entryNo += 1
try:
checkEntry( entry, entryNo )
devDesc = techno.addDeviceDescriptor( entry['name'] )
devDesc.setSpiceFilePath( entry['spice'] )
for connector in entry['connectors']:
devDesc.addConnector( connector )
for layout in entry['layouts']:
devDesc.addLayout( layout[0], layout[1] )
except Exception, e:
ErrorMessage.wrapPrint(e,'In %s:<devicesTable> at index %d.' % (devicesFile,entryNo))
return
def loadDevices ( table, fromFile ):
global devicesFile
devicesFile = fromFile
techno = DataBase.getDB().getTechnology()
_loadDevices( techno, table )
return

11
crlcore/python/helpers/__init__.py
View File

@ -46,9 +46,16 @@ def isderived ( derived, base ):
return False
def truncPath ( path, maxlength=70 ):
def truncPath ( path, maxlength=80 ):
if len(path) < maxlength: return path
return '.../'+os.sep.join(path.split(os.sep)[-4:])
components = path.split(os.sep)
trunc = ''
for i in range(-1,-len(components),-1):
if len(trunc)+len(components[i]) >= maxlength: break
if not len(trunc): trunc = components[i]
else: trunc = os.path.join( components[i], trunc )
return '...' + os.sep + trunc
def showPythonTrace ( scriptPath=None, e=None, tryContinue=True ):

4
crlcore/src/ccore/Utilities.cpp
View File

@ -318,14 +318,14 @@ namespace CRL {
Utilities::Path crlcoreDir = pythonSitePackages / "crlcore";
Utilities::Path stratusDir = pythonSitePackages / "stratus";
Utilities::Path cumulusDir = pythonSitePackages / "cumulus";
Utilities::Path pharosDir = pythonSitePackages / "pharos";
Utilities::Path oroshiDir = pythonSitePackages / "oroshi";
Isobar::Script::addPath ( sysConfDir.toString() );
Isobar::Script::addPath ( pythonSitePackages.toString() );
Isobar::Script::addPath ( crlcoreDir.toString() );
Isobar::Script::addPath ( stratusDir.toString() );
Isobar::Script::addPath ( cumulusDir.toString() );
Isobar::Script::addPath ( pharosDir.toString() );
Isobar::Script::addPath ( oroshiDir.toString() );
// Triggers Configuration singleton creation.
Cfg::Configuration::get ();

11
documentation/Analog/Analog.rst Normal file
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@ -0,0 +1,11 @@
.. -*- Mode: rst -*-
.. include:: ../etc/definitions.rst
==========================
Hurricane/Analog Reference
==========================
The Viewer C++ API reference is generated by Doxygen_ and is
available here: `Hurricane/Analog <file:../../analog/index.html>`_

11
documentation/Oroshi/Oroshi.rst Normal file
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@ -0,0 +1,11 @@
.. -*- Mode: rst -*-
.. include:: ../etc/definitions.rst
================
Oroshi Reference
================
The Oroshi Python API reference is generated by Doxygen_ and is
available here: `Oroshi <file:../../oroshi/index.html>`_

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