From 37252175ed80558d460a0a091772d8bf6c999f54 Mon Sep 17 00:00:00 2001 From: Damien Dupuis Date: Fri, 6 May 2011 09:25:32 +0000 Subject: [PATCH] A very simple "drive what I have parsed" example (C++ only): usual examples will follow --- vlsisapd/examples/CMakeLists.txt | 1 + vlsisapd/examples/spice/CMakeLists.txt | 9 + vlsisapd/examples/spice/OTA.cir | 100 +++++++++++ .../examples/spice/cplusplus/CMakeLists.txt | 10 ++ vlsisapd/examples/spice/cplusplus/cmake.ex | 17 ++ .../examples/spice/cplusplus/parseSpice.cpp | 168 ++++++++++++++++++ vlsisapd/examples/spice/np_mos.spi | 77 ++++++++ vlsisapd/examples/spice/otaTwoStage.spi | 28 +++ 8 files changed, 410 insertions(+) create mode 100644 vlsisapd/examples/spice/CMakeLists.txt create mode 100644 vlsisapd/examples/spice/OTA.cir create mode 100644 vlsisapd/examples/spice/cplusplus/CMakeLists.txt create mode 100644 vlsisapd/examples/spice/cplusplus/cmake.ex create mode 100644 vlsisapd/examples/spice/cplusplus/parseSpice.cpp create mode 100644 vlsisapd/examples/spice/np_mos.spi create mode 100644 vlsisapd/examples/spice/otaTwoStage.spi diff --git a/vlsisapd/examples/CMakeLists.txt b/vlsisapd/examples/CMakeLists.txt index abfa2611..0efb27ba 100644 --- a/vlsisapd/examples/CMakeLists.txt +++ b/vlsisapd/examples/CMakeLists.txt @@ -3,3 +3,4 @@ ADD_SUBDIRECTORY(agds) ADD_SUBDIRECTORY(dtr) ADD_SUBDIRECTORY(openChams) ADD_SUBDIRECTORY(liberty) +ADD_SUBDIRECTORY(spice) diff --git a/vlsisapd/examples/spice/CMakeLists.txt b/vlsisapd/examples/spice/CMakeLists.txt new file mode 100644 index 00000000..5809bd62 --- /dev/null +++ b/vlsisapd/examples/spice/CMakeLists.txt @@ -0,0 +1,9 @@ +ADD_SUBDIRECTORY(cplusplus) +#ADD_SUBDIRECTORY(python) + +SET ( SP_FILES OTA.cir + np_mos.spi + otaTwoStage.spi + ) + +INSTALL ( FILES ${SP_FILES} DESTINATION share/doc/coriolis2/examples/vlsisapd/spice ) diff --git a/vlsisapd/examples/spice/OTA.cir b/vlsisapd/examples/spice/OTA.cir new file mode 100644 index 00000000..97acfc73 --- /dev/null +++ b/vlsisapd/examples/spice/OTA.cir @@ -0,0 +1,100 @@ +CARACTERISATION_OTA_CASCODE_SIMPLE_REPLIE + +* alimentations * +vdd evdd 0 3.300000 +vss evss 0 0.000000 +gfoncd evdd 0 evdd 0 1.0e-15 + +* acces aux modeles de simulation * +.include /users/cao/porte/OCEAN/oceane/share/envtech/modeles/proprietaires/ams0.35/eldo_bsim3v3 + +* dispositif principal * + +.SUBCKT OTACSRND1 ep em sp evp1 evp2 evc1 evc3 evdd evss +*infoceane:netpolar evp1 evp2 evc1 evc3 +MN1 nbi1c_1 ep 2_1 evss modn_typ W=1.75000u L=1.95000u M=10 ++ ad=1.066p as=2.132p pd=2.977u ps=5.954u ++ nrs=0.000 nrd=0.000 +MN2 nbi2c_1 em 2_1 evss modn_typ W=1.75000u L=1.95000u M=10 ++ ad=1.066p as=2.132p pd=2.977u ps=5.954u ++ nrs=0.000 nrd=0.000 +MN5 2_1 evp1 evss evss modn_typ W=4.45000u L=2.65000u M=12 ++ ad=2.686p as=5.372p pd=5.677u ps=11.354u ++ nrs=0.000 nrd=0.000 +MP1C ndm1c_1 evc1 nbi1c_1 nbi1c_1 modp_typ W=8.45000u L=1.95000u M=6 ++ ad=5.093p as=10.186p pd=9.688u ps=19.377u ++ nrs=0.000 nrd=0.000 +D_MP1C evss nbi1c_1 dwell_sub AREA=113.295p PJ=43.100u +MP2C sp evc1 nbi2c_1 nbi2c_1 modp_typ W=8.45000u L=1.95000u M=6 ++ ad=5.093p as=10.186p pd=9.688u ps=19.377u ++ nrs=0.000 nrd=0.000 +D_MP2C evss nbi2c_1 dwell_sub AREA=113.295p PJ=43.100u +MP7 nbi1c_1 evp2 evdd evdd modp_typ W=17.40000u L=1.95000u M=6 ++ ad=10.463p as=20.926p pd=18.638u ps=37.277u ++ nrs=0.000 nrd=0.000 +D_MP7 evss evdd dwell_sub AREA=194.740p PJ=61.000u +MP8 nbi2c_1 evp2 evdd evdd modp_typ W=17.40000u L=1.95000u M=6 ++ ad=10.463p as=20.926p pd=18.638u ps=37.277u ++ nrs=0.000 nrd=0.000 +D_MP8 evss evdd dwell_sub AREA=194.740p PJ=61.000u +MN3 nbi3c_1 ndm1c_1 evss evss modn_typ W=0.50000u L=2.65000u M=2 ++ ad=0.316p as=0.474p pd=1.727u ps=2.590u ++ nrs=0.000 nrd=0.000 +MN4 nbi4c_1 ndm1c_1 evss evss modn_typ W=0.50000u L=2.65000u M=2 ++ ad=0.316p as=0.474p pd=1.727u ps=2.590u ++ nrs=0.000 nrd=0.000 +MN3C ndm1c_1 evc3 nbi3c_1 evss modn_typ W=1.75000u L=1.95000u M=10 ++ ad=1.066p as=2.132p pd=2.977u ps=5.954u ++ nrs=0.000 nrd=0.000 +MN4C sp evc3 nbi4c_1 evss modn_typ W=1.75000u L=1.95000u M=10 ++ ad=1.066p as=2.132p pd=2.977u ps=5.954u ++ nrs=0.000 nrd=0.000 +.ENDS OTACSRND1 +* +XOTACSRND1 ep em sp evp1 evp2 evc1 evc3 evdd evss OTACSRND1 +* + +* dispositif auxiliaire 1 * +.SUBCKT POLAR_OTACSRND1 evp1 evp2 evc1 evc3 evdd evss +vp1 evp1 0 0.6830 +vp2 evp2 0 2.4598 +vc1 evc1 0 2.1580 +vc3 evc3 0 1.8255 +rfonc_vdd evdd 0 1.0e15 +rfonc_vss evss 0 1.0e15 +.ENDS POLAR_OTACSRND1 +* +XPOLAR_OTACSRND1 evp1 evp2 evc1 evc3 evdd evss POLAR_OTACSRND1 +* + +* dispositif auxiliaire 3 * +.SUBCKT CHARGE_OTACSRND1 sp smc +CL sp smc 3.000000e-12 +.ENDS CHARGE_OTACSRND1 +* +XCHARGE_OTACSRND1 sp smc CHARGE_OTACSRND1 +* + +* mode commun en entree * +vemc emc 0 1.650000 + +* mode commun en sortie * +vsmc smc 0 1.650000 + +* determination des points de repos * +vcct sp em dc 0.000000 +vop ep emc dc 0.0 +.op + +* options de simulation * +.option nowavecomplex stat=3 nomod analog eps=1.0e-6 numdgt=8 + +* temperature de simulation * +.temp 27.00 + +.nodeset v(sp)=1.650000 + + +* fin de fichier * +.end + diff --git a/vlsisapd/examples/spice/cplusplus/CMakeLists.txt b/vlsisapd/examples/spice/cplusplus/CMakeLists.txt new file mode 100644 index 00000000..6481b93d --- /dev/null +++ b/vlsisapd/examples/spice/cplusplus/CMakeLists.txt @@ -0,0 +1,10 @@ +INCLUDE_DIRECTORIES ( ${VLSISAPD_SOURCE_DIR}/src/spice/src ) +#ADD_EXECUTABLE ( driveSpice driveSpice.cpp ) +ADD_EXECUTABLE ( parseSpice parseSpice.cpp ) +#TARGET_LINK_LIBRARIES ( driveSpice spice ) # 'driveSpice' is the name of the executable and 'spice' the name of the target library in openChams/src/CMakeLists.txt +TARGET_LINK_LIBRARIES ( parseSpice spice ) +#INSTALL ( TARGETS driveSpice parseSpice DESTINATION share/doc/coriolis2/examples/vlsisapd/spice ) +#INSTALL ( FILES driveSpice.cpp parseSpice.cpp DESTINATION share/doc/coriolis2/examples/vlsisapd/spice ) +INSTALL ( TARGETS parseSpice DESTINATION share/doc/coriolis2/examples/vlsisapd/spice ) +INSTALL ( FILES parseSpice.cpp DESTINATION share/doc/coriolis2/examples/vlsisapd/spice ) +INSTALL ( FILES cmake.ex DESTINATION share/doc/coriolis2/examples/vlsisapd/spice RENAME CMakeLists.txt ) diff --git a/vlsisapd/examples/spice/cplusplus/cmake.ex b/vlsisapd/examples/spice/cplusplus/cmake.ex new file mode 100644 index 00000000..2d749376 --- /dev/null +++ b/vlsisapd/examples/spice/cplusplus/cmake.ex @@ -0,0 +1,17 @@ +PROJECT(PARSEDRIVESPICE) + +CMAKE_MINIMUM_REQUIRED(VERSION 2.4.0) + +SET(CMAKE_MODULE_PATH "$ENV{VLSISAPD_USER_TOP}/share/cmake/Modules" + "$ENV{VLSISAPD_TOP}/share/cmake/Modules" + ) + +FIND_PACKAGE(VLSISAPD REQUIRED) + +IF(SPICE_FOUND) + INCLUDE_DIRECTORIES(${SPICE_INCLUDE_DIR}) +# ADD_EXECUTABLE(driveSpice driveSpice.cpp) + ADD_EXECUTABLE(parseSpice parseSpice.cpp) +# TARGET_LINK_LIBRARIES(driveOpenChams ${SPICE_LIBRARY}) + TARGET_LINK_LIBRARIES(parseOpenChams ${SPICE_LIBRARY}) +ENDIF(SPICE_FOUND) diff --git a/vlsisapd/examples/spice/cplusplus/parseSpice.cpp b/vlsisapd/examples/spice/cplusplus/parseSpice.cpp new file mode 100644 index 00000000..ea214942 --- /dev/null +++ b/vlsisapd/examples/spice/cplusplus/parseSpice.cpp @@ -0,0 +1,168 @@ +#include +#include +#include +#include +using namespace std; + +#include "vlsisapd/spice/Circuit.h" +#include "vlsisapd/spice/SpiceException.h" + +int main(int argc, char * argv[]) { + string file = ""; + if (argc == 1) + file = "./OTA.cir"; + else if (argc == 2) + file = argv[1]; + else { + cerr << "Usage: parseSpice [filename]" << endl; + exit(1); + } + + SPICE::Circuit* circuit = NULL; + try { + circuit = SPICE::Circuit::readFromFile(file); + } catch (SPICE::SpiceException& e) { + cerr << e.what() << endl; + exit(48); + } + +// if (!circuit) cerr << "circuit is NULL !!" << endl; + cerr << circuit->getTitle() << endl; + circuit->writeToFile("./myTest.spi"); +// cerr << " + parameters" << endl; +// OpenChams::Parameters params = circuit->getParameters(); +// if (!params.isEmpty()) { +// for (map::const_iterator it = params.getValues().begin() ; it != params.getValues().end() ; ++it) { +// cerr << " | | " << ((*it).first).getString() << " : " << (*it).second << endl; +// } +// for (map::const_iterator it = params.getEqValues().begin() ; it != params.getEqValues().end() ; ++it) { +// cerr << " | | " << ((*it).first).getString() << " : " << (*it).second << endl; +// } +// } +// cerr << " + netlist" << endl; +// cerr << " | + instances" << endl; +// OpenChams::Netlist* netlist = circuit->getNetlist(); +// if (netlist && !netlist->hasNoInstances()) { +// for (size_t i = 0 ; i < netlist->getInstances().size() ; i++) { +// OpenChams::Instance* inst = netlist->getInstances()[i]; +// OpenChams::Device* dev = NULL; +// if (dynamic_cast(inst)) { +// dev = static_cast(inst); +// cerr << " | | + " << dev->getName().getString() << " : " << dev->getModel().getString() << " - " << dev->getMosType().getString() << " - " << (dev->isSourceBulkConnected()?"true":"false") << endl; +// } else { +// cerr << " | | + " << inst->getName().getString() << " : " << inst->getModel().getString() << endl; +// } +// cerr << " | | | + connectors" << endl; +// for (map::const_iterator cit = inst->getConnectors().begin() ; cit != inst->getConnectors().end() ; ++cit) { +// if ((*cit).second) +// cerr << " | | | | " << ((*cit).first).getString() << " : " << ((*cit).second)->getName().getString() << endl; +// else +// cerr << " | | | | " << ((*cit).first).getString() << endl; // no net connected ! +// } +// if (dev) { +// cerr << " | | | + transistors" << endl; +// for (size_t j = 0 ; j < dev->getTransistors().size() ; j++) { +// OpenChams::Transistor* tr = dev->getTransistors()[j]; +// cerr << " | | | | name: " << tr->getName().getString() << " - gate: " << tr->getGate().getString() << " - source: " << tr->getSource().getString() << " - drain: " << tr->getDrain().getString() << " - bulk: " << tr->getBulk().getString() << endl; +// } +// } +// } +// } +// cerr << " | + nets" << endl; +// bool schematicNet = false; // define wether net sections are needed in schematic section +// if (!netlist->hasNoNets()) { +// for (size_t i = 0 ; i < netlist->getNets().size() ; i++) { +// OpenChams::Net* net = netlist->getNets()[i]; +// cerr << " | | + " << net->getName().getString() << " : " << net->getType().getString() << " - " << (net->isExternal()?"true":"false") << endl; +// cerr << " | | | + connections" << endl; +// for (size_t j = 0 ; j < net->getConnections().size() ; j++) { +// OpenChams::Net::Connection* connect = net->getConnections()[j]; +// cerr << " | | | | " << connect->getInstanceName().getString() << "." << connect->getConnectorName().getString() << endl; +// } +// if (!net->hasNoPorts() || !net->hasNoWires()) +// schematicNet = true; +// } +// } +// OpenChams::Schematic* schematic = circuit->getSchematic(); +// if (schematic && !schematic->hasNoInstances()) { +// cerr << " + schematic" << endl; +// for (map::const_iterator sit = schematic->getInstances().begin() ; sit != schematic->getInstances().end() ; ++sit) { +// OpenChams::Schematic::Infos* inf = (*sit).second; +// cerr << " | + instance: name: " << ((*sit).first).getString() << " - x: " << inf->getX() << " - y: " << inf->getY() << " - orientation: " << inf->getOrientation().getString() << endl; +// } +// if (schematicNet) { +// for (size_t i = 0 ; i < netlist->getNets().size() ; i++) { +// OpenChams::Net* net = netlist->getNets()[i]; +// cerr << " | + net name: " << net->getName().getString() << endl; +// if (!net->hasNoPorts()) { +// for (size_t j = 0 ; j < net->getPorts().size() ; j++) { +// OpenChams::Port* port = net->getPorts()[j]; +// cerr << " | | + port type: " << port->getType().getString() << " - idx: " << port->getIndex() << " - x: " << port->getX() << " - y: " << port->getY() << " - orientation: " << port->getOrientation().getString() << endl; +// } +// } +// if (!net->hasNoWires()) { +// for (size_t j = 0 ; j < net->getWires().size() ; j++) { +// OpenChams::Wire* wire = net->getWires()[j]; +// cerr << " | | + wire "; +// OpenChams::WirePoint* start = wire->getStartPoint(); +// if (dynamic_cast(start)) { +// OpenChams::InstancePoint* iP = static_cast(start); +// cerr << "<" << iP->getName().getString() << "," << iP->getPlug().getString() << "> "; +// } else if (dynamic_cast(start)) { +// OpenChams::PortPoint* pP = static_cast(start); +// cerr << "<" << pP->getIndex() << "> "; +// } +// for (size_t k = 0 ; k < wire->getIntermediatePoints().size() ; k++) { +// OpenChams::IntermediatePoint* iP = wire->getIntermediatePoints()[k]; +// cerr << "<" << iP->getX() << "," << iP->getY() << "> "; +// } +// OpenChams::WirePoint* end = wire->getEndPoint(); +// if (dynamic_cast(end)) { +// OpenChams::InstancePoint* iP = static_cast(end); +// cerr << "<" << iP->getName().getString() << "," << iP->getPlug().getString() << "> "; +// } else if (dynamic_cast(end)) { +// OpenChams::PortPoint* pP = static_cast(end); +// cerr << "<" << pP->getIndex() << "> "; +// } +// cerr << endl; +// } +// } +// +// } +// } +// +// } +// OpenChams::Sizing* sizing = circuit->getSizing(); +// if (sizing) { +// cerr << " + sizing" << endl; +// if (!sizing->hasNoOperators()) { +// for (map::const_iterator oit = sizing->getOperators().begin() ; oit != sizing->getOperators().end() ; ++oit) { +// OpenChams::Operator* op = (*oit).second; +// cerr << " | + instance name: " << ((*oit).first).getString() << " - operator: " << op->getName().getString() << " - simulModel: " << op->getSimulModel().getString() << " - callOrder: " << op->getCallOrder() << endl; +// if (!op->hasNoConstraints()) { +// for (map::const_iterator cit = op->getConstraints().begin() ; cit != op->getConstraints().end() ; ++cit) { +// OpenChams::Operator::Constraint* cstr = (*cit).second; +// cerr << " | | + param: " << ((*cit).first).getString() << " - ref: " << cstr->getRef().getString() << " - refParam: " << cstr->getRefParam().getString() << " - factor: " << cstr->getFactor() << endl; +// } +// } +// } +// } +// if (!sizing->hasNoEquations()) { +// cerr << " | + equations" << endl; +// for (map::const_iterator eit = sizing->getEquations().begin() ; eit != sizing->getEquations().end() ; ++eit) { +// cerr << " | | " << ((*eit).first).getString() << " : " << (*eit).second << endl; +// } +// } +// } +// OpenChams::Layout* layout = circuit->getLayout(); +// if (layout && !layout->hasNoInstance()) { +// cerr << " + layout" << endl; +// for (map::const_iterator lit = layout->getInstances().begin() ; lit != layout->getInstances().end() ; ++lit) { +// cerr << " | | instance name: " << ((*lit).first).getString() << " - style: " << ((*lit).second).getString() << endl; +// } +// } +// +// + return 0; +} + diff --git a/vlsisapd/examples/spice/np_mos.spi b/vlsisapd/examples/spice/np_mos.spi new file mode 100644 index 00000000..45c99a0f --- /dev/null +++ b/vlsisapd/examples/spice/np_mos.spi @@ -0,0 +1,77 @@ +* NMOS-PMOS netlist for CHAMS sizing & biasing + +.param MOSLL_DEV=0 +.param PARAMCHK=1 + +.LIB ~techno/dev/grenoble/hcmos9/modeles_mars03/common_poly.lib PRO_stat +.LIB ~techno/dev/grenoble/hcmos9/modeles_mars03/common_active.lib PRO_stat +.LIB ~techno/dev/grenoble/hcmos9/modeles_mars03/common_go1.lib PRO_stat +.LIB ~techno/dev/grenoble/hcmos9/modeles_mars03/mos_bsim3_LL.lib mosLL_stat +*.LIB ~/stage_Ngspice/ngspice_chams_test_US/ST130nm/design_kit/mos_bsim3_LL.lib mosll_stat + +.option numdgt = 15 +.option noqtrunc +*.option numdgt = 15 post_double +*.option printlg = 15 +*.option numdgt = 6 eps=1.0e-9 + +*----------------------------------------------------------- +* NMOS + +.param VDSN_VAL = 0.8 +.param VGSN_VAL = 0.8 +.param VBSN_VAL = 0.425 +.param NFINGN_VAL = 1 +.param WN_VAL = 2.0e-6 +.param LN_VAL = 1.5e-6 + +.param AD_N_VAL = 5.2125e-13 +.param AS_N_VAL = 5.2125e-13 +.param PD_N_VAL = 2.195e-06 +.param PS_N_VAL = 2.195e-06 +.param PO2ACT_N_VAL = -1 + +XMN dn gn sn bn ENLLGP_BS3JU w=WN_VAL l=LN_VAL nfing=NFINGN_VAL ++ ad=AD_N_VAL as=AS_N_VAL pd=PD_N_VAL ps=PS_N_VAL ++ po2act=PO2ACT_N_VAL + +vdsn dn sn VDSN_VAL +vgsn gn sn VGSN_VAL +vbsn bn sn VBSN_VAL +vsn sn 0 0.0 + +*----------------------------------------------------------- +* PMOS + +.param VDSP_VAL = -0.8 +.param VGSP_VAL = -0.8 +.param VBSP_VAL = 0.698 +.param NFINGP_VAL = 1 +.param WP_VAL = 2.0e-6 +.param LP_VAL = 1.5e-6 + +.param AD_P_VAL = 6.95e-13 +.param AS_P_VAL = 6.95e-13 +.param PD_P_VAL = 2.695e-06 +.param PS_P_VAL = 2.695e-06 +.param PO2ACT_P_VAL = -1 + +XMP dp gp sp bp EPLLGP_BS3JU w=WP_VAL l=LP_VAL nfing=NFINGP_VAL ++ ad=AD_P_VAL as=AS_P_VAL pd=PD_P_VAL ps=PS_P_VAL ++ po2act=PO2ACT_P_VAL + +vdsp dp sp VDSP_VAL +vgsp gp sp VGSP_VAL +vbsp bp sp VBSP_VAL +vsp sp 0 0.0 + +*----------------------------------------------------------- + +* temperature +.param TEMP_VAL = 27.0 +.temp TEMP_VAL + +* analysis +.op + +.end diff --git a/vlsisapd/examples/spice/otaTwoStage.spi b/vlsisapd/examples/spice/otaTwoStage.spi new file mode 100644 index 00000000..a610c529 --- /dev/null +++ b/vlsisapd/examples/spice/otaTwoStage.spi @@ -0,0 +1,28 @@ +* Single-ended two-stage amplifier + +.INCLUDE paramsFile.spi + +.INCLUDE ota2et_cm_m3_m4.spi +.INCLUDE ota2et_dp_m1_m2.spi +.INCLUDE ota2et_tr_m7.spi +.INCLUDE ota2et_tr_m6.spi +.INCLUDE ota2et_tr_m5.spi +.INCLUDE ota2et_tr_m8.spi + +.subckt ota2et 4 8 9 5 6 7 + +xota2et_cm_m3_m4 5 5 2 1 ota2et_cm_m3_m4 l_val=L_CM w_val=W_CM nf_val=1 tr_name="psvtlp_TT" temp_val=27 aeq_val=100e-6 +xota2et_dp_m1_m2 9 3 7 6 2 1 ota2et_dp_m1_m2 l_val=L_DP w_val=W_DP nf_val=1 tr_name="nsvtlp_TT" temp_val=27 aeq_val=100e-6 +xota2et_tr_m7 9 4 8 ota2et_tr_m7 l_val=L_M7 w_val=W_M7 nf_val=1 tr_name="nsvtlp_TT" temp_val=27 aeq_val=100e-6 +xota2et_tr_m6 5 2 8 ota2et_tr_m6 l_val=L_M6 w_val=W_M6 nf_val=1 tr_name="psvtlp_TT" temp_val=27 aeq_val=100e-6 +xota2et_tr_m5 9 4 3 ota2et_tr_m5 l_val=L_M5 w_val=W_M5 nf_val=1 tr_name="nsvtlp_TT" temp_val=27 aeq_val=100e-6 +xota2et_tr_m8 9 4 4 ota2et_tr_m8 l_val=L_M8 w_val=W_M8 nf_val=1 tr_name="nsvtlp_TT" temp_val=27 aeq_val=100e-6 + +* Initial values for CC and RC : +*CC 8 285 1.9pF +*RC 285 2 673 + +CC 8 285 0.9pF +RC 285 2 673 + +.ends ota2et