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Adding support for Port and Wire objects in openChams paser / driver. 

Examples have been (partially) updated.
This commit is contained in:
Damien Dupuis 2011-02-15 13:57:39 +00:00
parent 628057f7bb
commit 360e8d5348
21 changed files with 758 additions and 86 deletions
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50
vlsisapd/examples/openChams/buffer.xml
View File

@ -1,8 +1,8 @@
<?xml version="1.0" encoding="UTF-8"?>
<circuit name="buffer" techno="myTech">
<subCircuitsPathes>
<subCircuitsPaths>
<path path="."/>
</subCircuitsPathes>
</subCircuitsPaths>
<netlist>
<instances>
<instance name="inv1" model="inverter">
@ -43,4 +43,50 @@
</net>
</nets>
</netlist>
<schematic>
<instance name="inv1" x="2490" y="2600" sym="ID"/>
<instance name="inv2" x="2490" y="2300" sym="ID"/>
<net name="in">
<port type="inV" idx="0" x="2415" y="2700" sym="MY"/>
<wire>
<connector name="inv1" plug="in"/>
<connector idx="0"/>
</wire>
</net>
<net name="internal">
<wire>
<connector name="inv1" plug="out"/>
<connector name="inv2" plug="in"/>
</wire>
</net>
<net name="out">
<port type="outV" idx="0" x="2415" y="2200" sym="MY"/>
<wire>
<connector name="inv2" plug="out"/>
<connector idx="0"/>
</wire>
</net>
<net name="vdd">
<port type="inH" idx="0" x="2200" y="2500" sym="ID"/>
<wire>
<connector idx="0"/>
<connector name="inv2" plug="vdd"/>
</wire>
<wire>
<connector name="inv1" plug="vdd"/>
<connector name="inv2" plug="vdd"/>
</wire>
</net>
<net name="vss">
<port type="inH" idx="0" x="2700" y="2500" sym="MX"/>
<wire>
<connector idx="0"/>
<connector name="inv2" plug="vss"/>
</wire>
<wire>
<connector name="inv1" plug="vss"/>
<connector name="inv2" plug="vss"/>
</wire>
</net>
</schematic>
</circuit>

27
vlsisapd/examples/openChams/cplusplus/driveOpenChams.cpp
View File

@ -11,6 +11,8 @@ using namespace std;
#include "vlsisapd/openChams/Sizing.h"
#include "vlsisapd/openChams/Operator.h"
#include "vlsisapd/openChams/Layout.h"
#include "vlsisapd/openChams/Port.h"
#include "vlsisapd/openChams/Wire.h"
int main(int argc, char * argv[]) {
OpenChams::Circuit* circuit = new OpenChams::Circuit(OpenChams::Name("design"), OpenChams::Name("myTech"));
@ -60,9 +62,32 @@ int main(int argc, char * argv[]) {
_out->connectTo(OpenChams::Name("pmos1"), OpenChams::Name("D"));
// schematic
OpenChams::Schematic* schematic = circuit->createSchematic(1.0);
OpenChams::Schematic* schematic = circuit->createSchematic();
schematic->addInstance(OpenChams::Name("nmos1"), 2490, 2600, OpenChams::Name("ID"));
schematic->addInstance(OpenChams::Name("pmos1"), 2490, 2300, OpenChams::Name("ID"));
_vdd->addPort(OpenChams::Name("inV"), 0, 2490, 2100, OpenChams::Name("ID"));
OpenChams::Wire* wVdd = _vdd->addWire();
wVdd->setStartPoint(OpenChams::Name("pmos1"), OpenChams::Name("S"));
wVdd->setEndPoint (0);
_vss->addPort(OpenChams::Name("inV"), 0, 2490, 2800, OpenChams::Name("MY"));
OpenChams::Wire* wVss = _vss->addWire();
wVss->setStartPoint(OpenChams::Name("nmos1"), OpenChams::Name("S"));
wVss->setEndPoint (0);
_in->addPort(OpenChams::Name("inH"), 0, 2190, 2500, OpenChams::Name("ID"));
OpenChams::Wire* wIn = _in->addWire();
wIn->setStartPoint(OpenChams::Name("pmos1"), OpenChams::Name("G"));
wIn->setEndPoint (OpenChams::Name("nmos1"), OpenChams::Name("G"));
OpenChams::Wire* wIn1 = _in->addWire();
wIn1->setStartPoint(0);
wIn1->setEndPoint (OpenChams::Name("pmos1"), OpenChams::Name("G"));
_out->addPort(OpenChams::Name("outH"), 0, 2600, 2500, OpenChams::Name("ID"));
OpenChams::Wire* wOut = _out->addWire();
wOut->setStartPoint(OpenChams::Name("pmos1"), OpenChams::Name("D"));
wOut->setEndPoint (OpenChams::Name("nmos1"), OpenChams::Name("D"));
OpenChams::Wire* wOut1 = _out->addWire();
wOut1->setStartPoint(OpenChams::Name("nmos1"), OpenChams::Name("D"));
wOut1->setEndPoint (0);
// sizing
OpenChams::Sizing* sizing = circuit->createSizing();
OpenChams::Operator* op_pmos1 = sizing->addOperator(OpenChams::Name("pmos1"), OpenChams::Name("OPVG(Veg)"), OpenChams::Name("BSIM3V3"), 0);

50
vlsisapd/examples/openChams/cplusplus/parseOpenChams.cpp
View File

@ -16,6 +16,8 @@ using namespace std;
#include "vlsisapd/openChams/Sizing.h"
#include "vlsisapd/openChams/Operator.h"
#include "vlsisapd/openChams/Layout.h"
#include "vlsisapd/openChams/Port.h"
#include "vlsisapd/openChams/Wire.h"
#include "vlsisapd/openChams/OpenChamsException.h"
int main(int argc, char * argv[]) {
@ -78,6 +80,7 @@ int main(int argc, char * argv[]) {
}
}
cerr << " | + nets" << endl;
bool schematicNet = false; // define wether net sections are needed in schematic section
if (!netlist->hasNoNets()) {
for (size_t i = 0 ; i < netlist->getNets().size() ; i++) {
OpenChams::Net* net = netlist->getNets()[i];
@ -87,15 +90,58 @@ int main(int argc, char * argv[]) {
OpenChams::Net::Connection* connect = net->getConnections()[j];
cerr << " | | | | " << connect->getInstanceName().getString() << "." << connect->getConnectorName().getString() << endl;
}
if (!net->hasNoPorts() || !net->hasNoWires())
schematicNet = true;
}
}
OpenChams::Schematic* schematic = circuit->getSchematic();
if (schematic && !schematic->hasNoInstances()) {
cerr << " + schematic - zoom: " << schematic->getZoom() << endl;
cerr << " + schematic" << endl;
for (map<OpenChams::Name, OpenChams::Schematic::Infos*>::const_iterator sit = schematic->getInstances().begin() ; sit != schematic->getInstances().end() ; ++sit) {
OpenChams::Schematic::Infos* inf = (*sit).second;
cerr << " | name: " << ((*sit).first).getString() << " - x: " << inf->getX() << " - y: " << inf->getY() << " - symmetry: " << inf->getSymmetry().getString() << endl;
cerr << " | + instance: name: " << ((*sit).first).getString() << " - x: " << inf->getX() << " - y: " << inf->getY() << " - symmetry: " << inf->getSymmetry().getString() << endl;
}
if (schematicNet) {
for (size_t i = 0 ; i < netlist->getNets().size() ; i++) {
OpenChams::Net* net = netlist->getNets()[i];
cerr << " | + net name: " << net->getName().getString() << endl;
if (!net->hasNoPorts()) {
for (size_t j = 0 ; j < net->getPorts().size() ; j++) {
OpenChams::Port* port = net->getPorts()[j];
cerr << " | | + port type: " << port->getType().getString() << " - idx: " << port->getIndex() << " - x: " << port->getX() << " - y: " << port->getY() << " - sym: " << port->getSymmetry().getString() << endl;
}
}
if (!net->hasNoWires()) {
for (size_t j = 0 ; j < net->getWires().size() ; j++) {
OpenChams::Wire* wire = net->getWires()[j];
cerr << " | | + wire ";
OpenChams::WirePoint* start = wire->getStartPoint();
if (dynamic_cast<OpenChams::InstancePoint*>(start)) {
OpenChams::InstancePoint* iP = static_cast<OpenChams::InstancePoint*>(start);
cerr << "<" << iP->getName().getString() << "," << iP->getPlug().getString() << "> ";
} else if (dynamic_cast<OpenChams::PortPoint*>(start)) {
OpenChams::PortPoint* pP = static_cast<OpenChams::PortPoint*>(start);
cerr << "<" << pP->getIndex() << "> ";
}
for (size_t k = 0 ; k < wire->getIntermediatePoints().size() ; k++) {
OpenChams::IntermediatePoint* iP = wire->getIntermediatePoints()[k];
cerr << "<" << iP->getX() << "," << iP->getY() << "> ";
}
OpenChams::WirePoint* end = wire->getEndPoint();
if (dynamic_cast<OpenChams::InstancePoint*>(end)) {
OpenChams::InstancePoint* iP = static_cast<OpenChams::InstancePoint*>(end);
cerr << "<" << iP->getName().getString() << "," << iP->getPlug().getString() << "> ";
} else if (dynamic_cast<OpenChams::PortPoint*>(end)) {
OpenChams::PortPoint* pP = static_cast<OpenChams::PortPoint*>(end);
cerr << "<" << pP->getIndex() << "> ";
}
cerr << endl;
}
}
}
}
}
OpenChams::Sizing* sizing = circuit->getSizing();
if (sizing) {

41
vlsisapd/examples/openChams/inverter.xml
View File

@ -53,9 +53,46 @@
</net>
</nets>
</netlist>
<schematic zoom="1.0">
<schematic>
<instance name="nmos1" x="2490" y="2600" sym="ID"/>
<instance name="pmos1" x="2490" y="2300" sym="ID"/>
<instance name="pmos1" x="2490" y="2490" sym="ID"/>
<net name="vdd">
<port type="inV" idx="0" x="2525" y="2430" sym="ID"/>
<wire>
<connector name="pmos1" plug="S"/>
<!--point x="" y=""/-->
<connector idx="0"/>
</wire>
</net>
<net name="vss">
<port type="inV" idx="0" x="2525" y="2740" sym="MY"/>
<wire>
<connector name="nmos1" plug="S"/>
<connector idx="0"/>
</wire>
</net>
<net name="in">
<port type="inH" idx="0" x="2415" y="2520" sym="ID"/>
<wire>
<connector name="pmos1" plug="G"/>
<connector name="nmos1" plug="G"/>
</wire>
<wire>
<connector idx="0"/>
<connector name="pmos1" plug="G"/>
</wire>
</net>
<net name="out">
<port type="outH" idx="0" x="2570" y="2590" sym="ID"/>
<wire>
<connector name="pmos1" plug="D"/>
<connector name="nmos1" plug="D"/>
</wire>
<wire>
<connector name="nmos1" plug="D"/>
<connector idx="0"/>
</wire>
</net>
</schematic>
<sizing>
<instance name="pmos1" operator="OPVG(Veg)" simulModel="BSIM3V3" callOrder="0">

24
vlsisapd/examples/openChams/python/driveOpenChams.py
View File

@ -46,9 +46,31 @@ _in.connectTo ("pmos1", "G")
_out.connectTo("nmos1", "D")
_out.connectTo("pmos1", "D")
# schematic
schematic = circuit.createSchematic(1.0)
schematic = circuit.createSchematic()
schematic.addInstance("nmos1", 2490, 2600, "ID")
schematic.addInstance("pmos1", 2490, 2300, "ID")
_vdd.addPort("inV" , 0, 2490, 2100, "ID")
_vss.addPort("inV" , 0, 2490, 2800, "MY")
_in.addPort ("inH" , 0, 2190, 2500, "ID")
_out.addPort("outH", 0, 2600, 2500, "ID")
wireVdd = _vdd.addWire()
wireVdd.setStartPoint("pmos1", "S")
wireVdd.setEndPoint(0)
wireVss = _vss.addWire()
wireVss.setStartPoint("nmos1", "S")
wireVss.setEndPoint(0)
wireIn0 = _in.addWire()
wireIn1 = _in.addWire()
wireIn0.setStartPoint("pmos1", "G")
wireIn0.setEndPoint ("nmos1", "G")
wireIn1.setStartPoint(0)
wireIn1.setEndPoint ("pmos1", "G")
wireOut0 = _out.addWire()
wireOut1 = _out.addWire()
wireOut0.setStartPoint("pmos1", "D")
wireOut0.setEndPoint ("nmos1", "D")
wireOut1.setStartPoint("nmos1", "D")
wireOut1.setEndPoint (0)
# sizing
sizing = circuit.createSizing()
op_pmos1 = sizing.addOperator("pmos1", "OPVG(Veg)" , "BSIM3V3", 0)

29
vlsisapd/examples/openChams/python/parseOpenChams.py
View File

@ -28,16 +28,41 @@ def printContents(circuit):
print " | | | | name:", tr.name, "- gate:", tr.gate, "- source:", tr.source, "- drain:", tr.drain, "- bulk:", tr.bulk
# nets
print " | + nets"
schematicNet = False
for net in circuit.netlist.getNets():
print " | | +", net.name, ":", net.type, net.external
print " | | | + connections"
for conn in net.getConnections():
print " | | | | %s.%s"%(conn.instanceName, conn.connectorName)
if not net.hasNoPorts() or not net.hasNoWires():
schematicNet = True
# schematic
if (circuit.schematic):
print " + schematic - zoom:", circuit.schematic.zoom
print " + schematic"
for instance in circuit.schematic.getInstances():
print " | name:", instance.key, "- x:", instance.value.x, "- y:", instance.value.y, "- symmetry:", instance.value.symmetry
print " | + instance name:", instance.key, "- x:", instance.value.x, "- y:", instance.value.y, "- symmetry:", instance.value.symmetry
if schematicNet:
for net in circuit.netlist.getNets():
if net.hasNoPorts() and net.hasNoWires():
continue
print " | + net name:", net.name
for port in net.getPorts():
print " | | + port type:", port.type, "- idx:", port.index, "- x:", port.x, "- y:", port.y, "- sym:", port.symmetry
for wire in net.getWires():
if isinstance(wire.startPoint, InstancePoint):
print " | | + wire <" + wire.startPoint.name.getString() + "," + wire.startPoint.plug.getString() +">"
elif isinstance(wire.startPoint, PortPoint):
print " | | + wire <" + str(wire.startPoint.index) + ">"
else:
print " - - UNKNOWN START POINT"
for point in wire.getIntermediatePoints():
print " | | <" + str(point.x) + "," + str(point.y) + ">"
if isinstance(wire.endPoint, InstancePoint):
print " | | <" + wire.endPoint.name.getString() + "," + wire.endPoint.plug.getString() +">"
elif isinstance(wire.endPoint, PortPoint):
print " | | <" + str(wire.endPoint.index) + ">"
else:
print " - - UNKNOWN END POINT"
# sizing
if (circuit.sizing):
print " + sizing"

2
vlsisapd/src/agds/src/CMakeLists.txt
View File

@ -24,7 +24,7 @@ IF(Boost_FOUND)
OUTPUT_NAME "AGDS"
PREFIX ""
)
TARGET_LINK_LIBRARIES(pyAGDS agds ${PYTHON_LIBRARIES})
TARGET_LINK_LIBRARIES(pyAGDS agds ${Boost_LIBRARIES} ${PYTHON_LIBRARIES})
INSTALL(TARGETS pyAGDS DESTINATION ${PYTHON_SITE_PACKAGES})
ENDIF(Boost_FOUND)

4
vlsisapd/src/configuration/src/CMakeLists.txt
View File

@ -14,11 +14,11 @@
vlsisapd/configuration/ConfigurationWidget.h
vlsisapd/configuration/ConfEditorWidget.h
)
set ( includes vlsisapd/configuration/Parameter.h
set ( includes vlsisapd/configuration/Parameter.h
vlsisapd/configuration/LayoutDescription.h
vlsisapd/configuration/Configuration.h
)
set ( cpps Parameter.cpp
set ( cpps Parameter.cpp
LayoutDescription.cpp
Configuration.cpp
FilePathEdit.cpp

3
vlsisapd/src/openChams/src/CMakeLists.txt
View File

@ -13,6 +13,8 @@ SET ( hpps vlsisapd/openChams/Circuit.h
vlsisapd/openChams/Sizing.h
vlsisapd/openChams/Layout.h
vlsisapd/openChams/Transistor.h
vlsisapd/openChams/Port.h
vlsisapd/openChams/Wire.h
vlsisapd/openChams/OpenChamsException.h
)
SET ( cpps Circuit.cpp
@ -28,6 +30,7 @@ SET ( cpps Circuit.cpp
Sizing.cpp
Layout.cpp
Transistor.cpp
Wire.cpp
)
SET ( pycpps PyOpenChams.cpp
)

223
vlsisapd/src/openChams/src/Circuit.cpp
View File

@ -25,6 +25,8 @@ using namespace std;
#include "vlsisapd/openChams/Layout.h"
#include "vlsisapd/openChams/Transistor.h"
#include "vlsisapd/openChams/Operator.h"
#include "vlsisapd/openChams/Port.h"
#include "vlsisapd/openChams/Wire.h"
#include "vlsisapd/openChams/OpenChamsException.h"
namespace {
@ -39,7 +41,7 @@ namespace {
namespace OpenChams {
static bool readSubCircuitsPathesDone = false;
static bool readSubCircuitsPathsDone = false;
static bool readCircuitParametersDone = false;
static bool readSimulModelsDone = false;
static bool readNetListDone = false;
@ -49,8 +51,15 @@ static bool readSchematicDone = false;
static bool readSizingDone = false;
static bool readLayoutDone = false;
Circuit::Circuit(Name name, Name techno) : _name(name), _techno(techno), _netlist(NULL), _schematic(NULL), _sizing(NULL), _layout(NULL) {
readSubCircuitsPathesDone = false;
Circuit::Circuit(Name name, Name techno) : _name(name)
, _absolutePath("")
, _techno(techno)
, _netlist(NULL)
, _schematic(NULL)
, _sizing(NULL)
, _layout(NULL)
{
readSubCircuitsPathsDone = false;
readCircuitParametersDone = false;
readSimulModelsDone = false;
readNetListDone = false;
@ -145,9 +154,9 @@ Name Circuit::readConnector(xmlNode* node) {
}
// CIRCUIT //
void Circuit::readSubCircuitsPathes(xmlNode* node) {
if (readSubCircuitsPathesDone) {
cerr << "[WARNING] Only one 'subCircuitsPathes' node is allowed in circuit, others will be ignored." << endl;
void Circuit::readSubCircuitsPaths(xmlNode* node) {
if (readSubCircuitsPathsDone) {
cerr << "[WARNING] Only one 'subCircuitsPaths' node is allowed in circuit, others will be ignored." << endl;
return;
}
if (node->type == XML_ELEMENT_NODE && node->children) {
@ -157,18 +166,21 @@ void Circuit::readSubCircuitsPathes(xmlNode* node) {
xmlChar* pathC = xmlGetProp(pathNode, (xmlChar*)"path");
if (pathC) {
string path((const char*)pathC);
_subCircuitsPathes.push_back(path);
if (path[0] != '/') { // this is not an absolute path
path = _absolutePath+"/"+path;
}
_subCircuitsPaths.push_back(path);
} else {
throw OpenChamsException("[ERROR] 'path' node must have 'path' property.");
}
} else {
cerr << "[WARNING] Only 'path' nodes are allowed under 'subCircuitsPathes' node." << endl;
cerr << "[WARNING] Only 'path' nodes are allowed under 'subCircuitsPaths' node." << endl;
return;
}
}
}
}
readSubCircuitsPathesDone = true;
readSubCircuitsPathsDone = true;
}
void Circuit::readCircuitParameters(xmlNode* node) {
@ -530,22 +542,17 @@ void Circuit::readSchematic(xmlNode* node) {
cerr << "[WARNING] Only one 'schematic' node is allowed in circuit, others will be ignored." << endl;
return;
}
xmlChar* zoomC = xmlGetProp(node, (xmlChar*)"zoom");
double zoom = 1.0;
if (zoomC) {
zoom = ::getValue<double>(zoomC);
} else {
throw OpenChamsException("[ERROR] 'schematic' node must have 'zoom' property.");
}
Schematic* schematic = new Schematic(this, zoom);
Schematic* schematic = new Schematic(this);
xmlNode* child = node->children;
for (xmlNode* node = child; node; node = node->next) {
if (node->type == XML_ELEMENT_NODE) {
if (xmlStrEqual(node->name, (xmlChar*)"instance")) {
readInstanceSchematic(node, schematic);
} else if (xmlStrEqual(node->name, (xmlChar*)"net")) {
readNetSchematic(node, this);
} else {
cerr << "[WARNING] Only 'instance' nodes are allowed in 'schematic', others will be ignored." << endl;
cerr << "[WARNING] Only 'instance' and 'nets' nodes are allowed in 'schematic', others will be ignored." << endl;
}
}
}
@ -565,13 +572,111 @@ void Circuit::readInstanceSchematic(xmlNode* node, Schematic* schematic) {
string symStr((const char*)symC);
string symComp[8] = {"ID", "R1", "R2", "R3", "MX", "XR", "MY", "YR"};
vector<string> symComps (symComp, symComp+8);
check_uppercase(symStr, symComps, "[ERROR] In 'schematic/instance', 'sym' must be 'ID', 'R1', 'R2', 'R3', 'MX', 'XR', 'MY' or 'YR'.");
check_uppercase(symStr, symComps, "[ERROR] In 'schematic'.'instance', 'sym' must be 'ID', 'R1', 'R2', 'R3', 'MX', 'XR', 'MY' or 'YR'.");
schematic->addInstance(iName, x, y, Name(symStr));
} else {
throw OpenChamsException("[ERROR] 'instance' node in 'schematic' must have 'name', 'x', 'y' and 'sym' properties.");
}
}
void Circuit::readNetSchematic(xmlNode* node, Circuit* circuit) {
xmlChar* nameC = xmlGetProp(node, (xmlChar*)"name");
if (nameC) {
Name nName((const char*)nameC);
Net* net = circuit->getNetlist()->getNet(nName);
if (!net) {
string error ("[ERROR] In 'schematic' section cannot specify wires for net ");
error += nName.getString();
error += " since it has not been defined in netlist section.";
throw OpenChamsException(error);
}
xmlNode* child = node->children;
for (xmlNode* node = child; node; node = node->next) {
if (node->type == XML_ELEMENT_NODE) {
if (xmlStrEqual(node->name, (xmlChar*)"port")) {
readPortSchematic(node, net);
} else if (xmlStrEqual(node->name, (xmlChar*)"wire")) {
readWireSchematic(node, net);
} else {
cerr << "[WARNING] Only 'port' and 'wire' nodes are allowed in 'schematic'.'net', others will be ignored." << endl;
}
}
}
} else {
throw OpenChamsException("[ERROR] 'net' node in schematic must have 'name' property.");
}
}
void Circuit::readPortSchematic(xmlNode* node, Net* net) {
xmlChar* typeC = xmlGetProp(node, (xmlChar*)"type");
xmlChar* idxC = xmlGetProp(node, (xmlChar*)"idx");
xmlChar* xC = xmlGetProp(node, (xmlChar*)"x");
xmlChar* yC = xmlGetProp(node, (xmlChar*)"y");
xmlChar* symC = xmlGetProp(node, (xmlChar*)"sym");
if (typeC && idxC && xC && yC && symC) {
Name pType((const char*)typeC);
unsigned idx = ::getValue<unsigned>(idxC);
double x = ::getValue<double>(xC);
double y = ::getValue<double>(yC);
string symStr((const char*)symC);
string symComp[8] = {"ID", "R1", "R2", "R3", "MX", "XR", "MY", "YR"};
vector<string> symComps (symComp, symComp+8);
check_uppercase(symStr, symComps, "[ERROR] In 'schematic'.'port', 'sym' must be 'ID', 'R1', 'R2', 'R3', 'MX', 'XR', 'MY' or 'YR'.");
net->addPort(pType, idx, x, y, Name(symStr));
} else {
throw OpenChamsException("[ERROR] 'schematic'.'port' must have 'type', 'idx', 'x', 'y' and 'sym properties.");
}
}
void Circuit::readWireSchematic(xmlNode* node, Net* net) {
Wire* wire = net->addWire();
xmlNode* child = node->children;
for (xmlNode* node = child; node; node = node->next) {
if (node->type == XML_ELEMENT_NODE) {
if (xmlStrEqual(node->name, (xmlChar*)"connector")) {
xmlChar* nameC = xmlGetProp(node, (xmlChar*)"name");
xmlChar* plugC = xmlGetProp(node, (xmlChar*)"plug");
xmlChar* idxC = xmlGetProp(node, (xmlChar*)"idx");
if (nameC && plugC) {
Name name((const char*)nameC);
Name plug((const char*)plugC);
if (!wire->getStartPoint()) {
wire->setStartPoint(name, plug);
} else if (!wire->getEndPoint()) {
wire->setEndPoint(name, plug);
} else {
throw OpenChamsException("[ERROR] In 'schematic' a 'wire' must have exactly 2 connectors (not more).");
}
} else if (idxC) {
unsigned idx = ::getValue<unsigned>(idxC);
if (!wire->getStartPoint()) {
wire->setStartPoint(idx);
} else if (!wire->getEndPoint()) {
wire->setEndPoint(idx);
} else {
throw OpenChamsException("[ERROR] In 'schematic' a 'wire' must have exactly 2 connectors (not more).");
}
} else {
throw OpenChamsException("[ERROR] 'schematic'.'net'.'connector' node must have 'name' & 'plug' OR 'idx' properties. ");
}
} else if (xmlStrEqual(node->name, (xmlChar*)"point")) {
xmlChar* xC = xmlGetProp(node, (xmlChar*)"x");
xmlChar* yC = xmlGetProp(node, (xmlChar*)"y");
if (xC && yC) {
double x = ::getValue<double>(xC);
double y = ::getValue<double>(yC);
wire->addIntermediatePoint(x, y); // check is done inside the method (start/end points)
} else {
throw OpenChamsException("[ERROR] 'schematic'.'net'.'point' node must have 'x' and 'y' properties.");
}
} else {
cerr << "[WARNING] Only 'connector' and 'points' nodes are allowed in 'schematic'.'net'.'wire', others will be ignored." << endl;
}
}
}
}
// SIZING //
void Circuit::readSizing(xmlNode* node) {
if (readSizingDone) {
@ -714,10 +819,21 @@ void Circuit::readInstanceLayout(xmlNode* node, Layout* layout) {
throw OpenChamsException("[ERROR] 'instance' node in 'layout' must have 'name' and 'style' properties.");
}
}
void Circuit::setAbsolutePath(const string filePath) {
if (filePath[0] == '/')
_absolutePath = filePath;
else {
_absolutePath = string(getenv("PWD"))+"/"+filePath;
}
size_t found = _absolutePath.find_last_of("/");
_absolutePath = _absolutePath.substr(0, found);
}
Circuit* Circuit::readFromFile(const string filePath) {
LIBXML_TEST_VERSION;
Circuit* cir = NULL;
xmlDoc* doc = xmlReadFile(filePath.c_str(), NULL, 0);
if (doc == NULL) {
string error ("[ERROR] Failed to parse: ");
@ -738,13 +854,13 @@ Circuit* Circuit::readFromFile(const string filePath) {
throw OpenChamsException("[ERROR] 'circuit' node must have 'name' and 'techno' properties.");
return NULL;
}
cir->setAbsolutePath(filePath);
xmlNode* child = rootElement->children;
for (xmlNode* node = child; node; node = node->next) {
if (node->type == XML_ELEMENT_NODE) {
if (xmlStrEqual(node->name, (xmlChar*)"subCircuitsPathes")) {
cir->readSubCircuitsPathes(node);
if (xmlStrEqual(node->name, (xmlChar*)"subCircuitsPaths")) {
cir->readSubCircuitsPaths(node);
}
else if (xmlStrEqual(node->name, (xmlChar*)"parameters")) {
cir->readCircuitParameters(node);
@ -791,11 +907,11 @@ Netlist* Circuit::createNetlist() {
return _netlist;
}
Schematic* Circuit::createSchematic(double zoom) {
Schematic* Circuit::createSchematic() {
if (_schematic)
throw OpenChamsException("[ERROR] Cannot create two scheamtics in one circuit.");
_schematic = new Schematic(this, zoom);
_schematic = new Schematic(this);
if (!_schematic)
throw OpenChamsException("[ERROR] Cannot create schematic.");
@ -852,6 +968,13 @@ bool Circuit::writeToFile(string filePath) {
file << "<?xml version=\"1.0\" encoding=\"UTF-8\" ?>" << endl
<< "<circuit name=\"" << _name.getString() << "\" techno=\"" << _techno.getString() << "\">" << endl;
if (_subCircuitsPaths.size() != 0) {
file << " <subCircuitsPaths>" << endl;
for (size_t i = 0 ; i < _subCircuitsPaths.size() ; i++ ) {
file << " <path path=\"" << _subCircuitsPaths[i] << "\"/>" << endl;
}
file << " </subCircuitsPaths>" << endl;
}
if (!_params.isEmpty()) {
file << " <parameters>" << endl;
for (map<Name, double>::const_iterator it = _params.getValues().begin() ; it != _params.getValues().end() ; ++it) {
@ -915,6 +1038,7 @@ bool Circuit::writeToFile(string filePath) {
}
file << " </instances>" << endl
<< " <nets>" << endl;
bool schematicNets = false; // to know if net sections in schematic are needed
vector<Net*> nets = _netlist->getNets();
sort(nets.begin(), nets.end(), NetNameSort); // sort based on nets' names
for (vector<Net*>::iterator it = nets.begin() ; it != nets.end() ; ++it) {
@ -926,6 +1050,8 @@ bool Circuit::writeToFile(string filePath) {
throw OpenChamsException(error);
//return false;
}
if (!net->hasNoPorts() || !net->hasNoWires())
schematicNets = true;
string externStr = (net->isExternal()) ? "True" : "False";
file << " <net name=\"" << net->getName().getString() << "\" type=\"" << net->getType().getString() << "\" isExternal=\"" << externStr << "\">" << endl;
vector<Net::Connection*> connections = net->getConnections();
@ -938,11 +1064,58 @@ bool Circuit::writeToFile(string filePath) {
file << " </nets>" << endl;
file << " </netlist>" << endl;
if (_schematic && !_schematic->hasNoInstances()) {
file << " <schematic zoom=\"" << _schematic->getZoom() << "\">" << endl;
file << " <schematic>" << endl;
for (map<Name, Schematic::Infos*>::const_iterator it = _schematic->getInstances().begin() ; it != _schematic->getInstances().end(); ++it ) {
Schematic::Infos* infos = (*it).second;
file << " <instance name=\"" << ((*it).first).getString() << "\" x=\"" << infos->getX() << "\" y=\"" << infos->getY() << "\" sym=\"" << infos->getSymmetry().getString() << "\"/>" << endl;
}
if (schematicNets) {
for (size_t i = 0 ; i < nets.size() ; i++) {
Net* net = nets[i];
if (net->hasNoPorts() && net->hasNoWires())
continue;
file << " <net name=\"" << net->getName().getString() << "\">" << endl;
for (size_t j = 0 ; j < net->getPorts().size() ; j++) {
Port* port = net->getPorts()[j];
if (!port)
continue;
file << " <port type=\"" << port->getType().getString() << "\" idx=\"" << port->getIndex() << "\" x=\"" << port->getX() << "\" y=\"" << port->getY() << "\" sym=\"" << port->getSymmetry().getString() << "\"/>" << endl;
}
for (size_t j = 0 ; j < net->getWires().size() ; j++) {
Wire* wire = net->getWires()[j];
file << " <wire>" << endl;
WirePoint* start = wire->getStartPoint();
WirePoint* end = wire->getEndPoint();
// start point
if (dynamic_cast<InstancePoint*>(start)) {
InstancePoint* iP = static_cast<InstancePoint*>(start);
file << " <connector name=\"" << iP->getName().getString() << "\" plug=\"" << iP->getPlug().getString() << "\"/>" << endl;
} else if (dynamic_cast<PortPoint*>(start)) {
PortPoint* pP = static_cast<PortPoint*>(start);
file << " <connector idx=\"" << pP->getIndex() << "\"/>" << endl;
} else {
throw OpenChamsException("[ERROR] Wire start point is nor an InstancePoint nor a PortPoint.");
}
// intermediate points
for (size_t k = 0 ; k < wire->getIntermediatePoints().size() ; k++) {
IntermediatePoint* iP = wire->getIntermediatePoints()[k];
file << " <point x=\"" << iP->getX() << "\" y=\"" << iP->getY() << "\"/>" << endl;
}
// end point
if (dynamic_cast<InstancePoint*>(end)) {
InstancePoint* iP = static_cast<InstancePoint*>(end);
file << " <connector name=\"" << iP->getName().getString() << "\" plug=\"" << iP->getPlug().getString() << "\"/>" << endl;
} else if (dynamic_cast<PortPoint*>(end)) {
PortPoint* pP = static_cast<PortPoint*>(end);
file << " <connector idx=\"" << pP->getIndex() << "\"/>" << endl;
} else {
throw OpenChamsException("[ERROR] Wire end point is nor an InstancePoint nor a PortPoint.");
}
file << " </wire>" << endl;
}
file << " </net>" << endl;
}
}
file << " </schematic>" << endl;
}
if (_sizing && !_sizing->hasNoOperators()) {

24
vlsisapd/src/openChams/src/Net.cpp
View File

@ -12,6 +12,8 @@ using namespace std;
#include "vlsisapd/openChams/Net.h"
#include "vlsisapd/openChams/Instance.h"
#include "vlsisapd/openChams/Netlist.h"
#include "vlsisapd/openChams/Port.h"
#include "vlsisapd/openChams/Wire.h"
#include "vlsisapd/openChams/OpenChamsException.h"
namespace OpenChams {
@ -19,7 +21,11 @@ Net::Net(Name netName, Name typeName, bool isExternal, Netlist* netlist)
: _name(netName)
, _typeName(typeName)
, _isExternal(isExternal)
, _netlist(netlist) {}
, _netlist(netlist)
, _connections()
, _ports()
, _wires()
{}
void Net::connectTo(Name instanceName, Name connectorName) {
_connections.push_back(new Net::Connection(instanceName, connectorName));
@ -36,5 +42,21 @@ void Net::connectTo(Name instanceName, Name connectorName) {
}
}
Port* Net::addPort(Name type, unsigned idx, double x, double y, Name sym) {
while (_ports.size() <= idx)
_ports.push_back(NULL);
if (_ports[idx])
throw OpenChamsException("[ERROR] Net::addPort: cannot add port since another one with the same id already exists.");
_ports[idx] = new Port(type, idx, x, y, sym);
return _ports[idx];
}
Wire* Net::addWire() {
Wire* w = new Wire();
_wires.push_back(w);
return w;
}
Net::Connection::Connection(Name instanceName, Name connectorName) : _instanceName(instanceName), _connectorName(connectorName) {}
} // namespace

4
vlsisapd/src/openChams/src/Netlist.cpp
View File

@ -32,7 +32,7 @@ Instance* Netlist::addInstance(Name name, Name model) {
}
Instance* inst = new Instance(name, model, this);
if (!inst)
throw OpenChamsException("[ERROR] Cannot creeate instance.");
throw OpenChamsException("[ERROR] Cannot create instance.");
_instances.push_back(inst);
return inst;
@ -49,7 +49,7 @@ Device* Netlist::addDevice(Name name, Name model, Name mosType, bool sourceBulkC
}
Device* dev = new Device(name, model, mosType, sourceBulkConnected, this);
if (!dev)
throw OpenChamsException("[ERROR] Cannot creeate device.");
throw OpenChamsException("[ERROR] Cannot create device.");
_instances.push_back(dev);
return dev;

83
vlsisapd/src/openChams/src/PyOpenChams.cpp
View File

@ -17,6 +17,8 @@ using namespace boost::python;
#include "vlsisapd/openChams/Sizing.h"
#include "vlsisapd/openChams/Layout.h"
#include "vlsisapd/openChams/Circuit.h"
#include "vlsisapd/openChams/Port.h"
#include "vlsisapd/openChams/Wire.h"
#include "vlsisapd/openChams/OpenChamsException.h"
#include "vlsisapd/openChams/PySTLMapWrapper.h"
@ -133,11 +135,68 @@ BOOST_PYTHON_MODULE(OPENCHAMS) {
.def("getTransistors", &Device::getTransistors, return_internal_reference<>())
;
// class OpenChams::Port
class_<Port, Port*>("Port", init<Name, unsigned, double, double, Name>())
// properties
.add_property("type" , &Port::getType )
.add_property("index" , &Port::getIndex )
.add_property("x" , &Port::getX )
.add_property("y" , &Port::getY )
.add_property("symmetry", &Port::getSymmetry)
;
// class OpenChams::WirePoint
class_<WirePoint, WirePoint*>("WirePoint", init<>())
;
// class OpenChams::InstancePoint
class_<InstancePoint, bases<WirePoint> >("InstancePoint", init<Name, Name>())
// properties
.add_property("name", &InstancePoint::getName)
.add_property("plug", &InstancePoint::getPlug)
;
// class OpenChams::PortPoint
class_<PortPoint, bases<WirePoint> >("PortPoint", init<unsigned>())
// properties
.add_property("index", &PortPoint::getIndex)
;
// class OpenChams::IntermediatePoint
class_<IntermediatePoint, bases<WirePoint> >("IntermediatePoint", init<double, double>())
// properties
.add_property("x", &IntermediatePoint::getX)
.add_property("y", &IntermediatePoint::getY)
;
// vector_indexing for OpenChams::Wire
class_<std::vector<IntermediatePoint*> >("IntermediatePointsVector")
.def(vector_indexing_suite<std::vector<IntermediatePoint*>, true>())
;
// class OpenChams::Wire
class_<Wire, Wire*>("Wire", init<>())
// properties
.add_property("startPoint", make_function(&Wire::getStartPoint, return_value_policy<reference_existing_object>()))
.add_property("endPoint" , make_function(&Wire::getEndPoint , return_value_policy<reference_existing_object>()))
// accessors
.def("hasNoIntermediatePoints", &Wire::hasNoIntermediatePoints)
// modifiers
.def("setStartPoint" , static_cast<void(Wire::*)(Name, Name)>(&Wire::setStartPoint))
.def("setStartPoint" , static_cast<void(Wire::*)(unsigned )>(&Wire::setStartPoint))
.def("setEndPoint" , static_cast<void(Wire::*)(Name, Name)>(&Wire::setEndPoint))
.def("setEndPoint" , static_cast<void(Wire::*)(unsigned )>(&Wire::setEndPoint))
.def("addIntermediatePoint", &Wire::addIntermediatePoint)
// stl containers
.def("getIntermediatePoints" , &Wire::getIntermediatePoints, return_internal_reference<>())
;
// vector_indexing for OpenChams::Net
class_<std::vector<Net::Connection*> >("ConnectionsVector")
.def(vector_indexing_suite<std::vector<Net::Connection*>, true>())
;
class_<std::vector<Port*> >("PortsVector")
.def(vector_indexing_suite<std::vector<Port*>, true>())
;
class_<std::vector<Wire*> >("WiresVector")
.def(vector_indexing_suite<std::vector<Wire*>, true>())
;
{ //this scope is used to define Connection as a subclass of Net
// class OpenChams::Net
scope netScope = class_<Net, Net*>("Net", init<Name, Name, bool, Netlist*>())
@ -148,10 +207,16 @@ BOOST_PYTHON_MODULE(OPENCHAMS) {
.add_property("netlist" , make_function(&Net::getNetlist, return_value_policy<reference_existing_object>()))
// accessors
.def("hasNoConnections", &Net::hasNoConnections)
.def("hasNoPorts" , &Net::hasNoPorts )
.def("hasNoWires" , &Net::hasNoWires )
// modifiers
.def("connectTo" , &Net::connectTo )
.def("addPort" , &Net::addPort, return_value_policy<reference_existing_object>())
.def("addWire" , &Net::addWire, return_value_policy<reference_existing_object>())
// stl containers
.def("getConnections", &Net::getConnections, return_internal_reference<>())
.def("getPorts" , &Net::getPorts , return_internal_reference<>())
.def("getWires" , &Net::getWires , return_internal_reference<>())
;
// class OpenChams::Net::Connection
@ -188,9 +253,7 @@ BOOST_PYTHON_MODULE(OPENCHAMS) {
STL_MAP_WRAPPING_PTR(Name, Schematic::Infos*, "SchematicInstancesMap")
{ // this scope is used to define Infos as a subclass of Schematic
// class OpenChams::Schematic
scope schematicScope = class_<Schematic, Schematic*>("Schematic", init<Circuit*, double>())
// properties
.add_property("zoom" , &Schematic::getZoom)
scope schematicScope = class_<Schematic, Schematic*>("Schematic", init<Circuit*>())
// accessors
.def("hasNoInstances", &Schematic::hasNoInstances)
// modifiers
@ -264,13 +327,13 @@ BOOST_PYTHON_MODULE(OPENCHAMS) {
class_<Circuit, Circuit*>("Circuit", init<Name, Name>())
// properties
.add_property("name" , &Circuit::getName )
.add_property("techno" , &Circuit::getTechno )
.add_property("parameters", &Circuit::getParameters)
.add_property("netlist" , make_function(&Circuit::getNetlist , return_value_policy<reference_existing_object>()))
.add_property("schematic" , make_function(&Circuit::getSchematic, return_value_policy<reference_existing_object>()))
.add_property("sizing" , make_function(&Circuit::getSizing , return_value_policy<reference_existing_object>()))
.add_property("layout" , make_function(&Circuit::getLayout , return_value_policy<reference_existing_object>()))
.add_property("name" , &Circuit::getName )
.add_property("techno" , &Circuit::getTechno )
.add_property("parameters" , &Circuit::getParameters )
.add_property("netlist" , make_function(&Circuit::getNetlist , return_value_policy<reference_existing_object>()))
.add_property("schematic" , make_function(&Circuit::getSchematic, return_value_policy<reference_existing_object>()))
.add_property("sizing" , make_function(&Circuit::getSizing , return_value_policy<reference_existing_object>()))
.add_property("layout" , make_function(&Circuit::getLayout , return_value_policy<reference_existing_object>()))
// accessors
.def("getValue", &Circuit::getValue)
// modifiers

4
vlsisapd/src/openChams/src/Schematic.cpp
View File

@ -13,9 +13,7 @@ using namespace std;
#include "vlsisapd/openChams/OpenChamsException.h"
namespace OpenChams {
Schematic::Schematic(Circuit* circuit, double zoom)
: _circuit(circuit)
, _zoom(zoom) {}
Schematic::Schematic(Circuit* circuit): _circuit(circuit) {}
void Schematic::addInstance(Name instanceName, double x, double y, Name sym) {
map<Name, Schematic::Infos*>::iterator it = _instances.find(instanceName);

57
vlsisapd/src/openChams/src/Wire.cpp Normal file
View File

@ -0,0 +1,57 @@
/*
* Wire.cpp
* openChams
*
* Created by damien dupuis on 08/02/11.
* Copyright 2011 UPMC / LIP6. All rights reserved.
*
*/
using namespace std;
#include "vlsisapd/openChams/Wire.h"
#include "vlsisapd/openChams/OpenChamsException.h"
namespace OpenChams {
void Wire::setStartPoint(Name name, Name plug) {
if (_start)
throw OpenChamsException("[ERROR] Wire::setStartPoint: cannot set start point since it has already been set.");
_start = new InstancePoint(name, plug);
}
void Wire::setStartPoint(unsigned idx) {
if (_start)
throw OpenChamsException("[ERROR] Wire::setStartPoint: cannot set start point since it has already been set.");
_start = new PortPoint(idx);
}
void Wire::setEndPoint(Name name, Name plug) {
if (!_start)
throw OpenChamsException("[ERROR] Wire::setEndPoint: cannot set end point since start point has not been set.");
if (_end)
throw OpenChamsException("[ERROR] Wire::setEndPoint: cannot set end point since it has already been set.");
_end = new InstancePoint(name, plug);
}
void Wire::setEndPoint(unsigned idx) {
if (!_start)
throw OpenChamsException("[ERROR] Wire::setEndPoint: cannot set end point since start point has not been set.");
if (_end)
throw OpenChamsException("[ERROR] Wire::setEndPoint: cannot set end point since it has already been set.");
_end = new PortPoint(idx);
}
void Wire::addIntermediatePoint(double x, double y) {
if (!_start)
throw OpenChamsException("[ERROR] Wire::addIntermediatePoint: cannot add point since start point has not been set.");
if (_end)
throw OpenChamsException("[ERROR] Wire::addIntermediatePoint: cannot add point since end point has already been set.");
_inters.push_back(new IntermediatePoint(x, y));
}
} // namespace

49
vlsisapd/src/openChams/src/vlsisapd/openChams/Circuit.h
View File

@ -45,6 +45,8 @@ class Circuit {
inline void addParameter(Name, double);
inline void addParameter(Name, std::string);
inline Parameters getParameters();
inline void addSubCircuitPath(std::string);
inline std::vector<std::string>& getSubCircuitPaths();
void addSimulModel(unsigned, SimulModel::Base, SimulModel::Version, std::string);
@ -52,7 +54,7 @@ class Circuit {
inline void setLayout(Layout*);
Netlist* createNetlist();
Schematic* createSchematic(double);
Schematic* createSchematic();
Sizing* createSizing();
Layout* createLayout();
@ -63,7 +65,7 @@ class Circuit {
Name readParameter(xmlNode*, double&);
Name readParameterEq(xmlNode*, std::string&);
Name readConnector(xmlNode*);
void readSubCircuitsPathes(xmlNode*);
void readSubCircuitsPaths(xmlNode*);
void readCircuitParameters(xmlNode*);
void readSimulModels(xmlNode*);
void readNetList(xmlNode*);
@ -79,6 +81,9 @@ class Circuit {
void readNetConnector(xmlNode*, Net*);
void readSchematic(xmlNode*);
void readInstanceSchematic(xmlNode*, Schematic*);
void readNetSchematic(xmlNode*, Circuit*);
void readPortSchematic(xmlNode*, Net*);
void readWireSchematic(xmlNode*, Net*);
void readSizing(xmlNode*);
void readInstanceSizing(xmlNode*, Sizing*);
void readConstraint(xmlNode*, Operator*);
@ -86,31 +91,35 @@ class Circuit {
void readEquation(xmlNode*, Sizing*);
void readLayout(xmlNode*);
void readInstanceLayout(xmlNode*, Layout*);
void setAbsolutePath(const std::string filePath);
void check_uppercase(std::string& str, std::vector<std::string>& compares, std::string message);
void check_lowercase(std::string& str, std::vector<std::string>& compares, std::string message);
Name _name;
Name _techno;
Parameters _params;
Netlist* _netlist;
Schematic* _schematic;
Sizing* _sizing;
Layout* _layout;
std::vector<std::string> _subCircuitsPathes;
Name _name;
std::string _absolutePath;
Name _techno;
Parameters _params;
Netlist* _netlist;
Schematic* _schematic;
Sizing* _sizing;
Layout* _layout;
std::vector<std::string> _subCircuitsPaths;
std::map<unsigned, SimulModel*> _simulModels;
};
inline Name Circuit::getName() { return _name; };
inline Name Circuit::getTechno() { return _techno; };
inline double Circuit::getValue(Name name) { return _params.getValue(name); };
inline Netlist* Circuit::getNetlist() { return _netlist; };
inline Schematic* Circuit::getSchematic() { return _schematic; };
inline Sizing* Circuit::getSizing() { return _sizing; };
inline Layout* Circuit::getLayout() { return _layout; };
inline void Circuit::addParameter(Name name, double value) { _params.addParameter(name, value); };
inline void Circuit::addParameter(Name name, std::string eqStr) { _params.addParameter(name, eqStr); };
inline Parameters Circuit::getParameters() { return _params; };
inline Name Circuit::getName() { return _name; }
inline Name Circuit::getTechno() { return _techno; }
inline double Circuit::getValue(Name name) { return _params.getValue(name); }
inline Netlist* Circuit::getNetlist() { return _netlist; }
inline Schematic* Circuit::getSchematic() { return _schematic; }
inline Sizing* Circuit::getSizing() { return _sizing; }
inline Layout* Circuit::getLayout() { return _layout; }
inline void Circuit::addParameter(Name name, double value) { _params.addParameter(name, value); }
inline void Circuit::addParameter(Name name, std::string eqStr) { _params.addParameter(name, eqStr); }
inline Parameters Circuit::getParameters() { return _params; }
inline void Circuit::addSubCircuitPath(std::string path) { _subCircuitsPaths.push_back(path); }
inline std::vector<std::string>& Circuit::getSubCircuitPaths() { return _subCircuitsPaths; }
} // namespace OpenChams

29
vlsisapd/src/openChams/src/vlsisapd/openChams/Net.h
View File

@ -16,6 +16,8 @@
namespace OpenChams {
class Netlist;
class Port;
class Wire;
class Net {
public:
class Connection {
@ -44,22 +46,37 @@ class Net {
//inline vector<pair<Name, Name> >::iterator getLastConnectionIt();
inline const std::vector<Net::Connection*>& getConnections();
// schematic relative methods
Port* addPort(Name type, unsigned idx, double x, double y, Name sym);
Wire* addWire();
inline bool hasNoPorts();
inline const std::vector<Port*>& getPorts();
inline bool hasNoWires();
inline const std::vector<Wire*>& getWires();
private:
Name _name;
Name _typeName;
bool _isExternal;
Netlist* _netlist;
std::vector<Net::Connection*> _connections; // <instanceName, connectorName>
// schematic relative members
std::vector<Port*> _ports;
std::vector<Wire*> _wires;
};
inline Name Net::getName() const { return _name; };
inline Name Net::getType() { return _typeName; };
inline bool Net::isExternal() { return _isExternal; };
inline Netlist* Net::getNetlist() { return _netlist; };
inline bool Net::hasNoConnections() { return (_connections.size() == 0)? true : false; };
inline Name Net::getName() const { return _name; }
inline Name Net::getType() { return _typeName; }
inline bool Net::isExternal() { return _isExternal; }
inline Netlist* Net::getNetlist() { return _netlist; }
inline bool Net::hasNoConnections() { return (_connections.size() == 0)? true : false; }
//inline vector<pair<Name, Name> >::iterator Net::getFirstConnectionIt() { return _connections.begin();};
//inline vector<pair<Name, Name> >::iterator Net::getLastConnectionIt() { return _connections.end();};
inline const std::vector<Net::Connection*>& Net::getConnections() { return _connections; };
inline const std::vector<Net::Connection*>& Net::getConnections() { return _connections; }
inline bool Net::hasNoPorts() { return (_ports.size() == 0)? true : false; }
inline const std::vector<Port*>& Net::getPorts() { return _ports; }
inline bool Net::hasNoWires() { return (_wires.size() == 0)? true : false; }
inline const std::vector<Wire*>& Net::getWires() { return _wires; }
inline Name Net::Connection::getInstanceName() const { return _instanceName; };
inline Name Net::Connection::getConnectorName() const { return _connectorName; };

6
vlsisapd/src/openChams/src/vlsisapd/openChams/Netlist.h
View File

@ -34,6 +34,7 @@ class Netlist {
inline bool hasNoNets();
inline const std::vector<Instance*>& getInstances();
inline const std::vector<Net*>& getNets();
inline Circuit* getCircuit();
private:
Circuit* _circuit;
@ -43,8 +44,9 @@ class Netlist {
inline bool Netlist::hasNoInstances() { return (_instances.size() == 0)? true : false; }
inline bool Netlist::hasNoNets() { return (_nets.size() == 0)? true : false; }
inline const std::vector<Instance*>& Netlist::getInstances() { return _instances; };
inline const std::vector<Net*>& Netlist::getNets() { return _nets; };
inline const std::vector<Instance*>& Netlist::getInstances() { return _instances; }
inline const std::vector<Net*>& Netlist::getNets() { return _nets; }
inline Circuit* Netlist::getCircuit() { return _circuit; }
} // namespace
#endif

43
vlsisapd/src/openChams/src/vlsisapd/openChams/Port.h Normal file
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@ -0,0 +1,43 @@
/*
* Port.h
* openChams
*
* Created by damien dupuis on 08/02/11.
* Copyright 2011 UPMC / LIP6. All rights reserved.
*
*/
#ifndef __OPENCHAMS_PORT_H__
#define __OPENCHAMS_PORT_H__
#include "vlsisapd/openChams/Name.h"
namespace OpenChams {
class Port {
public:
Port(Name type, unsigned idx , double x, double y, Name sym): _type(type), _idx(idx), _x(x), _y(y), _sym(sym) {}
~Port() {}
inline Name getType() const;
inline unsigned getIndex() const;
inline double getX() const;
inline double getY() const;
inline Name getSymmetry() const;
private:
Name _type;
unsigned _idx;
double _x;
double _y;
Name _sym;
};
inline Name Port::getType() const { return _type; }
inline unsigned Port::getIndex() const { return _idx; }
inline double Port::getX() const { return _x; }
inline double Port::getY() const { return _y; }
inline Name Port::getSymmetry() const { return _sym; }
} // namespace
#endif

5
vlsisapd/src/openChams/src/vlsisapd/openChams/Schematic.h
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@ -33,21 +33,18 @@ class Schematic {
Name _sym;
};
public:
Schematic(Circuit*, double);
Schematic(Circuit*);
void addInstance(Name instanceName, double x, double y, Name sym );
inline double getZoom();
inline bool hasNoInstances();
inline const std::map<Name, Infos*>& getInstances();
private:
Circuit* _circuit;
double _zoom;
std::map<Name, Infos*> _instances;
};
inline double Schematic::getZoom() { return _zoom; };
inline bool Schematic::hasNoInstances() { return (_instances.size() == 0) ? true : false; };
inline const std::map<Name, Schematic::Infos*>& Schematic::getInstances() { return _instances; };

87
vlsisapd/src/openChams/src/vlsisapd/openChams/Wire.h Normal file
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@ -0,0 +1,87 @@
/*
* Wire.h
* openChams
*
* Created by damien dupuis on 08/02/11.
* Copyright 2011 UPMC / LIP6. All rights reserved.
*
*/
#ifndef __OPENCHAMS_WIRE_H__
#define __OPENCHAMS_WIRE_H__
#include <vector>
#include "vlsisapd/openChams/Name.h"
namespace OpenChams {
class WirePoint {
public:
WirePoint() {}
virtual ~WirePoint() {};
};
class InstancePoint: public WirePoint {
private:
Name _name;
Name _plug;
public:
InstancePoint(Name name, Name plug): _name(name), _plug(plug) {}
virtual ~InstancePoint() {}
inline Name getName() { return _name; }
inline Name getPlug() { return _plug; }
};
class PortPoint: public WirePoint {
private:
unsigned _idx;
public:
PortPoint(unsigned idx): _idx(idx) {}
virtual ~PortPoint() {}
inline unsigned getIndex() { return _idx; }
};
class IntermediatePoint: public WirePoint {
private:
double _x;
double _y;
public:
IntermediatePoint(double x, double y): _x(x), _y(y) {}
virtual ~IntermediatePoint() {}
inline double getX() { return _x; }
inline double getY() { return _y; }
};
class Wire {
private:
WirePoint* _start;
WirePoint* _end;
std::vector<IntermediatePoint*> _inters;
public:
Wire(): _start(NULL), _end(NULL), _inters() {}
~Wire() {}
// Accessors
inline WirePoint* getStartPoint() { return _start; }
inline WirePoint* getEndPoint() { return _end; }
inline bool hasNoIntermediatePoints() { return (_inters.size() == 0)? true : false; }
inline const std::vector<IntermediatePoint*>& getIntermediatePoints() { return _inters; }
// Modifiers
void setStartPoint(Name name, Name plug);
void setStartPoint(unsigned idx);
void setEndPoint(Name name, Name plug);
void setEndPoint(unsigned idx);
void addIntermediatePoint(double x, double y);
};
} // namespace
#endif