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Try VH topologies for G180MCU. Not working either...

This commit is contained in:
Jean-Paul Chaput 2023-07-03 20:02:33 +02:00
parent 73265c2d68
commit 3243b12abb
2 changed files with 21 additions and 18 deletions
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19
crlcore/python/technos/node180/gf180mcu/mcu9t5v0.py
View File

@ -11,6 +11,7 @@ from coriolis.CRL import AllianceFramework, Gds, LefImport, CellGa
RoutingGauge, RoutingLayerGauge
from coriolis.helpers import l, u, n, overlay, io, ndaTopDir
from coriolis.helpers.overlay import CfgCache, UpdateSession
from coriolis.Anabatic import StyleFlags
__all__ = [ "setup" ]
@ -27,7 +28,7 @@ def _routing ():
rg.setSymbolic( False )
rg.addLayerGauge(
RoutingLayerGauge.create( tech.getLayer( 'Metal1' ) # metal
, RoutingLayerGauge.Vertical # preferred routing direction
, RoutingLayerGauge.Horizontal # preferred routing direction
, RoutingLayerGauge.PinOnly # layer usage
, 0 # depth
, 0.0 # density (deprecated)
@ -39,7 +40,7 @@ def _routing ():
, u(0.0 ) )) # obstacle dW
rg.addLayerGauge(
RoutingLayerGauge.create( tech.getLayer( 'Metal2' ) # metal
, RoutingLayerGauge.Horizontal # preferred routing direction
, RoutingLayerGauge.Vertical # preferred routing direction
, RoutingLayerGauge.Default # layer usage
, 1 # depth
, 0.0 # density (deprecated)
@ -48,10 +49,10 @@ def _routing ():
, u(0.28) # wire width
, u(0.28) # perpandicular wire width
, u(0.26) # VIA side
, u(0.0 ) )) # obstacle dW
, u(0.0 ) )) # obstacle dW
rg.addLayerGauge(
RoutingLayerGauge.create( tech.getLayer( 'Metal3' ) # metal
, RoutingLayerGauge.Vertical # preferred routing direction
, RoutingLayerGauge.Horizontal # preferred routing direction
, RoutingLayerGauge.Default # layer usage
, 2 # depth
, 0.0 # density (deprecated)
@ -63,7 +64,7 @@ def _routing ():
, u(0.0 ) )) # obstacle dW
rg.addLayerGauge(
RoutingLayerGauge.create( tech.getLayer( 'Metal4' ) # metal
, RoutingLayerGauge.Horizontal # preferred routing direction
, RoutingLayerGauge.Vertical # preferred routing direction
, RoutingLayerGauge.Default # layer usage
, 3 # depth
, 0.0 # density (deprecated)
@ -75,7 +76,7 @@ def _routing ():
, u(0.0 ) )) # obstacle dW
rg.addLayerGauge(
RoutingLayerGauge.create( tech.getLayer( 'Metal5' ) # metal
, RoutingLayerGauge.Vertical # preferred routing direction
, RoutingLayerGauge.Horizontal # preferred routing direction
, RoutingLayerGauge.Default # layer usage
, 4 # depth
, 0.0 # density (deprecated)
@ -87,7 +88,7 @@ def _routing ():
, u(0.0 ) )) # obstacle dW
rg.addLayerGauge(
RoutingLayerGauge.create( tech.getLayer( 'MetalTop' ) # metal
, RoutingLayerGauge.Horizontal # preferred routing direction
, RoutingLayerGauge.Vertical # preferred routing direction
, RoutingLayerGauge.PowerSupply # layer usage
, 5 # depth
, 0.0 # density (deprecated)
@ -161,7 +162,9 @@ def _routing ():
cfg.anabatic.globalIterations = [ 1, 100 ]
cfg.anabatic.gcell.displayMode = 1
cfg.anabatic.gcell.displayMode = (("Boundary", 1), ("Density", 2))
cfg.katana.disableStackedVias = True
cfg.anabatic.netBuilderStyle = 'VH,3RL+'
cfg.anabatic.routingStyle = StyleFlags.VH
cfg.katana.disableStackedVias = False
cfg.katana.hTracksReservedLocal = 4
cfg.katana.hTracksReservedLocal = [0, 20]
cfg.katana.vTracksReservedLocal = 3

20
crlcore/python/technos/node180/gf180mcu/techno.py
View File

@ -80,20 +80,20 @@ def _setup_techno():
setEnclosures( CONT, Poly2 , u(0.07) )
setEnclosures( CONT, Metal1, u(0.12) )
VIA12 = createVia( tech, 'VIA12', 'Metal1', 'Via1', 'Metal2', u(0.26) )
setEnclosures( VIA12, Metal1, u(0.06) )
setEnclosures( VIA12, Metal2, u(0.06) )
setEnclosures( VIA12, Metal1, (u(0.06), u(0.00)) )
setEnclosures( VIA12, Metal2, (u(0.06), u(0.01)) )
VIA23 = createVia( tech, 'VIA23', 'Metal2', 'Via2', 'Metal3', u(0.26) )
setEnclosures( VIA23, Metal2, u(0.06) )
setEnclosures( VIA23, Metal3, u(0.06) )
setEnclosures( VIA23, Metal2, (u(0.06), u(0.01)) )
setEnclosures( VIA23, Metal3, (u(0.01), u(0.06)) )
VIA34 = createVia( tech, 'VIA34', 'Metal3', 'Via3', 'Metal4', u(0.26) )
setEnclosures( VIA34, Metal3, u(0.06) )
setEnclosures( VIA34, Metal4, u(0.06) )
setEnclosures( VIA34, Metal3, (u(0.01), u(0.06)) )
setEnclosures( VIA34, Metal4, (u(0.06), u(0.01)) )
VIA45 = createVia( tech, 'VIA45', 'Metal4', 'Via4', 'Metal5', u(0.26) )
setEnclosures( VIA45, Metal4, u(0.06) )
setEnclosures( VIA45, Metal5, u(0.06) )
setEnclosures( VIA45, Metal4, (u(0.06), u(0.01)) )
setEnclosures( VIA45, Metal5, (u(0.01), u(0.06)) )
VIA5T = createVia( tech, 'VIA5T', 'Metal5', 'Via5', 'MetalTop', u(0.26) )
setEnclosures( VIA5T, Metal5 , u(0.06) )
setEnclosures( VIA5T, MetalTop, u(0.06) )
setEnclosures( VIA5T, Metal5 , (u(0.01), u(0.06)) )
setEnclosures( VIA5T, MetalTop, (u(0.06), u(0.01)) )
Border = createBL( tech, 'Border', BasicLayer.Material.other, gds2Layer=63 )