From 2e015ea78025b35d6d156ded790f5cbd6771c225 Mon Sep 17 00:00:00 2001 From: Jean-Paul Chaput Date: Sun, 13 Jun 2021 12:03:57 +0200 Subject: [PATCH] Prune ordinary wires in Katana::PowerRails. * Change: In Katana::PowerRails, in TerminalNetlist cells instances, the ordinary nets components where generating obstacles, leading to stupid cross blockages between the obstacle generated by the component supporting the routing pad and the RP itself. Now only take into account supplies and clocks (any layers) and blockage layers. Fix symbolic benches. --- katana/src/PowerRails.cpp | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/katana/src/PowerRails.cpp b/katana/src/PowerRails.cpp index 3942158a..23a62662 100644 --- a/katana/src/PowerRails.cpp +++ b/katana/src/PowerRails.cpp @@ -915,9 +915,10 @@ namespace { virtual void doQuery (); inline void doLayout (); inline uint32_t getGoMatchCount () const; + inline RoutingGauge* getRoutingGauge () const; private: AllianceFramework* _framework; - KatanaEngine* _katana; + KatanaEngine* _katana; RoutingGauge* _routingGauge; const ChipTools& _chipTools; PowerRailsPlanes _powerRailsPlanes; @@ -957,6 +958,10 @@ namespace { { return _powerRailsPlanes.doLayout(); } + inline RoutingGauge* QueryPowerRails::getRoutingGauge () const + { return _routingGauge; } + + bool QueryPowerRails::hasBasicLayer ( const BasicLayer* basicLayer ) { return _powerRailsPlanes.hasPlane ( basicLayer ); } @@ -1031,6 +1036,12 @@ namespace { cdebug_log(159,0) << " rootNet " << rootNet << " (" << rootNet->isClock() << ") " << go->getCell() << " (" << go->getCell()->isTerminal() << ")" << endl; + // unsigned int type = _powerRailsPlanes.getActivePlane()->getRoutingPlane()->getLayerGauge()->getType(); + if (go->getCell()->isTerminalNetlist()) { + if (not rootNet->isSupply() and not rootNet->isClock() and not _isBlockagePlane) + return; + } + const Segment* segment = dynamic_cast(component); if ( segment != NULL ) { _goMatchCount++;