Do not generate IEEE VHDL when driving vst files (silly me).
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@ -39,7 +39,10 @@ namespace CRL {
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void vstDriver ( const string cellPath, Cell *cell, unsigned int &saveState )
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void vstDriver ( const string cellPath, Cell *cell, unsigned int &saveState )
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{
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{
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NamingScheme::toVhdl( cell, NamingScheme::FromVerilog );
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NamingScheme::toVhdl( cell, NamingScheme::FromVerilog );
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Vhdl::Entity* vhdlEntity = Vhdl::EntityExtension::create( cell, Vhdl::Entity::EntityMode|Vhdl::Entity::IeeeMode );
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Vhdl::Entity* vhdlEntity = Vhdl::EntityExtension::create( cell
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, Vhdl::Entity::EntityMode
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//| Vhdl::Entity::IeeeMode
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);
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string celltest = cellPath;
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string celltest = cellPath;
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ofstream ccelltest ( celltest.c_str() );
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ofstream ccelltest ( celltest.c_str() );
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