From 1693eb500e7fed710bbe3e6127ff0896585c307c Mon Sep 17 00:00:00 2001 From: Jean-Manuel Caba Date: Mon, 2 Aug 2010 13:07:12 +0000 Subject: [PATCH] o correcting layer id (extractNumber) handling in driver o add sxlib2lef method we use to compare in test dir --- .../src/ccore/openaccess/OpenAccessDriver.cpp | 133 +- crlcore/src/ccore/openaccess/test/Makefile | 3 + .../ccore/openaccess/test/sxlib2lef/Makefile | 14 + .../src/ccore/openaccess/test/sxlib2lef/cells | 95 + .../openaccess/test/sxlib2lef/cmos.lef.bak | 435 + .../openaccess/test/sxlib2lef/sxlib.lef.bak | 8417 +++++++++++++++++ 6 files changed, 9060 insertions(+), 37 deletions(-) create mode 100644 crlcore/src/ccore/openaccess/test/sxlib2lef/Makefile create mode 100644 crlcore/src/ccore/openaccess/test/sxlib2lef/cells create mode 100644 crlcore/src/ccore/openaccess/test/sxlib2lef/cmos.lef.bak create mode 100644 crlcore/src/ccore/openaccess/test/sxlib2lef/sxlib.lef.bak diff --git a/crlcore/src/ccore/openaccess/OpenAccessDriver.cpp b/crlcore/src/ccore/openaccess/OpenAccessDriver.cpp index 8da9b80e..92eecb8c 100644 --- a/crlcore/src/ccore/openaccess/OpenAccessDriver.cpp +++ b/crlcore/src/ccore/openaccess/OpenAccessDriver.cpp @@ -1,5 +1,5 @@ // -*-compile-command:"cd ../../../../.. && make"-*- -// Time-stamp: "2010-07-30 16:44:00" - OpenAccessDriver.cpp +// Time-stamp: "2010-08-02 14:58:55" - OpenAccessDriver.cpp // x-----------------------------------------------------------------x // | This file is part of the hurricaneAMS Software. | // | Copyright (c) UPMC/LIP6 2008-2010, All Rights Reserved | @@ -54,15 +54,16 @@ namespace { Cell2OADesignMap _cell2OADesign4Layout; Instance2OAInstsMap _instance2OAInst; Layer2OAPhysicalLayerMap _layer2OAPhysicalLayer; + set _layerIDS; + int _layerID; + oaLayer* _layerDev; + oaLayer* _layerPin; + oaLayer* _layerText; + oaLayer* _layerWire; DataBase* _db; Technology* _technology; - int _layerID; - oaLayer* layerDev; - oaLayer* layerPin; - oaLayer* layerText; - oaLayer* layerWire; public: - OADriver(const string& path): + OADriver(const string& path) : _path(path), _oaTech(NULL), _library2OALib(), @@ -72,9 +73,14 @@ namespace { _cell2OADesign4Layout(), _instance2OAInst(), _layer2OAPhysicalLayer(), + _layerIDS(), + _layerID(0), + _layerDev(NULL), + _layerPin(NULL), + _layerText(NULL), + _layerWire(NULL), _db(NULL), - _technology(NULL), - _layerID(0) { + _technology(NULL) { _db = DataBase::getDB(); if (!_db) { throw Error("no database"); @@ -103,9 +109,7 @@ namespace { } /** - Create an empty oaLib from a Library - no cells are added in this oaLib - all sub Library are also converted. + create a oaLib from a Library */ oaLib* getOALibForLibrary(const Library* library) { cerr << "getOALibForLibrary" << endl; @@ -140,11 +144,39 @@ namespace { return lib; } + /** + handle layerID i.e: get extractNumber in Hurricane world if + possible ... + */ + int generateLayerID(BasicLayer* bLayer){ + // the layer number is unique to a particular layer + cerr << "generateLayerID -> "; + int numLayer = _layerID; + if(bLayer){ + numLayer = bLayer->getExtractNumber(); + if(_layerIDS.find(numLayer) == _layerIDS.end()){ + cerr << "getExtractNumber " << numLayer << endl; + _layerIDS.insert(numLayer); + return numLayer; + } + } + + cerr << " while(...) "; + set::iterator it; + while((it = _layerIDS.find(_layerID)) != _layerIDS.end()){ + numLayer = ++_layerID; + } + cerr << numLayer << endl; + _layerIDS.insert(numLayer); + return numLayer; + } + /** convert oaLayer from a Layer ... */ - oaLayer* getOALayerFromLayer(Layer* layer,oaTech* theOATech) { + oaPhysicalLayer* getOALayerFromLayer(Layer* layer,oaTech* theOATech) { assert(layer); + cerr << "getOALayerFromLayer " << getString(layer->getName()) << endl; Layer2OAPhysicalLayerMap::iterator it = _layer2OAPhysicalLayer.find(layer); if (it != _layer2OAPhysicalLayer.end()) { return it->second; @@ -157,24 +189,25 @@ namespace { aOALayer = oaPhysicalLayer::find(theOATech, layerName, true); if(aOALayer){ _layer2OAPhysicalLayer[layer] = aOALayer; + _layerIDS.insert(aOALayer->getNumber()); return aOALayer; } BasicLayer* bLayer = dynamic_cast(layer); - if(bLayer) - aOALayer = oaPhysicalLayer::create(theOATech, layerName, _layerID++,getOAMaterial(bLayer->getMaterial())); - else - aOALayer = oaPhysicalLayer::create(theOATech, layerName, _layerID++); + aOALayer = oaPhysicalLayer::create(theOATech, layerName, generateLayerID(bLayer), + bLayer ? getOAMaterial(bLayer->getMaterial()) + : oaMaterial(oacOtherMaterial)); assert(aOALayer); _layer2OAPhysicalLayer[layer] = aOALayer; +#if 0 //create and add layer constraint for Layer specific manufacturing rules cerr << " o get value for constraint" << endl; long minSize = Hurricane::DbU::getDb(layer->getMinimalSize()); long minSpace = Hurricane::DbU::getDb(layer->getMinimalSpacing()); long pitch = Hurricane::DbU::getDb(layer->getPitch()); -#if 0 + cerr << " o create constraint for min size : " << pitch << endl; oaLayerConstraint* cMinSize = NULL; try{ @@ -206,9 +239,6 @@ namespace { oaIntValue::create(theOATech->getLib(),pitch)); assert(cPitchV); #endif - if(bLayer){ - unsigned gdsIInumber = bLayer->getExtractNumber(); - } return aOALayer; } @@ -253,22 +283,55 @@ namespace { oaConstraintGroup *cgFoundry = theOATech->getFoundryRules(); /* - add the constraint group LEFDefaultRouteSpec for oa2lef + add the constraint group LEFDefaultRouteSpec for oa2lef */ - - //first create "utility" layers following : - layerDev = oaPhysicalLayer::create(theOATech, "device", _layerID++); - layerText = oaPhysicalLayer::create(theOATech, "text", _layerID++); - layerPin = oaPhysicalLayer::create(theOATech, "pin", _layerID++); - layerWire = oaPhysicalLayer::create(theOATech, "wire", _layerID++); + } // get or create physical layer - + //first convert basicLayers and use the getExtractNumber + for_each_basic_layer(layer, technology->getBasicLayers()) { + getOALayerFromLayer(layer,theOATech); + end_for; + } + //then convert all other layers unsing a generated ID for_each_layer(layer, technology->getLayers()) { getOALayerFromLayer(layer,theOATech); end_for; } + cerr << "test" << endl; + try{ + //create or find "utility" layers following : + _layerDev = oaLayer::find(theOATech,"device"); + if(!_layerDev) + _layerDev = oaPhysicalLayer::create(theOATech, "device", generateLayerID(NULL)); + assert(_layerDev); + _layerIDS.insert(_layerDev->getNumber()); + + _layerText = oaLayer::find(theOATech,"text"); + if(!_layerText) + _layerText = oaPhysicalLayer::create(theOATech, "text", generateLayerID(NULL)); + assert(_layerText); + _layerIDS.insert(_layerText->getNumber()); + + _layerPin = oaLayer::find(theOATech,"pin"); + if(!_layerPin) + _layerPin = oaPhysicalLayer::create(theOATech, "pin", generateLayerID(NULL)); + assert(_layerPin); + _layerIDS.insert(_layerPin->getNumber()); + + _layerWire = oaLayer::find(theOATech,"wire"); + if(!_layerWire) + _layerWire = oaPhysicalLayer::create(theOATech, "wire", generateLayerID(NULL)); + assert(_layerWire); + _layerIDS.insert(_layerWire->getNumber()); + }catch(oaException&e ){ + cerr << "OA:" << e.getMsg() << endl; + exit(-2); + }catch(std::exception&e ){ + cerr << "STD:" << e.what() << endl; + exit(-1); + } printOALayers(theOATech); return theOATech; @@ -337,9 +400,9 @@ namespace { oaScalarName scNetName(ns, getString(net->getName()).c_str()); oaTerm* term = oaTerm::find(blockNet->getBlock(), scNetName); assert(term); - + oaPin* pin = oaPin::create(term); - + return pin; } @@ -351,11 +414,7 @@ namespace { getOABoxForBox(box, component->getBoundingBox()); Layer* layer = (Layer*) component->getLayer(); assert(layer); - oaPhysicalLayer* physLayer = NULL; - Layer2OAPhysicalLayerMap::iterator it = _layer2OAPhysicalLayer.find(layer); - if (it != _layer2OAPhysicalLayer.end()) { - physLayer = it->second; - } + oaPhysicalLayer* physLayer = getOALayerFromLayer(layer,_oaTech); assert(physLayer); oaLayerNum layerNum = physLayer->getNumber(); oaRect* rect = oaRect::create(topBlock, @@ -494,7 +553,7 @@ namespace { } oaBlock *topBlock = designCellView->getTopBlock(); assert(topBlock); - + return designCellView; } diff --git a/crlcore/src/ccore/openaccess/test/Makefile b/crlcore/src/ccore/openaccess/test/Makefile index 2be11892..ab394b35 100644 --- a/crlcore/src/ccore/openaccess/test/Makefile +++ b/crlcore/src/ccore/openaccess/test/Makefile @@ -11,6 +11,9 @@ debug: ddd: ddd -args ./x86_64/usr/local/bin/testOAWrapper /asim/chams/etc/chams/config.freePDK45.xml /tmp/testOA +valgrind: + valgrind ./x86_64/usr/local/bin/testOAWrapper /asim/chams/etc/chams/config.freePDK45.xml /tmp/testOA + rmtmp: rm -rf /tmp/* diff --git a/crlcore/src/ccore/openaccess/test/sxlib2lef/Makefile b/crlcore/src/ccore/openaccess/test/sxlib2lef/Makefile new file mode 100644 index 00000000..05780c6a --- /dev/null +++ b/crlcore/src/ccore/openaccess/test/sxlib2lef/Makefile @@ -0,0 +1,14 @@ + +all: sxlib.lef + lef2oa -lib sxlib -lef sxlib.lef + +sxlib.lef: + grep -v "END LIBRARY" cmos.lef.bak > sxlib.lef ; for i in $$(cat cells) ; do sxlib2lef $$i ; cat $$i.lef >> sxlib.lef ; done + echo "END LIBRARY" >> sxlib.lef + cp sxlib.lef sxlib.lef.bak + +mrproper: clean + rm -rf sxlib cds.lib + +clean: + rm -rf *.log *.slog *~ encounter* *.lef diff --git a/crlcore/src/ccore/openaccess/test/sxlib2lef/cells b/crlcore/src/ccore/openaccess/test/sxlib2lef/cells new file mode 100644 index 00000000..c5616138 --- /dev/null +++ b/crlcore/src/ccore/openaccess/test/sxlib2lef/cells @@ -0,0 +1,95 @@ +a2_x2 +a2_x4 +a3_x2 +a3_x4 +a4_x2 +a4_x4 +an12_x1 +an12_x4 +ao22_x2 +ao22_x4 +ao2o22_x2 +ao2o22_x4 +buf_x2 +buf_x4 +buf_x8 +fulladder_x2 +fulladder_x4 +halfadder_x2 +halfadder_x4 +inv_x1 +inv_x2 +inv_x4 +inv_x8 +mx2_x2 +mx2_x4 +mx3_x2 +mx3_x4 +na2_x1 +na2_x4 +na3_x1 +na3_x4 +na4_x1 +na4_x4 +nao22_x1 +nao22_x4 +nao2o22_x1 +nao2o22_x4 +nmx2_x1 +nmx2_x4 +nmx3_x1 +nmx3_x4 +no2_x1 +no2_x4 +no3_x1 +no3_x4 +no4_x1 +no4_x4 +noa22_x1 +noa22_x4 +noa2a22_x1 +noa2a22_x4 +noa2a2a23_x1 +noa2a2a23_x4 +noa2a2a2a24_x1 +noa2a2a2a24_x4 +noa2ao222_x1 +noa2ao222_x4 +noa3ao322_x1 +noa3ao322_x4 +nts_x1 +nts_x2 +nxr2_x1 +nxr2_x4 +o2_x2 +o2_x4 +o3_x2 +o3_x4 +o4_x2 +o4_x4 +oa22_x2 +oa22_x4 +oa2a22_x2 +oa2a22_x4 +oa2a2a23_x2 +oa2a2a23_x4 +oa2a2a2a24_x2 +oa2a2a2a24_x4 +oa2ao222_x2 +oa2ao222_x4 +oa3ao322_x2 +oa3ao322_x4 +on12_x1 +on12_x4 +one_x0 +powmid_x0 +rowend_x0 +sff1_x4 +sff2_x4 +sff3_x4 +tie_x0 +ts_x4 +ts_x8 +xr2_x1 +xr2_x4 +zero_x0 diff --git a/crlcore/src/ccore/openaccess/test/sxlib2lef/cmos.lef.bak b/crlcore/src/ccore/openaccess/test/sxlib2lef/cmos.lef.bak new file mode 100644 index 00000000..f9b7fa1c --- /dev/null +++ b/crlcore/src/ccore/openaccess/test/sxlib2lef/cmos.lef.bak @@ -0,0 +1,435 @@ +# +# $Id: cmos.lef,v 1.6 2005/03/01 14:59:15 jpc Exp $ +# +# /------------------------------------------------------------------\ +# | | +# | A l l i a n c e C A D S y s t e m | +# | S i l i c o n E n s e m b l e / A l l i a n c e | +# | | +# | Author : Jean-Paul CHAPUT | +# | E-mail : alliance-users@asim.lip6.fr | +# | ================================================================ | +# | LEF : "./cmos_12.lef" | +# | **************************************************************** | +# | U p d a t e s | +# | | +# \------------------------------------------------------------------/ +# + + +VERSION 5.2 ; +NAMESCASESENSITIVE ON ; +BUSBITCHARS "()" ; +DIVIDERCHAR "." ; + +#NOWIREEXTENSIONATPIN ON ; + + +#UNITS +# DATABASE MICRONS 100 ; +#END UNITS + + +LAYER POLY + TYPE MASTERSLICE ; +END POLY + + +LAYER VIAP + TYPE CUT ; +END VIAP + + +LAYER ALU1 + TYPE ROUTING ; + WIDTH 2.00 ; + SPACING 3.00 ; + PITCH 5.00 ; + DIRECTION VERTICAL ; + CAPACITANCE CPERSQDIST 0.000032 ; + RESISTANCE RPERSQ 0.100000 ; +END ALU1 + + +LAYER VIA1 + TYPE CUT ; +END VIA1 + + +LAYER ALU2 + TYPE ROUTING ; + WIDTH 2.00 ; + SPACING 3.00 ; + PITCH 5.00 ; + DIRECTION HORIZONTAL ; + CAPACITANCE CPERSQDIST 0.000032 ; + RESISTANCE RPERSQ 0.100000 ; +END ALU2 + + +LAYER VIA2 + TYPE CUT ; +END VIA2 + + +LAYER ALU3 + TYPE ROUTING ; + WIDTH 2.00 ; + SPACING 3.00 ; + PITCH 5.00 ; + DIRECTION VERTICAL ; + CAPACITANCE CPERSQDIST 0.000032 ; + RESISTANCE RPERSQ 0.100000 ; +END ALU3 + + +LAYER VIA3 + TYPE CUT ; +END VIA3 + + +LAYER ALU4 + TYPE ROUTING ; + WIDTH 2.00 ; + SPACING 3.00 ; + PITCH 5.00 ; + DIRECTION HORIZONTAL ; + CAPACITANCE CPERSQDIST 0.000032 ; + RESISTANCE RPERSQ 0.100000 ; +END ALU4 + + +LAYER VIA4 + TYPE CUT ; +END VIA4 + + +LAYER ALU5 + TYPE ROUTING ; + WIDTH 2.00 ; + SPACING 3.00 ; + PITCH 5.00 ; + DIRECTION VERTICAL ; + CAPACITANCE CPERSQDIST 0.000032 ; + RESISTANCE RPERSQ 0.100000 ; +END ALU5 + + +LAYER VIA5 + TYPE CUT ; +END VIA5 + + +LAYER ALU6 + TYPE ROUTING ; + WIDTH 2.00 ; + SPACING 3.00 ; + PITCH 5.00 ; + DIRECTION HORIZONTAL ; + CAPACITANCE CPERSQDIST 0.000032 ; + RESISTANCE RPERSQ 0.100000 ; +END ALU6 + + +#VIA CONT_POLY DEFAULT +# LAYER POLY ; +# RECT -1.50 -1.50 1.50 1.50 ; +# LAYER VIAP ; +# RECT -0.50 -0.50 0.50 0.50 ; +# LAYER ALU1 ; +# RECT -1.00 -1.00 1.00 1.00 ; +#END CONT_POLY + + +VIA CONT_VIA DEFAULT + LAYER ALU1 ; + RECT -1.00 -1.00 1.00 1.00 ; + LAYER VIA1 ; + RECT -0.50 -0.50 0.50 0.50 ; + LAYER ALU2 ; + RECT -1.00 -1.00 1.00 1.00 ; +END CONT_VIA + + +VIA CONT_VIA2 DEFAULT + LAYER ALU3 ; + RECT -1.00 -1.00 1.00 1.00 ; + LAYER VIA2 ; + RECT -0.50 -0.50 0.50 0.50 ; + LAYER ALU2 ; + RECT -1.00 -1.00 1.00 1.00 ; +END CONT_VIA2 + + +VIA CONT_VIA3 DEFAULT + LAYER ALU4 ; + RECT -1.00 -1.00 1.00 1.00 ; + LAYER VIA3 ; + RECT -0.50 -0.50 0.50 0.50 ; + LAYER ALU3 ; + RECT -1.00 -1.00 1.00 1.00 ; +END CONT_VIA3 + + +VIA CONT_VIA4 DEFAULT + LAYER ALU5 ; + RECT -1.00 -1.00 1.00 1.00 ; + LAYER VIA4 ; + RECT -0.50 -0.50 0.50 0.50 ; + LAYER ALU4 ; + RECT -1.00 -1.00 1.00 1.00 ; +END CONT_VIA4 + + +VIA CONT_VIA5 DEFAULT + LAYER ALU6 ; + RECT -1.00 -1.00 1.00 1.00 ; + LAYER VIA5 ; + RECT -0.50 -0.50 0.50 0.50 ; + LAYER ALU5 ; + RECT -1.00 -1.00 1.00 1.00 ; +END CONT_VIA5 + + +VIARULE TURN_ALU1 GENERATE + LAYER ALU1 ; + DIRECTION vertical ; + + LAYER ALU1 ; + DIRECTION horizontal ; +END TURN_ALU1 + + +VIARULE TURN_ALU2 GENERATE + LAYER ALU2 ; + DIRECTION vertical ; + + LAYER ALU2 ; + DIRECTION horizontal ; +END TURN_ALU2 + + +VIARULE TURN_ALU3 GENERATE + LAYER ALU3 ; + DIRECTION vertical ; + + LAYER ALU3 ; + DIRECTION horizontal ; +END TURN_ALU3 + + +VIARULE TURN_ALU4 GENERATE + LAYER ALU4 ; + DIRECTION vertical ; + + LAYER ALU4 ; + DIRECTION horizontal ; +END TURN_ALU4 + + +VIARULE TURN_ALU5 GENERATE + LAYER ALU5 ; + DIRECTION vertical ; + + LAYER ALU5 ; + DIRECTION horizontal ; +END TURN_ALU5 + + +VIARULE TURN_ALU6 GENERATE + LAYER ALU6 ; + DIRECTION vertical ; + + LAYER ALU6 ; + DIRECTION horizontal ; +END TURN_ALU6 + + +#VIARULE VIA1_HV +# LAYER ALU1 ; +# DIRECTION VERTICAL ; +# OVERHANG 0.50 ; +# METALOVERHANG 0.50 ; +# +# LAYER ALU2 ; +# DIRECTION HORIZONTAL ; +# OVERHANG 0.50 ; +# METALOVERHANG 0.50 ; +# +# VIA CONT_VIA ; +#END VIA1_HV +# +# +#VIARULE VIA2_VH +# LAYER ALU2 ; +# DIRECTION HORIZONTAL ; +# OVERHANG 0.50 ; +# METALOVERHANG 0.50 ; +# +# LAYER ALU3 ; +# DIRECTION VERTICAL ; +# OVERHANG 0.50 ; +# METALOVERHANG 0.50 ; +# +# VIA CONT_VIA2 ; +#END VIA2_VH +# +# +#VIARULE VIA3_VH +# LAYER ALU3 ; +# DIRECTION HORIZONTAL ; +# OVERHANG 0.50 ; +# METALOVERHANG 0.50 ; +# +# LAYER ALU4 ; +# DIRECTION VERTICAL ; +# OVERHANG 0.50 ; +# METALOVERHANG 0.50 ; +# +# VIA CONT_VIA3 ; +#END VIA3_VH + + +VIARULE genVIA1_HV GENERATE + LAYER ALU1 ; + DIRECTION VERTICAL ; + OVERHANG 0.50 ; + METALOVERHANG 0.50 ; + + LAYER ALU2 ; + DIRECTION HORIZONTAL ; + OVERHANG 0.50 ; + METALOVERHANG 0.50 ; + + LAYER VIA1 ; + RECT -0.50 -0.50 0.50 0.50 ; + SPACING 3.00 BY 3.00 ; +END genVIA1_HV + + +VIARULE genVIA1_VH GENERATE + LAYER ALU1 ; + DIRECTION HORIZONTAL ; + OVERHANG 0.50 ; + METALOVERHANG 0.50 ; + + LAYER ALU2 ; + DIRECTION VERTICAL ; + OVERHANG 0.50 ; + METALOVERHANG 0.50 ; + + LAYER VIA1 ; + RECT -0.50 -0.50 0.50 0.50 ; + SPACING 3.00 BY 3.00 ; +END genVIA1_VH + + +VIARULE genVIA2_VH GENERATE + LAYER ALU2 ; + DIRECTION HORIZONTAL ; + OVERHANG 0.50 ; + METALOVERHANG 0.50 ; + + LAYER ALU3 ; + DIRECTION VERTICAL ; + OVERHANG 0.50 ; + METALOVERHANG 0.50 ; + + LAYER VIA2 ; + RECT -0.50 -0.50 0.50 0.50 ; + SPACING 3.00 BY 3.00 ; +END genVIA2_VH + + +VIARULE genVIA2_HV GENERATE + LAYER ALU2 ; + DIRECTION VERTICAL ; + OVERHANG 0.50 ; + METALOVERHANG 0.50 ; + + LAYER ALU3 ; + DIRECTION HORIZONTAL ; + OVERHANG 0.50 ; + METALOVERHANG 0.50 ; + + LAYER VIA2 ; + RECT -0.50 -0.50 0.50 0.50 ; + SPACING 3.00 BY 3.00 ; +END genVIA2_HV + + +VIARULE genVIA3_VH GENERATE + LAYER ALU3 ; + DIRECTION HORIZONTAL ; + OVERHANG 0.50 ; + METALOVERHANG 0.50 ; + + LAYER ALU4 ; + DIRECTION VERTICAL ; + OVERHANG 0.50 ; + METALOVERHANG 0.50 ; + + LAYER VIA3 ; + RECT -0.50 -0.50 0.50 0.50 ; + SPACING 3.00 BY 3.00 ; +END genVIA3_VH + + +VIARULE genVIA3_HV GENERATE + LAYER ALU3 ; + DIRECTION VERTICAL ; + OVERHANG 0.50 ; + METALOVERHANG 0.50 ; + + LAYER ALU4 ; + DIRECTION HORIZONTAL ; + OVERHANG 0.50 ; + METALOVERHANG 0.50 ; + + LAYER VIA3 ; + RECT -0.50 -0.50 0.50 0.50 ; + SPACING 3.00 BY 3.00 ; +END genVIA3_HV + + +SPACING + SAMENET VIAP VIAP 3.00 ; + SAMENET VIA1 VIA1 3.00 ; + SAMENET VIA2 VIA2 3.00 ; + SAMENET VIAP VIA1 3.00 STACK ; + SAMENET VIA1 VIA2 3.00 STACK ; + SAMENET VIA2 VIA3 3.00 STACK ; + SAMENET VIA3 VIA4 3.00 STACK ; + SAMENET VIA4 VIA5 3.00 STACK ; + SAMENET POLY POLY 3.00 ; + SAMENET ALU1 ALU1 3.00 STACK ; + SAMENET ALU2 ALU2 3.00 STACK ; + SAMENET ALU3 ALU3 3.00 STACK ; + SAMENET ALU4 ALU4 3.00 STACK ; + SAMENET ALU5 ALU5 3.00 STACK ; + SAMENET ALU6 ALU6 3.00 ; +END SPACING + + +SITE core + SYMMETRY y ; + CLASS CORE ; + SIZE 5.00 BY 50.00 ; +END core + + +SITE pad + SYMMETRY y ; + CLASS PAD ; + SIZE 1.00 BY 500.00 ; +END pad + + +SITE corner + SYMMETRY y r90 ; + CLASS PAD ; + SIZE 500.00 BY 500.00 ; +END corner + + +END LIBRARY diff --git a/crlcore/src/ccore/openaccess/test/sxlib2lef/sxlib.lef.bak b/crlcore/src/ccore/openaccess/test/sxlib2lef/sxlib.lef.bak new file mode 100644 index 00000000..26955877 --- /dev/null +++ b/crlcore/src/ccore/openaccess/test/sxlib2lef/sxlib.lef.bak @@ -0,0 +1,8417 @@ +# +# $Id: cmos.lef,v 1.6 2005/03/01 14:59:15 jpc Exp $ +# +# /------------------------------------------------------------------\ +# | | +# | A l l i a n c e C A D S y s t e m | +# | S i l i c o n E n s e m b l e / A l l i a n c e | +# | | +# | Author : Jean-Paul CHAPUT | +# | E-mail : alliance-users@asim.lip6.fr | +# | ================================================================ | +# | LEF : "./cmos_12.lef" | +# | **************************************************************** | +# | U p d a t e s | +# | | +# \------------------------------------------------------------------/ +# + + +VERSION 5.2 ; +NAMESCASESENSITIVE ON ; +BUSBITCHARS "()" ; +DIVIDERCHAR "." ; + +#NOWIREEXTENSIONATPIN ON ; + + +#UNITS +# DATABASE MICRONS 100 ; +#END UNITS + + +LAYER POLY + TYPE MASTERSLICE ; +END POLY + + +LAYER VIAP + TYPE CUT ; +END VIAP + + +LAYER ALU1 + TYPE ROUTING ; + WIDTH 2.00 ; + SPACING 3.00 ; + PITCH 5.00 ; + DIRECTION VERTICAL ; + CAPACITANCE CPERSQDIST 0.000032 ; + RESISTANCE RPERSQ 0.100000 ; +END ALU1 + + +LAYER VIA1 + TYPE CUT ; +END VIA1 + + +LAYER ALU2 + TYPE ROUTING ; + WIDTH 2.00 ; + SPACING 3.00 ; + PITCH 5.00 ; + DIRECTION HORIZONTAL ; + CAPACITANCE CPERSQDIST 0.000032 ; + RESISTANCE RPERSQ 0.100000 ; +END ALU2 + + +LAYER VIA2 + TYPE CUT ; +END VIA2 + + +LAYER ALU3 + TYPE ROUTING ; + WIDTH 2.00 ; + SPACING 3.00 ; + PITCH 5.00 ; + DIRECTION VERTICAL ; + CAPACITANCE CPERSQDIST 0.000032 ; + RESISTANCE RPERSQ 0.100000 ; +END ALU3 + + +LAYER VIA3 + TYPE CUT ; +END VIA3 + + +LAYER ALU4 + TYPE ROUTING ; + WIDTH 2.00 ; + SPACING 3.00 ; + PITCH 5.00 ; + DIRECTION HORIZONTAL ; + CAPACITANCE CPERSQDIST 0.000032 ; + RESISTANCE RPERSQ 0.100000 ; +END ALU4 + + +LAYER VIA4 + TYPE CUT ; +END VIA4 + + +LAYER ALU5 + TYPE ROUTING ; + WIDTH 2.00 ; + SPACING 3.00 ; + PITCH 5.00 ; + DIRECTION VERTICAL ; + CAPACITANCE CPERSQDIST 0.000032 ; + RESISTANCE RPERSQ 0.100000 ; +END ALU5 + + +LAYER VIA5 + TYPE CUT ; +END VIA5 + + +LAYER ALU6 + TYPE ROUTING ; + WIDTH 2.00 ; + SPACING 3.00 ; + PITCH 5.00 ; + DIRECTION HORIZONTAL ; + CAPACITANCE CPERSQDIST 0.000032 ; + RESISTANCE RPERSQ 0.100000 ; +END ALU6 + + +#VIA CONT_POLY DEFAULT +# LAYER POLY ; +# RECT -1.50 -1.50 1.50 1.50 ; +# LAYER VIAP ; +# RECT -0.50 -0.50 0.50 0.50 ; +# LAYER ALU1 ; +# RECT -1.00 -1.00 1.00 1.00 ; +#END CONT_POLY + + +VIA CONT_VIA DEFAULT + LAYER ALU1 ; + RECT -1.00 -1.00 1.00 1.00 ; + LAYER VIA1 ; + RECT -0.50 -0.50 0.50 0.50 ; + LAYER ALU2 ; + RECT -1.00 -1.00 1.00 1.00 ; +END CONT_VIA + + +VIA CONT_VIA2 DEFAULT + LAYER ALU3 ; + RECT -1.00 -1.00 1.00 1.00 ; + LAYER VIA2 ; + RECT -0.50 -0.50 0.50 0.50 ; + LAYER ALU2 ; + RECT -1.00 -1.00 1.00 1.00 ; +END CONT_VIA2 + + +VIA CONT_VIA3 DEFAULT + LAYER ALU4 ; + RECT -1.00 -1.00 1.00 1.00 ; + LAYER VIA3 ; + RECT -0.50 -0.50 0.50 0.50 ; + LAYER ALU3 ; + RECT -1.00 -1.00 1.00 1.00 ; +END CONT_VIA3 + + +VIA CONT_VIA4 DEFAULT + LAYER ALU5 ; + RECT -1.00 -1.00 1.00 1.00 ; + LAYER VIA4 ; + RECT -0.50 -0.50 0.50 0.50 ; + LAYER ALU4 ; + RECT -1.00 -1.00 1.00 1.00 ; +END CONT_VIA4 + + +VIA CONT_VIA5 DEFAULT + LAYER ALU6 ; + RECT -1.00 -1.00 1.00 1.00 ; + LAYER VIA5 ; + RECT -0.50 -0.50 0.50 0.50 ; + LAYER ALU5 ; + RECT -1.00 -1.00 1.00 1.00 ; +END CONT_VIA5 + + +VIARULE TURN_ALU1 GENERATE + LAYER ALU1 ; + DIRECTION vertical ; + + LAYER ALU1 ; + DIRECTION horizontal ; +END TURN_ALU1 + + +VIARULE TURN_ALU2 GENERATE + LAYER ALU2 ; + DIRECTION vertical ; + + LAYER ALU2 ; + DIRECTION horizontal ; +END TURN_ALU2 + + +VIARULE TURN_ALU3 GENERATE + LAYER ALU3 ; + DIRECTION vertical ; + + LAYER ALU3 ; + DIRECTION horizontal ; +END TURN_ALU3 + + +VIARULE TURN_ALU4 GENERATE + LAYER ALU4 ; + DIRECTION vertical ; + + LAYER ALU4 ; + DIRECTION horizontal ; +END TURN_ALU4 + + +VIARULE TURN_ALU5 GENERATE + LAYER ALU5 ; + DIRECTION vertical ; + + LAYER ALU5 ; + DIRECTION horizontal ; +END TURN_ALU5 + + +VIARULE TURN_ALU6 GENERATE + LAYER ALU6 ; + DIRECTION vertical ; + + LAYER ALU6 ; + DIRECTION horizontal ; +END TURN_ALU6 + + +#VIARULE VIA1_HV +# LAYER ALU1 ; +# DIRECTION VERTICAL ; +# OVERHANG 0.50 ; +# METALOVERHANG 0.50 ; +# +# LAYER ALU2 ; +# DIRECTION HORIZONTAL ; +# OVERHANG 0.50 ; +# METALOVERHANG 0.50 ; +# +# VIA CONT_VIA ; +#END VIA1_HV +# +# +#VIARULE VIA2_VH +# LAYER ALU2 ; +# DIRECTION HORIZONTAL ; +# OVERHANG 0.50 ; +# METALOVERHANG 0.50 ; +# +# LAYER ALU3 ; +# DIRECTION VERTICAL ; +# OVERHANG 0.50 ; +# METALOVERHANG 0.50 ; +# +# VIA CONT_VIA2 ; +#END VIA2_VH +# +# +#VIARULE VIA3_VH +# LAYER ALU3 ; +# DIRECTION HORIZONTAL ; +# OVERHANG 0.50 ; +# METALOVERHANG 0.50 ; +# +# LAYER ALU4 ; +# DIRECTION VERTICAL ; +# OVERHANG 0.50 ; +# METALOVERHANG 0.50 ; +# +# VIA CONT_VIA3 ; +#END VIA3_VH + + +VIARULE genVIA1_HV GENERATE + LAYER ALU1 ; + DIRECTION VERTICAL ; + OVERHANG 0.50 ; + METALOVERHANG 0.50 ; + + LAYER ALU2 ; + DIRECTION HORIZONTAL ; + OVERHANG 0.50 ; + METALOVERHANG 0.50 ; + + LAYER VIA1 ; + RECT -0.50 -0.50 0.50 0.50 ; + SPACING 3.00 BY 3.00 ; +END genVIA1_HV + + +VIARULE genVIA1_VH GENERATE + LAYER ALU1 ; + DIRECTION HORIZONTAL ; + OVERHANG 0.50 ; + METALOVERHANG 0.50 ; + + LAYER ALU2 ; + DIRECTION VERTICAL ; + OVERHANG 0.50 ; + METALOVERHANG 0.50 ; + + LAYER VIA1 ; + RECT -0.50 -0.50 0.50 0.50 ; + SPACING 3.00 BY 3.00 ; +END genVIA1_VH + + +VIARULE genVIA2_VH GENERATE + LAYER ALU2 ; + DIRECTION HORIZONTAL ; + OVERHANG 0.50 ; + METALOVERHANG 0.50 ; + + LAYER ALU3 ; + DIRECTION VERTICAL ; + OVERHANG 0.50 ; + METALOVERHANG 0.50 ; + + LAYER VIA2 ; + RECT -0.50 -0.50 0.50 0.50 ; + SPACING 3.00 BY 3.00 ; +END genVIA2_VH + + +VIARULE genVIA2_HV GENERATE + LAYER ALU2 ; + DIRECTION VERTICAL ; + OVERHANG 0.50 ; + METALOVERHANG 0.50 ; + + LAYER ALU3 ; + DIRECTION HORIZONTAL ; + OVERHANG 0.50 ; + METALOVERHANG 0.50 ; + + LAYER VIA2 ; + RECT -0.50 -0.50 0.50 0.50 ; + SPACING 3.00 BY 3.00 ; +END genVIA2_HV + + +VIARULE genVIA3_VH GENERATE + LAYER ALU3 ; + DIRECTION HORIZONTAL ; + OVERHANG 0.50 ; + METALOVERHANG 0.50 ; + + LAYER ALU4 ; + DIRECTION VERTICAL ; + OVERHANG 0.50 ; + METALOVERHANG 0.50 ; + + LAYER VIA3 ; + RECT -0.50 -0.50 0.50 0.50 ; + SPACING 3.00 BY 3.00 ; +END genVIA3_VH + + +VIARULE genVIA3_HV GENERATE + LAYER ALU3 ; + DIRECTION VERTICAL ; + OVERHANG 0.50 ; + METALOVERHANG 0.50 ; + + LAYER ALU4 ; + DIRECTION HORIZONTAL ; + OVERHANG 0.50 ; + METALOVERHANG 0.50 ; + + LAYER VIA3 ; + RECT -0.50 -0.50 0.50 0.50 ; + SPACING 3.00 BY 3.00 ; +END genVIA3_HV + + +SPACING + SAMENET VIAP VIAP 3.00 ; + SAMENET VIA1 VIA1 3.00 ; + SAMENET VIA2 VIA2 3.00 ; + SAMENET VIAP VIA1 3.00 STACK ; + SAMENET VIA1 VIA2 3.00 STACK ; + SAMENET VIA2 VIA3 3.00 STACK ; + SAMENET VIA3 VIA4 3.00 STACK ; + SAMENET VIA4 VIA5 3.00 STACK ; + SAMENET POLY POLY 3.00 ; + SAMENET ALU1 ALU1 3.00 STACK ; + SAMENET ALU2 ALU2 3.00 STACK ; + SAMENET ALU3 ALU3 3.00 STACK ; + SAMENET ALU4 ALU4 3.00 STACK ; + SAMENET ALU5 ALU5 3.00 STACK ; + SAMENET ALU6 ALU6 3.00 ; +END SPACING + + +SITE core + SYMMETRY y ; + CLASS CORE ; + SIZE 5.00 BY 50.00 ; +END core + + +SITE pad + SYMMETRY y ; + CLASS PAD ; + SIZE 1.00 BY 500.00 ; +END pad + + +SITE corner + SYMMETRY y r90 ; + CLASS PAD ; + SIZE 500.00 BY 500.00 ; +END corner + + +MACRO a2_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + END +END a2_x2 + +MACRO a2_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i1 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END a2_x4 + +MACRO a3_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i0 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END a3_x2 + +MACRO a3_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END a3_x4 + +MACRO a4_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END q + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i3 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i2 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END a4_x2 + +MACRO a4_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END q + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i3 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i2 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END a4_x4 + +MACRO an12_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + END +END an12_x1 + +MACRO an12_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END an12_x4 + +MACRO ao22_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END q + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END ao22_x2 + +MACRO ao22_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + END + END i0 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END ao22_x4 + +MACRO ao2o22_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 45.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i3 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 42.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 42.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 43.50 41.00 ; + END +END ao2o22_x2 + +MACRO ao2o22_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i3 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END ao2o22_x4 + +MACRO buf_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 20.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END q + PIN i + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 17.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 17.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 18.50 41.00 ; + END +END buf_x2 + +MACRO buf_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END q + PIN i + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + END +END buf_x4 + +MACRO buf_x8 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END q + PIN i + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END buf_x8 + +MACRO fulladder_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 100.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN cout + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + LAYER ALU1 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END cout + PIN sout + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END sout + PIN cin1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END cin1 + PIN a2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END a2 + PIN b2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END b2 + PIN a3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 59.00 14.00 61.00 16.00 ; + END + END a3 + PIN b3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 64.00 29.00 66.00 31.00 ; + RECT 64.00 24.00 66.00 26.00 ; + RECT 64.00 19.00 66.00 21.00 ; + RECT 64.00 14.00 66.00 16.00 ; + END + END b3 + PIN cin2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 69.00 14.00 71.00 16.00 ; + END + END cin2 + PIN cin3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 84.00 29.00 86.00 31.00 ; + RECT 84.00 24.00 86.00 26.00 ; + RECT 84.00 19.00 86.00 21.00 ; + RECT 84.00 14.00 86.00 16.00 ; + END + END cin3 + PIN a1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END a1 + PIN b1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END b1 + PIN a4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 89.00 34.00 91.00 36.00 ; + RECT 89.00 29.00 91.00 31.00 ; + RECT 89.00 24.00 91.00 26.00 ; + RECT 89.00 19.00 91.00 21.00 ; + RECT 89.00 14.00 91.00 16.00 ; + END + END a4 + PIN b4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 94.00 34.00 96.00 36.00 ; + RECT 94.00 29.00 96.00 31.00 ; + RECT 94.00 24.00 96.00 26.00 ; + RECT 94.00 19.00 96.00 21.00 ; + RECT 94.00 14.00 96.00 16.00 ; + END + END b4 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 97.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 97.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 98.50 41.00 ; + END +END fulladder_x2 + +MACRO fulladder_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 105.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN sout + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + RECT 54.00 9.00 56.00 11.00 ; + END + END sout + PIN cout + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 44.00 9.00 46.00 11.00 ; + END + END cout + PIN a1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END a1 + PIN b1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END b1 + PIN cin1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END cin1 + PIN a2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END a2 + PIN b2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END b2 + PIN b4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 99.00 34.00 101.00 36.00 ; + RECT 99.00 29.00 101.00 31.00 ; + RECT 99.00 24.00 101.00 26.00 ; + RECT 99.00 19.00 101.00 21.00 ; + RECT 99.00 14.00 101.00 16.00 ; + END + END b4 + PIN a4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 94.00 34.00 96.00 36.00 ; + RECT 94.00 29.00 96.00 31.00 ; + RECT 94.00 24.00 96.00 26.00 ; + RECT 94.00 19.00 96.00 21.00 ; + RECT 94.00 14.00 96.00 16.00 ; + END + END a4 + PIN cin3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 89.00 29.00 91.00 31.00 ; + RECT 89.00 24.00 91.00 26.00 ; + RECT 89.00 19.00 91.00 21.00 ; + RECT 89.00 14.00 91.00 16.00 ; + END + END cin3 + PIN b3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 69.00 14.00 71.00 16.00 ; + END + END b3 + PIN cin2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 74.00 29.00 76.00 31.00 ; + RECT 74.00 24.00 76.00 26.00 ; + RECT 74.00 19.00 76.00 21.00 ; + RECT 74.00 14.00 76.00 16.00 ; + END + END cin2 + PIN a3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 64.00 29.00 66.00 31.00 ; + RECT 64.00 24.00 66.00 26.00 ; + RECT 64.00 19.00 66.00 21.00 ; + END + END a3 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 102.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 102.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 103.50 41.00 ; + END +END fulladder_x4 + +MACRO halfadder_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 80.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN sout + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 74.00 39.00 76.00 41.00 ; + RECT 74.00 34.00 76.00 36.00 ; + RECT 74.00 29.00 76.00 31.00 ; + RECT 74.00 24.00 76.00 26.00 ; + RECT 74.00 19.00 76.00 21.00 ; + RECT 74.00 14.00 76.00 16.00 ; + RECT 74.00 9.00 76.00 11.00 ; + END + END sout + PIN cout + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END cout + PIN b + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 34.00 9.00 36.00 11.00 ; + END + END b + PIN a + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END a + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 77.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 77.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 78.50 41.00 ; + END +END halfadder_x2 + +MACRO halfadder_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 90.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN sout + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 79.00 39.00 81.00 41.00 ; + RECT 79.00 34.00 81.00 36.00 ; + RECT 79.00 29.00 81.00 31.00 ; + RECT 79.00 24.00 81.00 26.00 ; + RECT 79.00 19.00 81.00 21.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 79.00 9.00 81.00 11.00 ; + END + END sout + PIN cout + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END cout + PIN b + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END b + PIN a + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END a + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 87.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 87.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 88.50 41.00 ; + END +END halfadder_x4 + +MACRO inv_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 15.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END nq + PIN i + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 12.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 12.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 13.50 41.00 ; + END +END inv_x1 + +MACRO inv_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 15.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END nq + PIN i + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 12.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 12.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 13.50 41.00 ; + END +END inv_x2 + +MACRO inv_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 20.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END nq + PIN i + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 17.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 17.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 18.50 41.00 ; + END +END inv_x4 + +MACRO inv_x8 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END nq + PIN i + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END inv_x8 + +MACRO mx2_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 45.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END q + PIN cmd + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END cmd + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END i1 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 42.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 42.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 43.50 41.00 ; + END +END mx2_x2 + +MACRO mx2_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END q + PIN cmd + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END cmd + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END i1 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END mx2_x4 + +MACRO mx3_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 65.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 59.00 9.00 61.00 11.00 ; + LAYER ALU1 ; + RECT 59.00 39.00 61.00 41.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + END + END q + PIN cmd1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END cmd1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 24.00 16.00 26.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 24.00 26.00 26.00 ; + END + END i1 + PIN cmd0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END cmd0 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 19.00 41.00 21.00 ; + LAYER ALU1 ; + RECT 44.00 24.00 46.00 26.00 ; + LAYER ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 62.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 62.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 63.50 41.00 ; + END +END mx3_x2 + +MACRO mx3_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 70.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 64.00 19.00 66.00 21.00 ; + LAYER ALU1 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 59.00 9.00 61.00 11.00 ; + LAYER ALU1 ; + RECT 59.00 39.00 61.00 41.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + END + END q + PIN cmd0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END cmd0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 24.00 26.00 26.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 24.00 16.00 26.00 ; + END + END i2 + PIN cmd1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END cmd1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 19.00 41.00 21.00 ; + LAYER ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + LAYER ALU1 ; + RECT 44.00 24.00 46.00 26.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 67.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 67.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 68.50 41.00 ; + END +END mx3_x4 + +MACRO na2_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 20.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END nq + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 17.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 17.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 18.50 41.00 ; + END +END na2_x1 + +MACRO na2_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END nq + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END na2_x4 + +MACRO na3_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + END +END na3_x1 + +MACRO na3_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END nq + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END na3_x4 + +MACRO na4_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i3 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END na4_x1 + +MACRO na4_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nq + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 34.00 9.00 36.00 11.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END i3 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END na4_x4 + +MACRO nao22_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END nao22_x1 + +MACRO nao22_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END nq + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 14.00 26.00 16.00 ; + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END nao22_x4 + +MACRO nao2o22_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END i1 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END nao2o22_x1 + +MACRO nao2o22_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 55.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 44.00 39.00 46.00 41.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 44.00 9.00 46.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END i1 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 52.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 52.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 53.50 41.00 ; + END +END nao2o22_x4 + +MACRO nmx2_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + LAYER ALU1 ; + RECT 19.00 9.00 21.00 11.00 ; + LAYER ALU1 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END nq + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i0 + PIN cmd + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END cmd + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END nmx2_x1 + +MACRO nmx2_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 60.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END nq + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i0 + PIN cmd + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END cmd + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 57.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 57.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 58.50 41.00 ; + END +END nmx2_x4 + +MACRO nmx3_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 60.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + RECT 54.00 9.00 56.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + LAYER ALU1 ; + RECT 44.00 24.00 46.00 26.00 ; + LAYER ALU1 ; + RECT 39.00 19.00 41.00 21.00 ; + END + END i0 + PIN cmd1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END cmd1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 24.00 16.00 26.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 24.00 26.00 26.00 ; + END + END i1 + PIN cmd0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END cmd0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 57.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 57.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 58.50 41.00 ; + END +END nmx3_x1 + +MACRO nmx3_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 75.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 59.00 39.00 61.00 41.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 59.00 14.00 61.00 16.00 ; + END + END nq + PIN cmd0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END cmd0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 24.00 26.00 26.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 24.00 16.00 26.00 ; + END + END i2 + PIN cmd1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END cmd1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 19.00 41.00 21.00 ; + LAYER ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + LAYER ALU1 ; + RECT 44.00 24.00 46.00 26.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 72.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 72.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 73.50 41.00 ; + END +END nmx3_x4 + +MACRO no2_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 20.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END nq + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 17.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 17.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 18.50 41.00 ; + END +END no2_x1 + +MACRO no2_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i1 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END no2_x4 + +MACRO no3_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END nq + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + END +END no3_x1 + +MACRO no3_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END nq + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END no3_x4 + +MACRO no4_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END nq + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i3 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END no4_x1 + +MACRO no4_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END nq + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i3 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END no4_x4 + +MACRO noa22_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END noa22_x1 + +MACRO noa22_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END noa22_x4 + +MACRO noa2a22_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nq + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i3 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END noa2a22_x1 + +MACRO noa2a22_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 55.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 44.00 39.00 46.00 41.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 44.00 9.00 46.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 52.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 52.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 53.50 41.00 ; + END +END noa2a22_x4 + +MACRO noa2a2a23_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END nq + PIN i5 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i5 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i3 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i1 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i4 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END noa2a2a23_x1 + +MACRO noa2a2a23_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 65.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + END + END nq + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i0 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i4 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i3 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i5 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 62.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 62.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 63.50 41.00 ; + END +END noa2a2a23_x4 + +MACRO noa2a2a2a24_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 70.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 59.00 14.00 61.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END i3 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i4 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i5 + PIN i6 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i6 + PIN i7 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i7 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 67.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 67.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 68.50 41.00 ; + END +END noa2a2a2a24_x1 + +MACRO noa2a2a2a24_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 85.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 69.00 39.00 71.00 41.00 ; + RECT 69.00 34.00 71.00 36.00 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 69.00 14.00 71.00 16.00 ; + END + END nq + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END i3 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i4 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i5 + PIN i6 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i6 + PIN i7 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i7 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 64.00 34.00 66.00 36.00 ; + RECT 64.00 29.00 66.00 31.00 ; + RECT 64.00 24.00 66.00 26.00 ; + RECT 64.00 19.00 66.00 21.00 ; + RECT 64.00 14.00 66.00 16.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 82.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 82.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 83.50 41.00 ; + END +END noa2a2a2a24_x4 + +MACRO noa2ao222_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + LAYER ALU1 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nq + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END i4 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END noa2ao222_x1 + +MACRO noa2ao222_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 60.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END i4 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i3 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 57.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 57.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 58.50 41.00 ; + END +END noa2ao222_x4 + +MACRO noa3ao322_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 45.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + LAYER ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END nq + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i2 + PIN i6 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END i6 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i3 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END i4 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i5 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 42.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 42.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 43.50 41.00 ; + END +END noa3ao322_x1 + +MACRO noa3ao322_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 65.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i0 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + END + END i3 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 59.00 14.00 61.00 16.00 ; + END + END i5 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + END + END i4 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END i2 + PIN i6 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + END + END i6 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i1 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 62.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 62.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 63.50 41.00 ; + END +END noa3ao322_x4 + +MACRO nts_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nq + PIN cmd + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END cmd + PIN i + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END nts_x1 + +MACRO nts_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nq + PIN i + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i + PIN cmd + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END cmd + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END nts_x2 + +MACRO nxr2_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 45.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 34.00 9.00 36.00 11.00 ; + END + END i1 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 42.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 42.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 43.50 41.00 ; + END +END nxr2_x1 + +MACRO nxr2_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 60.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END i1 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 57.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 57.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 58.50 41.00 ; + END +END nxr2_x4 + +MACRO o2_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + END +END o2_x2 + +MACRO o2_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END o2_x4 + +MACRO o3_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END q + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END o3_x2 + +MACRO o3_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END o3_x4 + +MACRO o4_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i3 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END o4_x2 + +MACRO o4_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + LAYER ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 34.00 9.00 36.00 11.00 ; + END + END q + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + END + END i3 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END o4_x4 + +MACRO oa22_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END oa22_x2 + +MACRO oa22_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END q + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END oa22_x4 + +MACRO oa2a22_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 45.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END q + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 42.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 42.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 43.50 41.00 ; + END +END oa2a22_x2 + +MACRO oa2a22_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END q + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END oa2a22_x4 + +MACRO oa2a2a23_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 60.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 54.00 39.00 56.00 41.00 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + RECT 54.00 9.00 56.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i1 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i4 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i5 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 57.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 57.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 58.50 41.00 ; + END +END oa2a2a23_x2 + +MACRO oa2a2a23_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 65.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 54.00 39.00 56.00 41.00 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + RECT 54.00 9.00 56.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + END + END i0 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i4 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i3 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i5 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 62.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 62.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 63.50 41.00 ; + END +END oa2a2a23_x4 + +MACRO oa2a2a2a24_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 75.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 69.00 39.00 71.00 41.00 ; + RECT 69.00 34.00 71.00 36.00 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 69.00 9.00 71.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 64.00 34.00 66.00 36.00 ; + RECT 64.00 29.00 66.00 31.00 ; + RECT 64.00 24.00 66.00 26.00 ; + RECT 64.00 19.00 66.00 21.00 ; + RECT 64.00 14.00 66.00 16.00 ; + END + END i0 + PIN i7 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i7 + PIN i6 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i6 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i5 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i4 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 72.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 72.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 73.50 41.00 ; + END +END oa2a2a2a24_x2 + +MACRO oa2a2a2a24_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 80.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 69.00 39.00 71.00 41.00 ; + RECT 69.00 34.00 71.00 36.00 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 69.00 9.00 71.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 64.00 34.00 66.00 36.00 ; + RECT 64.00 29.00 66.00 31.00 ; + RECT 64.00 24.00 66.00 26.00 ; + RECT 64.00 19.00 66.00 21.00 ; + RECT 64.00 14.00 66.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + END + END i1 + PIN i7 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i7 + PIN i6 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i6 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i5 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i4 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 77.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 77.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 78.50 41.00 ; + END +END oa2a2a2a24_x4 + +MACRO oa2ao222_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 44.00 39.00 46.00 41.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 44.00 9.00 46.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END i4 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i3 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END oa2ao222_x2 + +MACRO oa2ao222_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 55.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 44.00 39.00 46.00 41.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 44.00 9.00 46.00 11.00 ; + END + END q + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END i4 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 52.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 52.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 53.50 41.00 ; + END +END oa2ao222_x4 + +MACRO oa3ao322_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 55.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + END + END i4 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + END + END i5 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i3 + PIN i6 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + END + END i6 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 52.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 52.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 53.50 41.00 ; + END +END oa3ao322_x2 + +MACRO oa3ao322_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 60.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + END + END i2 + PIN i6 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END i6 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + END + END i4 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + END + END i5 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i0 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + END + END i3 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 57.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 57.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 58.50 41.00 ; + END +END oa3ao322_x4 + +MACRO on12_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + END +END on12_x1 + +MACRO on12_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END i1 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END on12_x4 + +MACRO one_x0 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 15.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END q + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 12.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 12.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 13.50 41.00 ; + END +END one_x0 + +MACRO powmid_x0 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + LAYER ALU3 ; + WIDTH 12.00 ; + PATH 10.00 6.00 10.00 44.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + LAYER ALU3 ; + WIDTH 12.00 ; + PATH 25.00 6.00 25.00 44.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + LAYER ALU2 ; + RECT 4.00 49.00 16.00 51.00 ; + RECT 19.00 -1.00 31.00 1.00 ; + END +END powmid_x0 + +MACRO rowend_x0 + CLASS CORE FEEDTHRU ; + ORIGIN 0.00 0.00 ; + SIZE 5.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 2.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 2.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 3.50 41.00 ; + END +END rowend_x0 + +MACRO sff1_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 90.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 79.00 39.00 81.00 41.00 ; + RECT 79.00 34.00 81.00 36.00 ; + RECT 79.00 29.00 81.00 31.00 ; + RECT 79.00 24.00 81.00 26.00 ; + RECT 79.00 19.00 81.00 21.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 79.00 9.00 81.00 11.00 ; + END + END q + PIN i + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + LAYER ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + LAYER ALU1 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END i + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 87.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 87.00 3.00 ; + END + END vss + PIN ck + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END ck + OBS + LAYER ALU1 ; + RECT 1.50 9.00 88.50 41.00 ; + END +END sff1_x4 + +MACRO sff2_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 120.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 109.00 39.00 111.00 41.00 ; + RECT 109.00 34.00 111.00 36.00 ; + RECT 109.00 29.00 111.00 31.00 ; + RECT 109.00 24.00 111.00 26.00 ; + RECT 109.00 19.00 111.00 21.00 ; + RECT 109.00 14.00 111.00 16.00 ; + RECT 109.00 9.00 111.00 11.00 ; + END + END q + PIN cmd + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + END + END cmd + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 117.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 117.00 3.00 ; + END + END vss + PIN ck + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER ALU1 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 44.00 9.00 46.00 11.00 ; + END + END ck + OBS + LAYER ALU1 ; + RECT 1.50 9.00 118.50 41.00 ; + END +END sff2_x4 + +MACRO sff3_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 140.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 129.00 39.00 131.00 41.00 ; + RECT 129.00 34.00 131.00 36.00 ; + RECT 129.00 29.00 131.00 31.00 ; + RECT 129.00 24.00 131.00 26.00 ; + RECT 129.00 19.00 131.00 21.00 ; + RECT 129.00 14.00 131.00 16.00 ; + RECT 129.00 9.00 131.00 11.00 ; + END + END q + PIN cmd1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END cmd1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 24.00 16.00 26.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 24.00 26.00 26.00 ; + END + END i1 + PIN cmd0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END cmd0 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 19.00 41.00 21.00 ; + LAYER ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + LAYER ALU1 ; + RECT 44.00 24.00 46.00 26.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 137.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 137.00 3.00 ; + END + END vss + PIN ck + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER ALU1 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 59.00 9.00 61.00 11.00 ; + END + END ck + OBS + LAYER ALU1 ; + RECT 1.50 9.00 138.50 41.00 ; + END +END sff3_x4 + +MACRO tie_x0 + CLASS CORE FEEDTHRU ; + ORIGIN 0.00 0.00 ; + SIZE 10.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 7.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 7.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 8.50 41.00 ; + END +END tie_x0 + +MACRO ts_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END q + PIN cmd + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END cmd + PIN i + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END ts_x4 + +MACRO ts_x8 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 65.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END q + PIN cmd + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END cmd + PIN i + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + END + END i + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 62.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 62.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 63.50 41.00 ; + END +END ts_x8 + +MACRO xr2_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 45.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 9.00 21.00 11.00 ; + LAYER ALU1 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 34.00 9.00 36.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 42.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 42.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 43.50 41.00 ; + END +END xr2_x1 + +MACRO xr2_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 60.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 57.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 57.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 58.50 41.00 ; + END +END xr2_x4 + +MACRO zero_x0 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 15.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END nq + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 12.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 12.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 13.50 41.00 ; + END +END zero_x0 + +END LIBRARY