diff --git a/.gitignore b/.gitignore index 96e462f7..9a5dba53 100644 --- a/.gitignore +++ b/.gitignore @@ -2,10 +2,17 @@ *.swp *.pyc *.log +*.bak man/ rtf/ html/ latex/ -crlcore/doc/UsersGuide/UsersGuide.tex -crlcore/doc/UsersGuide/UsersGuide.html +documentation/UsersGuide/UsersGuide-raw.tex +documentation/UsersGuide/UsersGuide.tex +documentation/UsersGuide/UsersGuide.aux +documentation/UsersGuide/UsersGuide.log +documentation/UsersGuide/UsersGuide.pdf +documentation/UsersGuide/UsersGuide.out +documentation/UsersGuide/UsersGuide.toc +documentation/UsersGuide/UsersGuide.html diff --git a/bootstrap/Makefile.package b/bootstrap/Makefile.package index c0b82e82..7f02e6ef 100644 --- a/bootstrap/Makefile.package +++ b/bootstrap/Makefile.package @@ -3,16 +3,14 @@ # Mimicking the behavior of a top-level autotool generated Makefile. tools = bootstrap vlsisapd hurricane crlcore nimbus metis mauka knik katabatic kite \ - equinox solstice cumulus stratus1 unicorn + equinox solstice cumulus stratus1 unicorn documentation prefix = /usr DESTDIR = BUILD_DESTDIR = $(shell pwd)/install.dir BOOTSTRAP_TOP = $(prefix) - VLSISAPD_TOP = $(prefix) CORIOLIS_TOP = $(prefix) environment = BOOTSTRAP_TOP=$(BOOTSTRAP_TOP); export BOOTSTRAP_TOP; \ - VLSISAPD_TOP=$(VLSISAPD_TOP); export VLSISAPD_TOP; \ CORIOLIS_TOP=$(CORIOLIS_TOP); export CORIOLIS_TOP .PHONY: build install FORCE diff --git a/bootstrap/build.conf b/bootstrap/build.conf index 822e6f9a..576b817e 100644 --- a/bootstrap/build.conf +++ b/bootstrap/build.conf @@ -23,6 +23,7 @@ projects = [ { 'name' : "coriolis" #, "ispd" , "cumulus" , "stratus1" + , "documentation" ] , 'repository': 'ssh://asim-t/users/largo2/git/coriolis.git' } diff --git a/bootstrap/svn2git/authors.txt b/bootstrap/svn2git/authors.txt index 6c7adddd..d1d0ec5e 100644 --- a/bootstrap/svn2git/authors.txt +++ b/bootstrap/svn2git/authors.txt @@ -18,6 +18,7 @@ karim = Karim Dioury labiadh = Forgotten Author (labiadh) liyao = Yao Li ludo = Ludovic Jacomme +mariem = Marie-Minerve Louerat masson = Christian Masson mitri = Forgotten Author (mitri) noury = Ludovic Noury @@ -28,4 +29,5 @@ xtof = Christophe Alexandre youssef = Stephanie Youssef jpc = Jean-Paul Chaput ramy = Ramy Iskander -roselyne = Roselyne Chotin +roselyne = Roselyne Chotin +(no author) = Anonymous Author diff --git a/bootstrap/svn2git/cvs2git-alliance.options b/bootstrap/svn2git/cvs2git-alliance.options new file mode 100644 index 00000000..cdfdfd3f --- /dev/null +++ b/bootstrap/svn2git/cvs2git-alliance.options @@ -0,0 +1,620 @@ +# (Be in -*- mode: python; coding: utf-8 -*- mode.) +# +# ==================================================================== +# Copyright (c) 2006-2009 CollabNet. All rights reserved. +# +# This software is licensed as described in the file COPYING, which +# you should have received as part of this distribution. The terms +# are also available at http://subversion.tigris.org/license-1.html. +# If newer versions of this license are posted there, you may use a +# newer version instead, at your option. +# +# This software consists of voluntary contributions made by many +# individuals. For exact contribution history, see the revision +# history and logs, available at http://cvs2svn.tigris.org/. +# ==================================================================== + +# ##################### +# ## PLEASE READ ME! ## +# ##################### +# +# This is a template for an options file that can be used to configure +# cvs2svn to convert to git rather than to Subversion. See +# www/cvs2git.html and www/cvs2svn.html for general information, and +# see the comments in this file for information about what options are +# available and how they can be set. +# +# The program that is run to convert from CVS to git is called +# cvs2git. Run it with the --options option, passing it this file +# like this: +# +# cvs2git --options=cvs2git-example.options +# +# The output of cvs2git is a blob file and a dump file that can be +# loaded into git using the "git fast-import" command. Please read +# www/cvs2git.html for more information. +# +# Many options do not have defaults, so it is easier to copy this file +# and modify what you need rather than creating a new options file +# from scratch. This file is in Python syntax, but you don't need to +# know Python to modify it. But if you *do* know Python, then you +# will be happy to know that you can use arbitary Python constructs to +# do fancy configuration tricks. +# +# But please be aware of the following: +# +# * In many places, leading whitespace is significant in Python (it is +# used instead of curly braces to group statements together). +# Therefore, if you don't know what you are doing, it is best to +# leave the whitespace as it is. +# +# * In normal strings, Python treats a backslash ("\") as an escape +# character. Therefore, if you want to specify a string that +# contains a backslash, you need either to escape the backslash with +# another backslash ("\\"), or use a "raw string", as in one if the +# following equivalent examples: +# +# cvs_executable = 'c:\\windows\\system32\\cvs.exe' +# cvs_executable = r'c:\windows\system32\cvs.exe' +# +# See http://docs.python.org/tutorial/introduction.html#strings for +# more information. +# +# Two identifiers will have been defined before this file is executed, +# and can be used freely within this file: +# +# ctx -- a Ctx object (see cvs2svn_lib/context.py), which holds +# many configuration options +# +# run_options -- an instance of the GitRunOptions class (see +# cvs2svn_lib/git_run_options.py), which holds some variables +# governing how cvs2git is run + + +# Import some modules that are used in setting the options: +import re + +from cvs2svn_lib import config +from cvs2svn_lib import changeset_database +from cvs2svn_lib.common import CVSTextDecoder +from cvs2svn_lib.log import Log +from cvs2svn_lib.project import Project +from cvs2svn_lib.git_revision_recorder import GitRevisionRecorder +from cvs2svn_lib.git_output_option import GitRevisionMarkWriter +from cvs2svn_lib.git_output_option import GitOutputOption +from cvs2svn_lib.revision_manager import NullRevisionRecorder +from cvs2svn_lib.revision_manager import NullRevisionExcluder +from cvs2svn_lib.fulltext_revision_recorder \ + import SimpleFulltextRevisionRecorderAdapter +from cvs2svn_lib.rcs_revision_manager import RCSRevisionReader +from cvs2svn_lib.cvs_revision_manager import CVSRevisionReader +from cvs2svn_lib.checkout_internal import InternalRevisionRecorder +from cvs2svn_lib.checkout_internal import InternalRevisionExcluder +from cvs2svn_lib.checkout_internal import InternalRevisionReader +from cvs2svn_lib.symbol_strategy import AllBranchRule +from cvs2svn_lib.symbol_strategy import AllTagRule +from cvs2svn_lib.symbol_strategy import BranchIfCommitsRule +from cvs2svn_lib.symbol_strategy import ExcludeRegexpStrategyRule +from cvs2svn_lib.symbol_strategy import ForceBranchRegexpStrategyRule +from cvs2svn_lib.symbol_strategy import ForceTagRegexpStrategyRule +from cvs2svn_lib.symbol_strategy import ExcludeTrivialImportBranchRule +from cvs2svn_lib.symbol_strategy import ExcludeVendorBranchRule +from cvs2svn_lib.symbol_strategy import HeuristicStrategyRule +from cvs2svn_lib.symbol_strategy import UnambiguousUsageRule +from cvs2svn_lib.symbol_strategy import HeuristicPreferredParentRule +from cvs2svn_lib.symbol_strategy import SymbolHintsFileRule +from cvs2svn_lib.symbol_transform import ReplaceSubstringsSymbolTransform +from cvs2svn_lib.symbol_transform import RegexpSymbolTransform +from cvs2svn_lib.symbol_transform import IgnoreSymbolTransform +from cvs2svn_lib.symbol_transform import NormalizePathsSymbolTransform +from cvs2svn_lib.property_setters import AutoPropsPropertySetter +from cvs2svn_lib.property_setters import CVSBinaryFileDefaultMimeTypeSetter +from cvs2svn_lib.property_setters import CVSBinaryFileEOLStyleSetter +from cvs2svn_lib.property_setters import DefaultEOLStyleSetter +from cvs2svn_lib.property_setters import EOLStyleFromMimeTypeSetter +from cvs2svn_lib.property_setters import ExecutablePropertySetter +from cvs2svn_lib.property_setters import KeywordsPropertySetter +from cvs2svn_lib.property_setters import MimeMapper +from cvs2svn_lib.property_setters import SVNBinaryFileKeywordsPropertySetter + +# To choose the level of logging output, uncomment one of the +# following lines: +#Log().log_level = Log.WARN +#Log().log_level = Log.QUIET +Log().log_level = Log.NORMAL +#Log().log_level = Log.VERBOSE +#Log().log_level = Log.DEBUG + + +# During CollectRevsPass, cvs2git records the contents of file +# revisions into a "blob" file in git-fast-import format. This option +# configures that process: +ctx.revision_recorder = SimpleFulltextRevisionRecorderAdapter( + # The following option specifies how the revision contents of the RCS + # files should be read. + # + # RCSRevisionReader uses RCS's "co" program to extract the revision + # contents of the RCS files during CollectRevsPass. The constructor + # argument specifies how to invoke the "co" executable. + # + # CVSRevisionReader uses the "cvs" program to extract the revision + # contents out of the RCS files during OutputPass. This option is + # considerably slower than RCSRevisionReader because "cvs" is + # considerably slower than "co". However, it works in some situations + # where RCSRevisionReader fails; see the HTML documentation of the + # "--use-cvs" option for details. The constructor argument specifies + # how to invoke the "co" executable. + # + # Uncomment one of the two following lines: + #RCSRevisionReader(co_executable=r'co'), + CVSRevisionReader(cvs_executable=r'cvs'), + + # The file in which to write the git-fast-import stream that + # contains the file revision contents: + GitRevisionRecorder('cvs2svn-tmp/git-blob.dat'), + ) + +# cvs2git does not need to keep track of what revisions will be +# excluded, so leave this option unchanged: +ctx.revision_excluder = NullRevisionExcluder() + +# cvs2git doesn't need a revision reader because OutputPass only +# refers to blobs that were output during CollectRevsPass, so leave +# this option set to None. +ctx.revision_reader = None + +# Change the following line to True if the conversion should only +# include the trunk of the repository (i.e., all branches and tags +# should be omitted from the conversion): +ctx.trunk_only = False + +# How to convert CVS author names, log messages, and filenames to +# Unicode. The first argument to CVSTextDecoder is a list of encoders +# that are tried in order in 'strict' mode until one of them succeeds. +# If none of those succeeds, then fallback_encoder (if it is +# specified) is used in lossy 'replace' mode. Setting a fallback +# encoder ensures that the encoder always succeeds, but it can cause +# information loss. +ctx.cvs_author_decoder = CVSTextDecoder( + [ + 'latin1', + 'utf8', + 'ascii', + ], + fallback_encoding='latin1' + ) +ctx.cvs_log_decoder = CVSTextDecoder( + [ + 'latin1', + 'utf8', + 'ascii', + ], + fallback_encoding='latin1' + ) +# You might want to be especially strict when converting filenames to +# Unicode (e.g., maybe not specify a fallback_encoding). +ctx.cvs_filename_decoder = CVSTextDecoder( + [ + 'latin1', + 'utf8', + 'ascii', + ], + fallback_encoding='latin1' + ) + +# Template for the commit message to be used for initial project +# commits. +ctx.initial_project_commit_message = ( + 'Standard project directories initialized by cvs2svn.' + ) + +# Template for the commit message to be used for post commits, in +# which modifications to a vendor branch are copied back to trunk. +# This message can use '%(revnum)d' to include the SVN revision number +# of the revision that included the change to the vendor branch +# (admittedly rather pointless in a cvs2git conversion). +ctx.post_commit_message = ( + 'This commit was generated by cvs2svn to track changes on a CVS ' + 'vendor branch.' + ) + +# Template for the commit message to be used for commits in which +# symbols are created. This message can use '%(symbol_type)s' to +# include the type of the symbol ('branch' or 'tag') or +# '%(symbol_name)s' to include the name of the symbol. +ctx.symbol_commit_message = ( + "This commit was manufactured by cvs2svn to create %(symbol_type)s " + "'%(symbol_name)s'." + ) + +# Template for the commit message to be used for commits in which +# tags are pseudo-merged back to their source branch. This message can +# use '%(symbol_name)s' to include the name of the symbol. +# (Not used by default unless you enable tie_tag_fixup_branches on +# GitOutputOption.) +ctx.tie_tag_ancestry_message = ( + "This commit was manufactured by cvs2svn to tie ancestry for " + "tag '%(symbol_name)s' back to the source branch." + ) + +# Some CVS clients for MacOS store resource fork data into CVS along +# with the file contents itself by wrapping it all up in a container +# format called "AppleSingle". Subversion currently does not support +# MacOS resource forks. Nevertheless, sometimes the resource fork +# information is not necessary and can be discarded. Set the +# following option to True if you would like cvs2svn to identify files +# whose contents are encoded in AppleSingle format, and discard all +# but the data fork for such files before committing them to +# Subversion. (Please note that AppleSingle contents are identified +# by the AppleSingle magic number as the first four bytes of the file. +# This check is not failproof, so only set this option if you think +# you need it.) +ctx.decode_apple_single = False + +# This option can be set to the name of a filename to which are stored +# statistics and conversion decisions about the CVS symbols. +ctx.symbol_info_filename = None +#ctx.symbol_info_filename = 'symbol-info.txt' + +# cvs2svn uses "symbol strategy rules" to help decide how to handle +# CVS symbols. The rules in a project's symbol_strategy_rules are +# applied in order, and each rule is allowed to modify the symbol. +# The result (after each of the rules has been applied) is used for +# the conversion. +# +# 1. A CVS symbol might be used as a tag in one file and as a branch +# in another file. cvs2svn has to decide whether to convert such a +# symbol as a tag or as a branch. cvs2svn uses a series of +# heuristic rules to decide how to convert a symbol. The user can +# override the default rules for specific symbols or symbols +# matching regular expressions. +# +# 2. cvs2svn is also capable of excluding symbols from the conversion +# (provided no other symbols depend on them. +# +# 3. CVS does not record unambiguously the line of development from +# which a symbol sprouted. cvs2svn uses a heuristic to choose a +# symbol's "preferred parents". +# +# The standard branch/tag/exclude StrategyRules do not change a symbol +# that has already been processed by an earlier rule, so in effect the +# first matching rule is the one that is used. + +global_symbol_strategy_rules = [ + # It is possible to specify manually exactly how symbols should be + # converted and what line of development should be used as the + # preferred parent. To do so, create a file containing the symbol + # hints and enable the following option. + # + # The format of the hints file is described in the documentation + # for the --symbol-hints command-line option. The file output by + # the --write-symbol-info (i.e., ctx.symbol_info_filename) option + # is in the same format. The simplest way to use this option is + # to run the conversion through CollateSymbolsPass with + # --write-symbol-info option, copy the symbol info and edit it to + # create a hints file, then re-start the conversion at + # CollateSymbolsPass with this option enabled. + #SymbolHintsFileRule('symbol-hints.txt'), + + # To force all symbols matching a regular expression to be + # converted as branches, add rules like the following: + #ForceBranchRegexpStrategyRule(r'branch.*'), + + # To force all symbols matching a regular expression to be + # converted as tags, add rules like the following: + #ForceTagRegexpStrategyRule(r'tag.*'), + + # To force all symbols matching a regular expression to be + # excluded from the conversion, add rules like the following: + #ExcludeRegexpStrategyRule(r'unknown-.*'), + + # Sometimes people use "cvs import" to get their own source code + # into CVS. This practice creates a vendor branch 1.1.1 and + # imports the code onto the vendor branch as 1.1.1.1, then copies + # the same content to the trunk as version 1.1. Normally, such + # vendor branches are useless and they complicate the SVN history + # unnecessarily. The following rule excludes any branches that + # only existed as a vendor branch with a single import (leaving + # only the 1.1 revision). If you want to retain such branches, + # comment out the following line. (Please note that this rule + # does not exclude vendor *tags*, as they are not so easy to + # identify.) + ExcludeTrivialImportBranchRule(), + + # To exclude all vendor branches (branches that had "cvs import"s + # on them bug no other kinds of commits), uncomment the following + # line: + #ExcludeVendorBranchRule(), + + # Usually you want this rule, to convert unambiguous symbols + # (symbols that were only ever used as tags or only ever used as + # branches in CVS) the same way they were used in CVS: + UnambiguousUsageRule(), + + # If there was ever a commit on a symbol, then it cannot be + # converted as a tag. This rule causes all such symbols to be + # converted as branches. If you would like to resolve such + # ambiguities manually, comment out the following line: + BranchIfCommitsRule(), + + # Last in the list can be a catch-all rule that is used for + # symbols that were not matched by any of the more specific rules + # above. (Assuming that BranchIfCommitsRule() was included above, + # then the symbols that are still indeterminate at this point can + # sensibly be converted as branches or tags.) Include at most one + # of these lines. If none of these catch-all rules are included, + # then the presence of any ambiguous symbols (that haven't been + # disambiguated above) is an error: + + # Convert ambiguous symbols based on whether they were used more + # often as branches or as tags: + HeuristicStrategyRule(), + # Convert all ambiguous symbols as branches: + #AllBranchRule(), + # Convert all ambiguous symbols as tags: + #AllTagRule(), + + # The last rule is here to choose the preferred parent of branches + # and tags, that is, the line of development from which the symbol + # sprouts. + HeuristicPreferredParentRule(), + ] + +# Specify a username to be used for commits for which CVS doesn't +# record the original author (for example, the creation of a branch). +# This should be a simple (unix-style) username, but it can be +# translated into a git-style name by the author_transforms map. +ctx.username = 'cvs2svn' + +# ctx.svn_property_setters contains a list of rules used to set the +# svn properties on files in the converted archive. For each file, +# the rules are tried one by one. Any rule can add or suppress one or +# more svn properties. Typically the rules will not overwrite +# properties set by a previous rule (though they are free to do so). +# +# Obviously, SVN properties per se are not interesting for a cvs2git +# conversion, but some of these properties have side-effects that do +# affect the git output. FIXME: Document this in more detail. +ctx.svn_property_setters.extend([ + # To read auto-props rules from a file, uncomment the following line + # and specify a filename. The boolean argument specifies whether + # case should be ignored when matching filenames to the filename + # patterns found in the auto-props file: + #AutoPropsPropertySetter( + # r'/home/username/.subversion/config', + # ignore_case=True, + # ), + + # To read mime types from a file, uncomment the following line and + # specify a filename: + #MimeMapper(r'/etc/mime.types'), + + # Omit the svn:eol-style property from any files that are listed + # as binary (i.e., mode '-kb') in CVS: + CVSBinaryFileEOLStyleSetter(), + + # If the file is binary and its svn:mime-type property is not yet + # set, set svn:mime-type to 'application/octet-stream'. + CVSBinaryFileDefaultMimeTypeSetter(), + + # To try to determine the eol-style from the mime type, uncomment + # the following line: + #EOLStyleFromMimeTypeSetter(), + + # Choose one of the following lines to set the default + # svn:eol-style if none of the above rules applied. The argument + # is the svn:eol-style that should be applied, or None if no + # svn:eol-style should be set (i.e., the file should be treated as + # binary). + # + # The default is to treat all files as binary unless one of the + # previous rules has determined otherwise, because this is the + # safest approach. However, if you have been diligent about + # marking binary files with -kb in CVS and/or you have used the + # above rules to definitely mark binary files as binary, then you + # might prefer to use 'native' as the default, as it is usually + # the most convenient setting for text files. Other possible + # options: 'CRLF', 'CR', 'LF'. + DefaultEOLStyleSetter(None), + #DefaultEOLStyleSetter('native'), + + # Prevent svn:keywords from being set on files that have + # svn:eol-style unset. + SVNBinaryFileKeywordsPropertySetter(), + + # If svn:keywords has not been set yet, set it based on the file's + # CVS mode: + KeywordsPropertySetter(config.SVN_KEYWORDS_VALUE), + + # Set the svn:executable flag on any files that are marked in CVS as + # being executable: + ExecutablePropertySetter(), + + ]) + +# The directory to use for temporary files: +ctx.tmpdir = r'cvs2svn-tmp' + +# To skip the cleanup of temporary files, uncomment the following +# option: +#ctx.skip_cleanup = True + + +# In CVS, it is perfectly possible to make a single commit that +# affects more than one project or more than one branch of a single +# project. Subversion also allows such commits. Therefore, by +# default, when cvs2svn sees what looks like a cross-project or +# cross-branch CVS commit, it converts it into a +# cross-project/cross-branch Subversion commit. +# +# However, other tools and SCMs have trouble representing +# cross-project or cross-branch commits. (For example, Trac's Revtree +# plugin, http://www.trac-hacks.org/wiki/RevtreePlugin is confused by +# such commits.) Therefore, we provide the following two options to +# allow cross-project/cross-branch commits to be suppressed. + +# cvs2git only supports single-project conversions (multiple-project +# conversions wouldn't really make sense for git anyway). So this +# option must be set to False: +ctx.cross_project_commits = False + +# git itself doesn't allow commits that affect more than one branch, +# so this option must be set to False: +ctx.cross_branch_commits = False + +# cvs2git does not yet handle translating .cvsignore files into +# .gitignore files, so by default, the .cvsignore files are included +# in the conversion output. If you would like to omit the .cvsignore +# files from the output, set this option to False: +ctx.keep_cvsignore = True + +# By default, it is a fatal error for a CVS ",v" file to appear both +# inside and outside of an "Attic" subdirectory (this should never +# happen, but frequently occurs due to botched repository +# administration). If you would like to retain both versions of such +# files, change the following option to True, and the attic version of +# the file will be written to a subdirectory called "Attic" in the +# output repository: +ctx.retain_conflicting_attic_files = False + +# CVS uses unix login names as author names whereas git requires +# author names to be of the form "foo ". The default is to set +# the git author to "cvsauthor ". author_transforms can be +# used to map cvsauthor names (e.g., "jrandom") to a true name and +# email address (e.g., "J. Random " for the +# example shown). All values should be either Unicode strings (i.e., +# with "u" as a prefix) or 8-bit strings in the utf-8 encoding. +# Please substitute your own project's usernames here to use with the +# author_transforms option of GitOutputOption below. +author_transforms={ + 'alain' : ('Alain Greiner' , 'alliance-cvs@asim.lip6.fr'), + 'boris' : ('Boris Boutillier' , 'alliance-cvs@asim.lip6.fr'), + 'czo' : ('Olivier Sirol' , 'alliance-cvs@asim.lip6.fr'), + 'd2' : ('Damien Dupuis' , 'alliance-cvs@asim.lip6.fr'), + 'dom' : ('Dominique Ledu' , 'alliance-cvs@asim.lip6.fr'), + 'franck' : ('Franck Wajsburt' , 'alliance-cvs@asim.lip6.fr'), + 'francois' : ('Francois Donnet' , 'alliance-cvs@asim.lip6.fr'), + 'fred' : ('Frederic Petrot' , 'alliance-cvs@asim.lip6.fr'), + 'gregoire' : ('Gregoire Avot' , 'alliance-cvs@asim.lip6.fr'), + 'hcl' : ('Hugo Clement' , 'alliance-cvs@asim.lip6.fr'), + 'jpc' : ('Jean-Paul Chaput' , 'Jean-Paul.Chaput@lip6.fr' ), + 'karim' : ('Karim Dioury' , 'alliance-cvs@asim.lip6.fr'), + 'ludo' : ('Ludovic Jacomme' , 'alliance-cvs@asim.lip6.fr'), + 'noury' : ('Ludovic Noury' , 'alliance-cvs@asim.lip6.fr'), + 'pnt' : ('Pierre Nguyen Tuong' , 'alliance-cvs@asim.lip6.fr'), + 'sirol' : ('Olivier Sirol' , 'alliance-cvs@asim.lip6.fr'), + 'xtof' : ('Christophe Alexandre' , 'alliance-cvs@asim.lip6.fr'), + + 'alliance' : ('The Alliance Tool' , 'alliance-cvs@asim.lip6.fr'), + 'asimut' : ('The Asimut Tool' , 'alliance-cvs@asim.lip6.fr'), + 'asm' : ('The ASM Tool' , 'alliance-cvs@asim.lip6.fr'), + 'beh' : ('The BEH Tool' , 'alliance-cvs@asim.lip6.fr'), + 'behvhdl' : ('The BEHVHDL Tool' , 'alliance-cvs@asim.lip6.fr'), + 'cns' : ('The CNS Tool' , 'alliance-cvs@asim.lip6.fr'), + 'dreal' : ('The Dreal Tool' , 'alliance-cvs@asim.lip6.fr'), + 'graal' : ('The Graal Tool' , 'alliance-cvs@asim.lip6.fr'), + 'lynx' : ('The Lynx Tool' , 'alliance-cvs@asim.lip6.fr'), + 'outil' : ('The Generic Tool' , 'alliance-cvs@asim.lip6.fr'), + 'rds' : ('The RDS Tool' , 'alliance-cvs@asim.lip6.fr'), + 'simcity' : ('The Simcity Tool' , 'alliance-cvs@asim.lip6.fr'), + 'syf' : ('The Syf Tool' , 'alliance-cvs@asim.lip6.fr'), + + 'ac' : ('Forgotten Author (ac)' , 'alliance-cvs@asim.lip6.fr'), + 'ana' : ('Forgotten Author (ana)' , 'alliance-cvs@asim.lip6.fr'), + 'dea9527' : ('Forgotten Author (dea9527)', 'alliance-cvs@asim.lip6.fr'), + 'mai0009' : ('Forgotten Author (mai0009)', 'alliance-cvs@asim.lip6.fr'), + 'nagat' : ('Forgotten Author (nagat)' , 'alliance-cvs@asim.lip6.fr'), + 'olivier' : ('Forgotten Author (olivier)', 'alliance-cvs@asim.lip6.fr'), + 'uid809' : ('Forgotten Author (uid809)' , 'alliance-cvs@asim.lip6.fr'), + 'vancour' : ('Forgotten Author (vancour)', 'alliance-cvs@asim.lip6.fr'), + 'vincent' : ('Forgotten Author (vincent)', 'alliance-cvs@asim.lip6.fr'), + + # This one will be used for commits for which CVS doesn't record + # the original author, as explained above. + 'cvs2svn' : ('cvs2svn', 'alliance-cvs@asim.lip6.fr'), + } + +# This is the main option that causes cvs2svn to output to a +# "fastimport"-format dumpfile rather than to Subversion: +ctx.output_option = GitOutputOption( + # The file in which to write the git-fast-import stream that + # contains the changesets and branch/tag information: + 'cvs2svn-tmp/git-dump.dat', + + # The blobs will be written via the revision recorder, so in + # OutputPass we only have to emit references to the blob marks: + GitRevisionMarkWriter(), + + # Optional map from CVS author names to git author names: + author_transforms=author_transforms, + ) + +# Change this option to True to turn on profiling of cvs2svn (for +# debugging purposes): +run_options.profiling = False + + +# Should CVSItem -> Changeset database files be memory mapped? In +# some tests, using memory mapping speeded up the overall conversion +# by about 5%. But this option can cause the conversion to fail with +# an out of memory error if the conversion computer runs out of +# virtual address space (e.g., when running a very large conversion on +# a 32-bit operating system). Therefore it is disabled by default. +# Uncomment the following line to allow these database files to be +# memory mapped. +#changeset_database.use_mmap_for_cvs_item_to_changeset_table = True + +# Now set the project to be converted to git. cvs2git only supports +# single-project conversions, so this method must only be called +# once: +run_options.set_project( + # The filesystem path to the part of the CVS repository (*not* a + # CVS working copy) that should be converted. This may be a + # subdirectory (i.e., a module) within a larger CVS repository. + r'/dsk/l1/alliance/cvsroot', + + # A list of symbol transformations that can be used to rename + # symbols in this project. + symbol_transforms=[ + # Use IgnoreSymbolTransforms like the following to completely + # ignore symbols matching a regular expression when parsing + # the CVS repository, for example to avoid warnings about + # branches with two names and to choose the preferred name. + # It is *not* recommended to use this instead of + # ExcludeRegexpStrategyRule; though more efficient, + # IgnoreSymbolTransforms are less flexible and don't exclude + # branches correctly. The argument is a Python-style regular + # expression that has to match the *whole* CVS symbol name: + #IgnoreSymbolTransform(r'nightly-build-tag-.*') + + # RegexpSymbolTransforms transform symbols textually using a + # regular expression. The first argument is a Python regular + # expression pattern and the second is a replacement pattern. + # The pattern is matched against each symbol name. If it + # matches the whole symbol name, then the symbol name is + # replaced with the corresponding replacement text. The + # replacement can include substitution patterns (e.g., r'\1' + # or r'\g'). Typically you will want to use raw strings + # (strings with a preceding 'r', like shown in the examples) + # for the regexp and its replacement to avoid backslash + # substitution within those strings. + #RegexpSymbolTransform(r'release-(\d+)_(\d+)', + # r'release-\1.\2'), + #RegexpSymbolTransform(r'release-(\d+)_(\d+)_(\d+)', + # r'release-\1.\2.\3'), + + # Simple 1:1 character replacements can also be done. The + # following transform, which converts backslashes into forward + # slashes, should usually be included: + ReplaceSubstringsSymbolTransform('\\','/'), + + # This last rule eliminates leading, trailing, and repeated + # slashes within the output symbol names: + NormalizePathsSymbolTransform(), + ], + + # See the definition of global_symbol_strategy_rules above for a + # description of this option: + symbol_strategy_rules=global_symbol_strategy_rules, + ) + diff --git a/bootstrap/svn2git/cvs2git-arith.options b/bootstrap/svn2git/cvs2git-arith.options new file mode 100644 index 00000000..b6fb17f3 --- /dev/null +++ b/bootstrap/svn2git/cvs2git-arith.options @@ -0,0 +1,622 @@ +# (Be in -*- mode: python; coding: utf-8 -*- mode.) +# +# ==================================================================== +# Copyright (c) 2006-2009 CollabNet. All rights reserved. +# +# This software is licensed as described in the file COPYING, which +# you should have received as part of this distribution. The terms +# are also available at http://subversion.tigris.org/license-1.html. +# If newer versions of this license are posted there, you may use a +# newer version instead, at your option. +# +# This software consists of voluntary contributions made by many +# individuals. For exact contribution history, see the revision +# history and logs, available at http://cvs2svn.tigris.org/. +# ==================================================================== + +# ##################### +# ## PLEASE READ ME! ## +# ##################### +# +# This is a template for an options file that can be used to configure +# cvs2svn to convert to git rather than to Subversion. See +# www/cvs2svn.html and www/cvs2svn.html for general information, and +# see the comments in this file for information about what options are +# available and how they can be set. +# +# The program that is run to convert from CVS to git is called +# cvs2svn. Run it with the --options option, passing it this file +# like this: +# +# cvs2svn --options=cvs2svn-example.options +# +# The output of cvs2svn is a blob file and a dump file that can be +# loaded into git using the "git fast-import" command. Please read +# www/cvs2svn.html for more information. +# +# Many options do not have defaults, so it is easier to copy this file +# and modify what you need rather than creating a new options file +# from scratch. This file is in Python syntax, but you don't need to +# know Python to modify it. But if you *do* know Python, then you +# will be happy to know that you can use arbitary Python constructs to +# do fancy configuration tricks. +# +# But please be aware of the following: +# +# * In many places, leading whitespace is significant in Python (it is +# used instead of curly braces to group statements together). +# Therefore, if you don't know what you are doing, it is best to +# leave the whitespace as it is. +# +# * In normal strings, Python treats a backslash ("\") as an escape +# character. Therefore, if you want to specify a string that +# contains a backslash, you need either to escape the backslash with +# another backslash ("\\"), or use a "raw string", as in one if the +# following equivalent examples: +# +# cvs_executable = 'c:\\windows\\system32\\cvs.exe' +# cvs_executable = r'c:\windows\system32\cvs.exe' +# +# See http://docs.python.org/tutorial/introduction.html#strings for +# more information. +# +# Two identifiers will have been defined before this file is executed, +# and can be used freely within this file: +# +# ctx -- a Ctx object (see cvs2svn_lib/context.py), which holds +# many configuration options +# +# run_options -- an instance of the GitRunOptions class (see +# cvs2svn_lib/git_run_options.py), which holds some variables +# governing how cvs2svn is run + + +# Import some modules that are used in setting the options: +import re + +from cvs2svn_lib import config +from cvs2svn_lib import changeset_database +from cvs2svn_lib.common import CVSTextDecoder +from cvs2svn_lib.log import Log +from cvs2svn_lib.project import Project +from cvs2svn_lib.git_revision_recorder import GitRevisionRecorder +from cvs2svn_lib.git_output_option import GitRevisionMarkWriter +from cvs2svn_lib.git_output_option import GitOutputOption +from cvs2svn_lib.revision_manager import NullRevisionRecorder +from cvs2svn_lib.revision_manager import NullRevisionExcluder +from cvs2svn_lib.fulltext_revision_recorder \ + import SimpleFulltextRevisionRecorderAdapter +from cvs2svn_lib.rcs_revision_manager import RCSRevisionReader +from cvs2svn_lib.cvs_revision_manager import CVSRevisionReader +from cvs2svn_lib.checkout_internal import InternalRevisionRecorder +from cvs2svn_lib.checkout_internal import InternalRevisionExcluder +from cvs2svn_lib.checkout_internal import InternalRevisionReader +from cvs2svn_lib.symbol_strategy import AllBranchRule +from cvs2svn_lib.symbol_strategy import AllTagRule +from cvs2svn_lib.symbol_strategy import BranchIfCommitsRule +from cvs2svn_lib.symbol_strategy import ExcludeRegexpStrategyRule +from cvs2svn_lib.symbol_strategy import ForceBranchRegexpStrategyRule +from cvs2svn_lib.symbol_strategy import ForceTagRegexpStrategyRule +from cvs2svn_lib.symbol_strategy import ExcludeTrivialImportBranchRule +from cvs2svn_lib.symbol_strategy import ExcludeVendorBranchRule +from cvs2svn_lib.symbol_strategy import HeuristicStrategyRule +from cvs2svn_lib.symbol_strategy import UnambiguousUsageRule +from cvs2svn_lib.symbol_strategy import HeuristicPreferredParentRule +from cvs2svn_lib.symbol_strategy import SymbolHintsFileRule +from cvs2svn_lib.symbol_transform import ReplaceSubstringsSymbolTransform +from cvs2svn_lib.symbol_transform import RegexpSymbolTransform +from cvs2svn_lib.symbol_transform import IgnoreSymbolTransform +from cvs2svn_lib.symbol_transform import NormalizePathsSymbolTransform +from cvs2svn_lib.property_setters import AutoPropsPropertySetter +from cvs2svn_lib.property_setters import CVSBinaryFileDefaultMimeTypeSetter +from cvs2svn_lib.property_setters import CVSBinaryFileEOLStyleSetter +from cvs2svn_lib.property_setters import DefaultEOLStyleSetter +from cvs2svn_lib.property_setters import EOLStyleFromMimeTypeSetter +from cvs2svn_lib.property_setters import ExecutablePropertySetter +from cvs2svn_lib.property_setters import KeywordsPropertySetter +from cvs2svn_lib.property_setters import MimeMapper +from cvs2svn_lib.property_setters import SVNBinaryFileKeywordsPropertySetter + +# To choose the level of logging output, uncomment one of the +# following lines: +#Log().log_level = Log.WARN +#Log().log_level = Log.QUIET +Log().log_level = Log.NORMAL +#Log().log_level = Log.VERBOSE +#Log().log_level = Log.DEBUG + + +# During CollectRevsPass, cvs2svn records the contents of file +# revisions into a "blob" file in git-fast-import format. This option +# configures that process: +ctx.revision_recorder = SimpleFulltextRevisionRecorderAdapter( + # The following option specifies how the revision contents of the RCS + # files should be read. + # + # RCSRevisionReader uses RCS's "co" program to extract the revision + # contents of the RCS files during CollectRevsPass. The constructor + # argument specifies how to invoke the "co" executable. + # + # CVSRevisionReader uses the "cvs" program to extract the revision + # contents out of the RCS files during OutputPass. This option is + # considerably slower than RCSRevisionReader because "cvs" is + # considerably slower than "co". However, it works in some situations + # where RCSRevisionReader fails; see the HTML documentation of the + # "--use-cvs" option for details. The constructor argument specifies + # how to invoke the "co" executable. + # + # Uncomment one of the two following lines: + #RCSRevisionReader(co_executable=r'co'), + CVSRevisionReader(cvs_executable=r'cvs'), + + # The file in which to write the git-fast-import stream that + # contains the file revision contents: + GitRevisionRecorder('cvs2svn-tmp/git-blob.dat'), + ) + +# cvs2svn does not need to keep track of what revisions will be +# excluded, so leave this option unchanged: +ctx.revision_excluder = NullRevisionExcluder() + +# cvs2svn doesn't need a revision reader because OutputPass only +# refers to blobs that were output during CollectRevsPass, so leave +# this option set to None. +ctx.revision_reader = None + +# Change the following line to True if the conversion should only +# include the trunk of the repository (i.e., all branches and tags +# should be omitted from the conversion): +ctx.trunk_only = False + +# How to convert CVS author names, log messages, and filenames to +# Unicode. The first argument to CVSTextDecoder is a list of encoders +# that are tried in order in 'strict' mode until one of them succeeds. +# If none of those succeeds, then fallback_encoder (if it is +# specified) is used in lossy 'replace' mode. Setting a fallback +# encoder ensures that the encoder always succeeds, but it can cause +# information loss. +ctx.cvs_author_decoder = CVSTextDecoder( + [ + 'latin1', + 'utf8', + 'ascii', + ], + fallback_encoding='latin1' + ) +ctx.cvs_log_decoder = CVSTextDecoder( + [ + 'latin1', + 'utf8', + 'ascii', + ], + fallback_encoding='latin1' + ) +# You might want to be especially strict when converting filenames to +# Unicode (e.g., maybe not specify a fallback_encoding). +ctx.cvs_filename_decoder = CVSTextDecoder( + [ + 'latin1', + 'utf8', + 'ascii', + ], + fallback_encoding='latin1' + ) + +# Template for the commit message to be used for initial project +# commits. +ctx.initial_project_commit_message = ( + 'Standard project directories initialized by cvs2svn.' + ) + +# Template for the commit message to be used for post commits, in +# which modifications to a vendor branch are copied back to trunk. +# This message can use '%(revnum)d' to include the SVN revision number +# of the revision that included the change to the vendor branch +# (admittedly rather pointless in a cvs2svn conversion). +ctx.post_commit_message = ( + 'This commit was generated by cvs2svn to track changes on a CVS ' + 'vendor branch.' + ) + +# Template for the commit message to be used for commits in which +# symbols are created. This message can use '%(symbol_type)s' to +# include the type of the symbol ('branch' or 'tag') or +# '%(symbol_name)s' to include the name of the symbol. +ctx.symbol_commit_message = ( + "This commit was manufactured by cvs2svn to create %(symbol_type)s " + "'%(symbol_name)s'." + ) + +# Template for the commit message to be used for commits in which +# tags are pseudo-merged back to their source branch. This message can +# use '%(symbol_name)s' to include the name of the symbol. +# (Not used by default unless you enable tie_tag_fixup_branches on +# GitOutputOption.) +ctx.tie_tag_ancestry_message = ( + "This commit was manufactured by cvs2svn to tie ancestry for " + "tag '%(symbol_name)s' back to the source branch." + ) + +# Some CVS clients for MacOS store resource fork data into CVS along +# with the file contents itself by wrapping it all up in a container +# format called "AppleSingle". Subversion currently does not support +# MacOS resource forks. Nevertheless, sometimes the resource fork +# information is not necessary and can be discarded. Set the +# following option to True if you would like cvs2svn to identify files +# whose contents are encoded in AppleSingle format, and discard all +# but the data fork for such files before committing them to +# Subversion. (Please note that AppleSingle contents are identified +# by the AppleSingle magic number as the first four bytes of the file. +# This check is not failproof, so only set this option if you think +# you need it.) +ctx.decode_apple_single = False + +# This option can be set to the name of a filename to which are stored +# statistics and conversion decisions about the CVS symbols. +ctx.symbol_info_filename = None +#ctx.symbol_info_filename = 'symbol-info.txt' + +# cvs2svn uses "symbol strategy rules" to help decide how to handle +# CVS symbols. The rules in a project's symbol_strategy_rules are +# applied in order, and each rule is allowed to modify the symbol. +# The result (after each of the rules has been applied) is used for +# the conversion. +# +# 1. A CVS symbol might be used as a tag in one file and as a branch +# in another file. cvs2svn has to decide whether to convert such a +# symbol as a tag or as a branch. cvs2svn uses a series of +# heuristic rules to decide how to convert a symbol. The user can +# override the default rules for specific symbols or symbols +# matching regular expressions. +# +# 2. cvs2svn is also capable of excluding symbols from the conversion +# (provided no other symbols depend on them. +# +# 3. CVS does not record unambiguously the line of development from +# which a symbol sprouted. cvs2svn uses a heuristic to choose a +# symbol's "preferred parents". +# +# The standard branch/tag/exclude StrategyRules do not change a symbol +# that has already been processed by an earlier rule, so in effect the +# first matching rule is the one that is used. + +global_symbol_strategy_rules = [ + # It is possible to specify manually exactly how symbols should be + # converted and what line of development should be used as the + # preferred parent. To do so, create a file containing the symbol + # hints and enable the following option. + # + # The format of the hints file is described in the documentation + # for the --symbol-hints command-line option. The file output by + # the --write-symbol-info (i.e., ctx.symbol_info_filename) option + # is in the same format. The simplest way to use this option is + # to run the conversion through CollateSymbolsPass with + # --write-symbol-info option, copy the symbol info and edit it to + # create a hints file, then re-start the conversion at + # CollateSymbolsPass with this option enabled. + #SymbolHintsFileRule('symbol-hints.txt'), + + # To force all symbols matching a regular expression to be + # converted as branches, add rules like the following: + #ForceBranchRegexpStrategyRule(r'branch.*'), + + # To force all symbols matching a regular expression to be + # converted as tags, add rules like the following: + #ForceTagRegexpStrategyRule(r'tag.*'), + + # To force all symbols matching a regular expression to be + # excluded from the conversion, add rules like the following: + #ExcludeRegexpStrategyRule(r'unknown-.*'), + + # Sometimes people use "cvs import" to get their own source code + # into CVS. This practice creates a vendor branch 1.1.1 and + # imports the code onto the vendor branch as 1.1.1.1, then copies + # the same content to the trunk as version 1.1. Normally, such + # vendor branches are useless and they complicate the SVN history + # unnecessarily. The following rule excludes any branches that + # only existed as a vendor branch with a single import (leaving + # only the 1.1 revision). If you want to retain such branches, + # comment out the following line. (Please note that this rule + # does not exclude vendor *tags*, as they are not so easy to + # identify.) + ExcludeTrivialImportBranchRule(), + + # To exclude all vendor branches (branches that had "cvs import"s + # on them bug no other kinds of commits), uncomment the following + # line: + #ExcludeVendorBranchRule(), + + # Usually you want this rule, to convert unambiguous symbols + # (symbols that were only ever used as tags or only ever used as + # branches in CVS) the same way they were used in CVS: + UnambiguousUsageRule(), + + # If there was ever a commit on a symbol, then it cannot be + # converted as a tag. This rule causes all such symbols to be + # converted as branches. If you would like to resolve such + # ambiguities manually, comment out the following line: + BranchIfCommitsRule(), + + # Last in the list can be a catch-all rule that is used for + # symbols that were not matched by any of the more specific rules + # above. (Assuming that BranchIfCommitsRule() was included above, + # then the symbols that are still indeterminate at this point can + # sensibly be converted as branches or tags.) Include at most one + # of these lines. If none of these catch-all rules are included, + # then the presence of any ambiguous symbols (that haven't been + # disambiguated above) is an error: + + # Convert ambiguous symbols based on whether they were used more + # often as branches or as tags: + HeuristicStrategyRule(), + # Convert all ambiguous symbols as branches: + #AllBranchRule(), + # Convert all ambiguous symbols as tags: + #AllTagRule(), + + # The last rule is here to choose the preferred parent of branches + # and tags, that is, the line of development from which the symbol + # sprouts. + HeuristicPreferredParentRule(), + ] + +# Specify a username to be used for commits for which CVS doesn't +# record the original author (for example, the creation of a branch). +# This should be a simple (unix-style) username, but it can be +# translated into a git-style name by the author_transforms map. +ctx.username = 'cvs2svn' + +# ctx.svn_property_setters contains a list of rules used to set the +# svn properties on files in the converted archive. For each file, +# the rules are tried one by one. Any rule can add or suppress one or +# more svn properties. Typically the rules will not overwrite +# properties set by a previous rule (though they are free to do so). +# +# Obviously, SVN properties per se are not interesting for a cvs2svn +# conversion, but some of these properties have side-effects that do +# affect the git output. FIXME: Document this in more detail. +ctx.svn_property_setters.extend([ + # To read auto-props rules from a file, uncomment the following line + # and specify a filename. The boolean argument specifies whether + # case should be ignored when matching filenames to the filename + # patterns found in the auto-props file: + #AutoPropsPropertySetter( + # r'/home/username/.subversion/config', + # ignore_case=True, + # ), + + # To read mime types from a file, uncomment the following line and + # specify a filename: + #MimeMapper(r'/etc/mime.types'), + + # Omit the svn:eol-style property from any files that are listed + # as binary (i.e., mode '-kb') in CVS: + CVSBinaryFileEOLStyleSetter(), + + # If the file is binary and its svn:mime-type property is not yet + # set, set svn:mime-type to 'application/octet-stream'. + CVSBinaryFileDefaultMimeTypeSetter(), + + # To try to determine the eol-style from the mime type, uncomment + # the following line: + #EOLStyleFromMimeTypeSetter(), + + # Choose one of the following lines to set the default + # svn:eol-style if none of the above rules applied. The argument + # is the svn:eol-style that should be applied, or None if no + # svn:eol-style should be set (i.e., the file should be treated as + # binary). + # + # The default is to treat all files as binary unless one of the + # previous rules has determined otherwise, because this is the + # safest approach. However, if you have been diligent about + # marking binary files with -kb in CVS and/or you have used the + # above rules to definitely mark binary files as binary, then you + # might prefer to use 'native' as the default, as it is usually + # the most convenient setting for text files. Other possible + # options: 'CRLF', 'CR', 'LF'. + DefaultEOLStyleSetter(None), + #DefaultEOLStyleSetter('native'), + + # Prevent svn:keywords from being set on files that have + # svn:eol-style unset. + SVNBinaryFileKeywordsPropertySetter(), + + # If svn:keywords has not been set yet, set it based on the file's + # CVS mode: + KeywordsPropertySetter(config.SVN_KEYWORDS_VALUE), + + # Set the svn:executable flag on any files that are marked in CVS as + # being executable: + ExecutablePropertySetter(), + + ]) + +# The directory to use for temporary files: +ctx.tmpdir = r'cvs2svn-tmp' + +# To skip the cleanup of temporary files, uncomment the following +# option: +#ctx.skip_cleanup = True + + +# In CVS, it is perfectly possible to make a single commit that +# affects more than one project or more than one branch of a single +# project. Subversion also allows such commits. Therefore, by +# default, when cvs2svn sees what looks like a cross-project or +# cross-branch CVS commit, it converts it into a +# cross-project/cross-branch Subversion commit. +# +# However, other tools and SCMs have trouble representing +# cross-project or cross-branch commits. (For example, Trac's Revtree +# plugin, http://www.trac-hacks.org/wiki/RevtreePlugin is confused by +# such commits.) Therefore, we provide the following two options to +# allow cross-project/cross-branch commits to be suppressed. + +# cvs2svn only supports single-project conversions (multiple-project +# conversions wouldn't really make sense for git anyway). So this +# option must be set to False: +ctx.cross_project_commits = False + +# git itself doesn't allow commits that affect more than one branch, +# so this option must be set to False: +ctx.cross_branch_commits = False + +# cvs2svn does not yet handle translating .cvsignore files into +# .gitignore files, so by default, the .cvsignore files are included +# in the conversion output. If you would like to omit the .cvsignore +# files from the output, set this option to False: +ctx.keep_cvsignore = True + +# By default, it is a fatal error for a CVS ",v" file to appear both +# inside and outside of an "Attic" subdirectory (this should never +# happen, but frequently occurs due to botched repository +# administration). If you would like to retain both versions of such +# files, change the following option to True, and the attic version of +# the file will be written to a subdirectory called "Attic" in the +# output repository: +ctx.retain_conflicting_attic_files = False + +# CVS uses unix login names as author names whereas git requires +# author names to be of the form "foo ". The default is to set +# the git author to "cvsauthor ". author_transforms can be +# used to map cvsauthor names (e.g., "jrandom") to a true name and +# email address (e.g., "J. Random " for the +# example shown). All values should be either Unicode strings (i.e., +# with "u" as a prefix) or 8-bit strings in the utf-8 encoding. +# Please substitute your own project's usernames here to use with the +# author_transforms option of GitOutputOption below. +author_transforms={ + 'alain' : ('Alain Greiner' , 'arith-devel@soc.lip6.fr'), + 'boris' : ('Boris Boutillier' , 'arith-devel@soc.lip6.fr'), + 'czo' : ('Olivier Sirol' , 'arith-devel@soc.lip6.fr'), + 'cobell' : ('Sophie Belloeil' , 'arith-devel@soc.lip6.fr'), + 'd2' : ('Damien Dupuis' , 'arith-devel@soc.lip6.fr'), + 'dom' : ('Dominique Ledu' , 'arith-devel@soc.lip6.fr'), + 'franck' : ('Franck Wajsburt' , 'arith-devel@soc.lip6.fr'), + 'francois' : ('Francois Donnet' , 'arith-devel@soc.lip6.fr'), + 'fred' : ('Frederic Petrot' , 'arith-devel@soc.lip6.fr'), + 'gregoire' : ('Gregoire Avot' , 'arith-devel@soc.lip6.fr'), + 'hcl' : ('Hugo Clement' , 'arith-devel@soc.lip6.fr'), + 'jpc' : ('Jean-Paul Chaput' , 'Jean-Paul.Chaput@lip6.fr' ), + 'karim' : ('Karim Dioury' , 'arith-devel@soc.lip6.fr'), + 'ludo' : ('Ludovic Jacomme' , 'arith-devel@soc.lip6.fr'), + 'noury' : ('Ludovic Noury' , 'arith-devel@soc.lip6.fr'), + 'pnt' : ('Pierre Nguyen Tuong' , 'arith-devel@soc.lip6.fr'), + 'roselyne' : ('Roselyne Chotin-Avot' , 'Roselyne.Chotin-Avot@lip6.fr'), + 'sirol' : ('Olivier Sirol' , 'arith-devel@soc.lip6.fr'), + 'xtof' : ('Christophe Alexandre' , 'arith-devel@soc.lip6.fr'), + + 'alliance' : ('The Alliance Tool' , 'arith-devel@soc.lip6.fr'), + 'asimut' : ('The Asimut Tool' , 'arith-devel@soc.lip6.fr'), + 'asm' : ('The ASM Tool' , 'arith-devel@soc.lip6.fr'), + 'beh' : ('The BEH Tool' , 'arith-devel@soc.lip6.fr'), + 'behvhdl' : ('The BEHVHDL Tool' , 'arith-devel@soc.lip6.fr'), + 'cns' : ('The CNS Tool' , 'arith-devel@soc.lip6.fr'), + 'dreal' : ('The Dreal Tool' , 'arith-devel@soc.lip6.fr'), + 'graal' : ('The Graal Tool' , 'arith-devel@soc.lip6.fr'), + 'lynx' : ('The Lynx Tool' , 'arith-devel@soc.lip6.fr'), + 'outil' : ('The Generic Tool' , 'arith-devel@soc.lip6.fr'), + 'rds' : ('The RDS Tool' , 'arith-devel@soc.lip6.fr'), + 'simcity' : ('The Simcity Tool' , 'arith-devel@soc.lip6.fr'), + 'syf' : ('The Syf Tool' , 'arith-devel@soc.lip6.fr'), + + 'ac' : ('Forgotten Author (ac)' , 'arith-devel@soc.lip6.fr'), + 'ana' : ('Forgotten Author (ana)' , 'arith-devel@soc.lip6.fr'), + 'dea9527' : ('Forgotten Author (dea9527)', 'arith-devel@soc.lip6.fr'), + 'mai0009' : ('Forgotten Author (mai0009)', 'arith-devel@soc.lip6.fr'), + 'nagat' : ('Forgotten Author (nagat)' , 'arith-devel@soc.lip6.fr'), + 'olivier' : ('Forgotten Author (olivier)', 'arith-devel@soc.lip6.fr'), + 'uid809' : ('Forgotten Author (uid809)' , 'arith-devel@soc.lip6.fr'), + 'vancour' : ('Forgotten Author (vancour)', 'arith-devel@soc.lip6.fr'), + 'vincent' : ('Forgotten Author (vincent)', 'arith-devel@soc.lip6.fr'), + + # This one will be used for commits for which CVS doesn't record + # the original author, as explained above. + 'cvs2svn' : ('cvs2svn', 'arith-devel@soc.lip6.fr'), + } + +# This is the main option that causes cvs2svn to output to a +# "fastimport"-format dumpfile rather than to Subversion: +ctx.output_option = GitOutputOption( + # The file in which to write the git-fast-import stream that + # contains the changesets and branch/tag information: + 'cvs2svn-tmp/git-dump.dat', + + # The blobs will be written via the revision recorder, so in + # OutputPass we only have to emit references to the blob marks: + GitRevisionMarkWriter(), + + # Optional map from CVS author names to git author names: + author_transforms=author_transforms, + ) + +# Change this option to True to turn on profiling of cvs2svn (for +# debugging purposes): +run_options.profiling = False + + +# Should CVSItem -> Changeset database files be memory mapped? In +# some tests, using memory mapping speeded up the overall conversion +# by about 5%. But this option can cause the conversion to fail with +# an out of memory error if the conversion computer runs out of +# virtual address space (e.g., when running a very large conversion on +# a 32-bit operating system). Therefore it is disabled by default. +# Uncomment the following line to allow these database files to be +# memory mapped. +#changeset_database.use_mmap_for_cvs_item_to_changeset_table = True + +# Now set the project to be converted to git. cvs2svn only supports +# single-project conversions, so this method must only be called +# once: +run_options.set_project( + # The filesystem path to the part of the CVS repository (*not* a + # CVS working copy) that should be converted. This may be a + # subdirectory (i.e., a module) within a larger CVS repository. + r'/users/outil/arith/cvs', + + # A list of symbol transformations that can be used to rename + # symbols in this project. + symbol_transforms=[ + # Use IgnoreSymbolTransforms like the following to completely + # ignore symbols matching a regular expression when parsing + # the CVS repository, for example to avoid warnings about + # branches with two names and to choose the preferred name. + # It is *not* recommended to use this instead of + # ExcludeRegexpStrategyRule; though more efficient, + # IgnoreSymbolTransforms are less flexible and don't exclude + # branches correctly. The argument is a Python-style regular + # expression that has to match the *whole* CVS symbol name: + #IgnoreSymbolTransform(r'nightly-build-tag-.*') + + # RegexpSymbolTransforms transform symbols textually using a + # regular expression. The first argument is a Python regular + # expression pattern and the second is a replacement pattern. + # The pattern is matched against each symbol name. If it + # matches the whole symbol name, then the symbol name is + # replaced with the corresponding replacement text. The + # replacement can include substitution patterns (e.g., r'\1' + # or r'\g'). Typically you will want to use raw strings + # (strings with a preceding 'r', like shown in the examples) + # for the regexp and its replacement to avoid backslash + # substitution within those strings. + #RegexpSymbolTransform(r'release-(\d+)_(\d+)', + # r'release-\1.\2'), + #RegexpSymbolTransform(r'release-(\d+)_(\d+)_(\d+)', + # r'release-\1.\2.\3'), + + # Simple 1:1 character replacements can also be done. The + # following transform, which converts backslashes into forward + # slashes, should usually be included: + ReplaceSubstringsSymbolTransform('\\','/'), + + # This last rule eliminates leading, trailing, and repeated + # slashes within the output symbol names: + NormalizePathsSymbolTransform(), + ], + + # See the definition of global_symbol_strategy_rules above for a + # description of this option: + symbol_strategy_rules=global_symbol_strategy_rules, + ) + diff --git a/crlcore/doc/CMakeLists.txt b/crlcore/doc/CMakeLists.txt index eefee8b1..2d17b364 100644 --- a/crlcore/doc/CMakeLists.txt +++ b/crlcore/doc/CMakeLists.txt @@ -20,9 +20,9 @@ # ${output_dir}/README.pdf # DESTINATION ${latexInstallDir} ) # install ( DIRECTORY ${output_dir}/README DESTINATION ${htmlInstallDir} ) - install ( FILES general-index.html DESTINATION ${htmlInstallDir} RENAME index.html ) +# install ( FILES general-index.html DESTINATION ${htmlInstallDir} RENAME index.html ) IF(DOXYGEN_FOUND) add_subdirectory(crlcore) ENDIF(DOXYGEN_FOUND) -add_subdirectory(UsersGuide) +#add_subdirectory(UsersGuide) diff --git a/crlcore/doc/README.tex b/crlcore/doc/README.tex deleted file mode 100644 index 036b1a29..00000000 --- a/crlcore/doc/README.tex +++ /dev/null @@ -1,682 +0,0 @@ - - \documentclass[11pt]{article} - - \usepackage[T1]{fontenc} - %\usepackage{ucs} - \usepackage[utf8x]{inputenc} - \usepackage{palatino} - \usepackage{marvosym} - \usepackage{pifont} - \usepackage{xspace} - \usepackage{longtable} - \usepackage{array} - \usepackage{fancyhdr} - \usepackage[sf,bf]{titlesec} - \usepackage{titletoc} - \usepackage{float} - \usepackage[dvips]{graphicx} - %\usepackage[dvips]{color} - \usepackage{listings} - \usepackage[dvips]{hyperref} - %\usepackage[hyphens]{url} - %\usepackage{html} - \usepackage[paper=a4paper - ,headheight=30pt - ]{geometry} - %\usepackage{layouts} - - \newcommand{\key}[1]{\fbox{\textsf{#1}}} - \newcommand{\menu}[1]{\fbox{\textsf{\textbf{{#1}}}}} - - \newcommand {\crlWebUrl} [1] {http://asim.lip6.fr/recherche/coriolis/#1} - \newcommand {\crlFtpUrl} [1] {http://asim.lip6.fr/pub/coriolis/2.0/#1} - \newcommand {\alcFtpUrl} [1] {http://asim.lip6.fr/pub/alliance/distribution/5.0/#1} - \newcommand {\slSocSrpmsUrl}[1] {http://ftp.lip6.fr/pub/linux/distributions/slsoc/5x/i386/SLSoC/SRPMS/#1} - \newcommand {\slRpmsiUrl} [1] {http://ftp.lip6.fr/pub/linux/distributions/slsoc/5x/i386/i386/SL/#1} - \newcommand {\slRpmsxUrl} [1] {http://ftp.lip6.fr/pub/linux/distributions/slsoc/5x/x86\_64/x86\_64/SL/#1} - - \latexhtml{ - %% LaTeX specific code. - \newcommand{\xhref} [2]{\href{#2}{#1}} - \newcommand{\crlWebRef} [1]{\href{\crlWebUrl{#1}}{\texttt{\footnotesize #1}}} - \newcommand{\crlFtpRef} [1]{\href{\crlFtpUrl{#1}}{\texttt{\footnotesize #1}}} - \newcommand{\alcFtpRef} [1]{\href{\alcFtpUrl{#1}}{\texttt{\footnotesize #1}}} - \newcommand{\slSocSrpmsRef}[1]{\href{\slSocSrpmsUrl{#1}}{\texttt{\footnotesize #1}}} - \newcommand{\slRpmsiRef} [1]{\href{\slRpmsiUrl{#1}}{\texttt{\footnotesize #1}}} - \newcommand{\slRpmsxRef} [1]{\href{\slRpmsxUrl{#1}}{\texttt{\footnotesize #1}}} - }{ - %% LaTeX2HTML specific code. - \newcommand{\xhref} [2]{\htmladdnormallink{#1}{#2}} - \newcommand{\crlWebRef} [1]{\htmladdnormallink{#1}{\crlWebUrl{#1}}} - \newcommand{\crlFtpRef} [1]{\htmladdnormallink{#1}{\crlFtpUrl{#1}}} - \newcommand{\alcFtpRef} [1]{\htmladdnormallink{#1}{\alcFtpUrl{#1}}} - \newcommand{\slSocSrpmsRef}[1]{\htmladdnormallink{#1}{\slSocSrpmsUrl{#1}}} - \newcommand{\slRpmsiRef} [1]{\htmladdnormallink{#1}{\slRpmsiUrl{#1}}} - \newcommand{\slRpmsxRef} [1]{\htmladdnormallink{#1}{\slRpmsxUrl{#1}}} - } - - \newcommand {\Alexandre} {\textsc{Alexandre}\xspace} - \newcommand {\Belloeil} {\textsc{Belloeil}\xspace} - \newcommand {\Chu} {\textsc{Chu}\xspace} - \newcommand {\Chaput} {\textsc{Chaput}\xspace} - \newcommand {\Dupuis} {\textsc{Dupuis}\xspace} - \newcommand {\Escassut} {\textsc{Escassut}\xspace} - \newcommand {\Masson} {\textsc{Masson}\xspace} - \newcommand {\LIP} {\textsc{lip6}\xspace} - \newcommand {\SoC} {\textsc{S}o\textsc{C}\xspace} - - \newcommand {\LGPL} {\textsc{lgpl}\xspace} - \newcommand {\GPL} {\textsc{gpl}\xspace} - \newcommand {\ANSI} {\textsc{ansi}\xspace} - \newcommand {\XML} {\textsc{xml}\xspace} - \newcommand {\VHDL} {\textsc{vhdl}\xspace} - \newcommand {\FEL} {\xhref{\textsc{fel}}{http://spins.fedoraproject.org/fel/}\xspace} - \newcommand {\SiII} {\xhref{\textsc{Si2}}{http://www.si2.org/}\xspace} - \newcommand {\Bull} {\xhref{\textsc{Bull}}{http://www.bull.com/}\xspace} - \newcommand {\UPMC} {\xhref{\textsc{upmc}}{http://www.upmc.fr/}\xspace} - \newcommand {\Cadence} {\xhref{\textsc{Cadence}}{http://www.cadence.com/}\xspace} - \newcommand {\LEFDEF} {\textsc{lef/def}\xspace} - \newcommand {\RHELV} {\textsc{rhel 5}\xspace} - \newcommand {\CentOSV} {\textsc{CentOS 5}\xspace} - \newcommand {\SLV} {\textsc{SL 5}\xspace} - \newcommand {\Fedora} {\textsc{Fedora}\xspace} - \newcommand {\FedoraXII} {\textsc{Fedora 12}\xspace} - \newcommand {\FedoraXIII} {\textsc{Fedora 13}\xspace} - \newcommand {\Karmik} {\textsc{Ubuntu Karmik}\xspace} - \newcommand {\Lucid} {\textsc{Ubuntu Lucid}\xspace} - \newcommand {\QtIV} {\textsc{Qt 4}\xspace} - \newcommand {\rpm} {\texttt{rpm}\xspace} - \newcommand {\alien} {\texttt{alien}\xspace} - \newcommand {\boost} {\texttt{boost}\xspace} - \newcommand {\tty} {\texttt{tty}\xspace} - \newcommand {\BoxRouter} {\textsc{BoxRouter}\xspace} - \newcommand {\BoxRouterRef} {\xhref{\BoxRouter}% - {http://www.cerc.utexas.edu/~thyeros/boxrouter/boxrouter.htm}\xspace} - \newcommand {\Flute} {\textsc{Flute}\xspace} - \newcommand {\FluteRef} {\xhref{http://home.eng.iastate.edu/\~{}cnchu/}% - {http://home.eng.iastate.edu/~cnchu/}\xspace} - \newcommand {\netlist} {\textit{netlist}\xspace} - \newcommand {\physical} {\textit{physical}\xspace} - \newcommand {\logical} {\textit{logical}\xspace} - - \newcommand {\Alliance} {\textsc{Alliance}\xspace} - \newcommand {\MBK} {\textsc{mbk}\xspace} - \newcommand {\SxLib} {\texttt{SxLib}\xspace} - \newcommand {\Nero} {\texttt{Nero}\xspace} - \newcommand {\vst} {\texttt{vst}\xspace} - \newcommand {\ap} {\texttt{ap}\xspace} - \newcommand {\PHFIG} {\texttt{PHFIG}\xspace} - \newcommand {\LOFIG} {\texttt{LOFIG}\xspace} - - \newcommand {\Coriolis} {\textsc{Coriolis}\xspace} - \newcommand {\CoriolisI} {\textsc{Coriolis 1}\xspace} - \newcommand {\CoriolisII} {\textsc{Coriolis 2}\xspace} - \newcommand {\Hurricane} {\textsc{Hurricane}\xspace} - \newcommand {\Stratus} {\texttt{Status}\xspace} - \newcommand {\GenLib} {\texttt{GenLib}\xspace} - \newcommand {\Mauka} {\texttt{Mauka}\xspace} - \newcommand {\Knik} {\texttt{Knik}\xspace} - \newcommand {\Kite} {\texttt{Kite}\xspace} - \newcommand {\Viewer} {\texttt{Viewer}\xspace} - \newcommand {\kgr} {\texttt{kgr}\xspace} - \newcommand {\cgt} {\texttt{cgt}\xspace} - \newcommand {\CELLTOP} {\texttt{CELL\_TOP}\xspace} - \newcommand {\confcoriolisIIalc} {\texttt{/etc/coriolis2/environment.alliance.xml}\xspace} - \newcommand {\usercoriolisIIalc} {\texttt{.environment.alliance.xml}\xspace} - \newcommand {\Cell} {\texttt{Cell}\xspace} - \newcommand {\POWER} {\texttt{POWER}\xspace} - \newcommand {\GROUND} {\texttt{GROUND}\xspace} - \newcommand {\MII} {\texttt{M2}\xspace} - \newcommand {\MV} {\texttt{M5}\xspace} - - \newcommand {\knikThesis}% - {\xhref{\texttt{http://www-soc.lip6.fr/en/users/damiendupuis/PhD/}}% - {http://www-soc.lip6.fr/en/users/damiendupuis/PhD/}\xspace} - - \newcommand {\coriolisIIfcXIIIirpm}{\crlFtpRef{coriolis2-1.0.1963-1.fc13.i686.rpm}\xspace} - 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\newcommand {\keyLEFT} {\key{LEFT}\xspace} - \newcommand {\keyRIGHT} {\key{RIGHT}\xspace} - \newcommand {\keyCTRL} {\key{CTRL}\xspace} - \newcommand {\keyESC} {\key{ESC}\xspace} - \newcommand {\keyf} {\key{f}\xspace} - \newcommand {\keyG} {\key{G}\xspace} - \newcommand {\keyI} {\key{I}\xspace} - \newcommand {\keyL} {\key{L}\xspace} - \newcommand {\keym} {\key{m}\xspace} - \newcommand {\keyk} {\key{k}\xspace} - \newcommand {\keyK} {\key{K}\xspace} - \newcommand {\keyO} {\key{O}\xspace} - \newcommand {\keyP} {\key{P}\xspace} - \newcommand {\keyQ} {\key{Q}\xspace} - \newcommand {\keys} {\key{s}\xspace} - \newcommand {\keyW} {\key{W}\xspace} - \newcommand {\keyS} {\key{S}\xspace} - \newcommand {\keyz} {\key{z}\xspace} - \newcommand {\keyPlus} {$+$\xspace} - \newcommand {\BigMouse} {{\Huge \ComputerMouse}\xspace} - }{ %% HTML version. - \newcommand {\keyUP} {\includegraphics{images/key_UP}\xspace} - \newcommand {\keyDOWN} {\includegraphics{images/key_DOWN}\xspace} - \newcommand {\keyLEFT} {\includegraphics{images/key_LEFT}\xspace} - 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\newcommand {\keyz} {\includegraphics{images/key_Z}\xspace} - \newcommand {\keyPlus} {\includegraphics{images/key_PLUS}\xspace} - \newcommand {\BigMouse} {\includegraphics[scale=.4]{images/ComputerMouse}\xspace} - } - - %\setlength {\parskip} {4mm} - %\setlength {\itemsep} {4mm} - - \pagestyle{fancy} - - %\renewcommand{\headheight}{14pt} - \renewcommand{\headrulewidth}{0.2mm} - \renewcommand{\footrulewidth}{0.2mm} - \renewcommand{\sectionmark}[1]{\markboth{\thesection\ #1}{\thesection\ #1}} - \renewcommand{\subsectionmark}[1]{} - \lhead[]{Coriolis 2} - \rhead[]{May 20, 2010} - \lfoot[]{\LIP/\SoC} - \rfoot[]{\thepage} - \cfoot[]{} - - %% The LaTeX Companion -- p. 204. - %% Miniature display of the page layout. - %\newcommand{\showpage}{% - % \setlayoutscale{0.65}\setlabelfont{\tiny}% - % \printheadingsfalse\printparametersfalse% - % \currentpage\pagedesign% - %} - - \titlecontents{section}[1pc] - {\sffamily\bfseries} % above code. - {\contentslabel{1pc}} % numbered entry format. - {The Numberless Entry Format} % numberless entry format. - {\titlerule*[8pt]{.}\textsc{\textbf{{\contentspage}}}} % page format. - \titlecontents{subsection}[3pc] - {\sffamily} % above code. - {\contentslabel{2pc}} % numbered entry format. - {The Numberless Entry Format} % numberless entry format. - {\titlerule*[8pt]{.}\textsc{\textbf{{\contentspage}}}} % page format. - - - \begin{document} - - \title{\CoriolisII} - \author{The Coriolis Team} - \date{April 2011} - - \maketitle - - \thispagestyle{fancy} - - \tableofcontents - - \section{Credits \& Licenses} - - \begin{center} - \Hurricane \dotfill\ Rémy \Escassut \& Christian \Masson \\ - \Mauka \dotfill\ Christophe \Alexandre \\ - \Stratus \dotfill Sophie \Belloeil \\ - \Knik \dotfill\ Damien \Dupuis \\ - \Kite, \Viewer \dotfill\ Jean-Paul \Chaput \\ - \end{center} - - The \Hurricane data-base is copyright\textcopyright\ \Bull 2000-2010 and is - released under the terms of the \LGPL license. All other tools are - copyright\textcopyright\ \UPMC 2008-2010 and released under the \GPL - license. - - The \Knik router makes use of the \Flute software, which is - copyright\textcopyright\ Chris C. N. \Chu from the Iowa State University - (\FluteRef). - - \newpage - - - \section{Release Notes} - - \subsection{Release 1.0.1475} - - This is the first preliminary release of the \CoriolisII framework. - - This release mainly ships the global router \Knik and the detailed router - \Kite. Together they aim to replace the \Alliance \Nero router. - Unlike \Nero, \Kite is based on an innovating routing modeling and ad-hoc - algorithm. Although it is released under \GPL license, the source code - will be avalaible later. - \medskip - - \noindent Contents of this release: - \begin{enumerate} - \item A graphical user interface (viewer only). - \item The \Knik global router. - \item The \Kite detailed router. - \end{enumerate} - - \noindent Supported input/output formats: - \begin{itemize} - \item \Alliance \vst (netlist) \& \ap (physical) formats. - \item Even if there are some references to the \Cadence \LEFDEF format, its - support is not included because it depends on a library only available - to \SiII affiliated members. - \end{itemize} - - \subsection{Release 1.0.1963} - - Release 1963 is alpha. All the tools from \CoriolisI have been ported into - this release. - - \noindent Contents of this release: - \begin{enumerate} - \item The \Stratus netlist capture language (\GenLib replacement). - \item The \Mauka placer (still contains bugs). - \item A graphical user interface (viewer only). - \item The \Knik global router. - \item The \Kite detailed router. - \item Partially implemented python support for configuration files - (alternative to \XML). - \item A documentation (imcomplete/obsoleted in \Hurricane's case). - \end{enumerate} - - \section{Installation} - - Binary \rpm packages avalaible: - \begin{center} - \begin{tabular}{|c|l|} - \hline - \FedoraXIII & \coriolisIIfcXIIIirpm \\ - & \coriolisIIfcXIIIxrpm \\ - \hline - \FedoraXII & \coriolisIIfcXIIirpm \\ - & \coriolisIIfcXIIxrpm \\ - \hline - \RHELV & \coriolisIIslVirpm \\ - \CentOSV & \coriolisIIslVxrpm \\ - \SLV & \\ - \hline - \Lucid & \coriolisIILucidideb \\ - & \coriolisIILucidxdeb \\ - \hline - \end{tabular} - \end{center} - - \noindent\textbf{Note:}\ The \Lucid packages have not beeing natively - compiled but converted from \Fedora with \alien, they might not work as - well as under \Fedora. As they uses slightly different versions of \boost, - you have to create the following link~: - \begin{verbatim} - > sudo ln -s /usr/lib/libboost_program_options.so.1.40.0 \ - /usr/lib/libboost_program_options-mt.so.1.41.0 - \end{verbatim} - - \newpage - - For \RHELV based distributions, additionnal \QtIV packages are needed: - - \begin{center} - \begin{tabular}{|l|l|} - \hline - \multicolumn{2}{|l|}{\qtIVsrpm} \\ - \hline - \hline - \qtIVirpm & \qtIVxrpm \\ - \qtIVdevelirpm & \qtIVdevelxrpm \\ - \qtIVdocirpm & \qtIVdocxrpm \\ - \qtIVmysqlirpm & \qtIVmysqlxrpm \\ - \qtIVodbcirpm & \qtIVodbcxrpm \\ - \qtIVpostgresqlirpm & \qtIVpostgresqlxrpm \\ - \qtIVxXIirpm & \qtIVxXIxrpm \\ - \hline - \end{tabular} - \end{center} - - \section{Configuration} - - Configuration of \CoriolisII no longer depends on environment variables. - All pathes and options are sets through \XML configuration files. The main - configuration file is~: - \begin{center} - \confcoriolisIIalc - \end{center} - Contents of this file should be familiar to all thoses already acquainted - with \Alliance as the \XML node names takes back former shell environment - variables. - - You may want to customize \CELLTOP to point to the directory where the \Alliance cells - libraries are installed (\texttt{/usr/share/alliance}\ if you installed - the \Alliance package from \FEL. - - All system settings can be overwritten by a \usercoriolisIIalc file in the - user's root directory. - - - \section{Tools} - - \subsection{The \Hurricane Data-Base} - - The \Alliance flow is based on the \MBK data-base, which has one data-structure - for each view. That is, \LOFIG for the \logical view and \PHFIG for the \physical - view. The place and route tools were responsible for maintaining (or not) the - coherency between views. Reflecting this weak coupling between views, each one - was stored in a separate file with a specific format. The \logical view is stored - in a \vst file in \VHDL format and the \physical in an \ap file in an ad-hoc format. - - The \Coriolis flow is based on the \Hurricane data-base, which has a unified - structure for \logical and \physical view. That data structure is the \Cell object. - The \Cell can have any state between pure netlist and completly placed and - routed design. Although the memory representation of the views has deeply - changed we still use the \Alliance files format, but they now really represent - views of the same object. The point is that one must be very careful about - view coherency when going to and from \Coriolis. - - \newpage - - As for the first release, \Coriolis can be used only for two purposes~: - \begin{itemize} - \item \textbf{Routing a design}\xspace, in that case the \netlist\xspace - view and the \physical view must be present and \physical view must contain - a placement. Both views must have the same name. When saving the routed design, - it is advised to change the design name otherwise the original unrouted placement - in the \physical view will be overwritten. - \item \textbf{Viewing a design}, the \logical view must be present, if a \physical - view is present it still must have the same name but it can be in any - state. - \end{itemize} - - - \subsection{Knik -- Global Router} - - The global router is (not yet) deterministic. To circumvent this limitation, - a global routing (also called a ``solution'') can be saved to disk and reloaded - for later uses. - - A global routing is saved into a file with the same name as the design and a - \kgr extention. It is in \BoxRouterRef output format. - - For an in-depth description of \Knik algorithms, you may download the thesis of - D. \Dupuis avalaible from here~: - \begin{center}\knikThesis\end{center} - - \noindent Menus~: - \begin{itemize} - \item - \latexhtml{\menu{P\&R}$\rightarrow$\menu{\underline{S}tep by Step} - $\rightarrow$\menu{Kite -- \underline{S}ave Global Routing}} - {\includegraphics{images/PR-SBS-SaveGlobal}} - \item - \latexhtml{\menu{P\&R}$\rightarrow$\menu{\underline{S}tep by Step} - $\rightarrow$\menu{Kite -- \underline{L}oad Global Routing}} - {\includegraphics{images/PR-SBS-LoadGlobal}} - \end{itemize} - - - \subsection{Kite -- Detailed Router} - - \Kite no longer suffers from the limitations of \Nero. It can route big designs - as its runtime and memory footprint is almost linear (with respect to the number - of gates). It has successfully routed design of more than \texttt{150K}\ gates. - - \medskip\noindent - However, this first release has the following restrictions: - \begin{itemize} - \item Works only with \SxLib standard cell gauge. - \item Works always with 4 routing metal layers (\MII through \MV). - \item Do not allow (take into account) pre-routed wires on signals - other than \POWER or \GROUND. - \end{itemize} - - After each run, \Kite displays a set of \textit{completion ratios}\ which must all - be equal to \textsf{100\%}\ if the detailed routing has been successfull. - In the event of a failure, on saturated design, you may decrease the \textit{edge - saturation ration} (argument \texttt{--edge}) to balance more evenly the design - saturation. That is, the maximum saturation decrease at the price of a wider - saturated area and increased wirelength. - - - \newpage - - \medskip\noindent - Routing a design is done in three ordered steps~: - \begin{enumerate} - \item Global routing - \latexhtml{\menu{P\&R}$\rightarrow$\menu{Kite -- \underline{G}lobal Route}} - {\includegraphics{images/PR-GlobalRoute}} - \item Detailed routing - \latexhtml{\menu{P\&R}$\rightarrow$\menu{Kite -- \underline{D}etailed Route}} - {\includegraphics{images/PR-DetailedRoute}} - \item Finalize routing - \latexhtml{\menu{P\&R}$\rightarrow$\menu{Kite -- \underline{F}inalize Route}} - {\includegraphics{images/PR-FinalizeRoute}} - \end{enumerate} - After the detailed routing step the \Kite data-structure is still active. - The wiring is thus represented in a way that allows \Kite to manage it but - which is not completly finished. The finalize step performs the removal of - the \Kite data-structure and finish/cleanup the wiring so that its - connex in the sense of \Hurricane. \textit{Do not}\xspace try to save - your design before that step, you would get gaps in it. - - - \subsection{Viewer Small Memento} - - The main application binary is \cgt. - - \begin{center} - \newlength{\keyheight} \settoheight{\keyheight}{\keyUP} \addtolength{\keyheight}{5pt} - \newlength{\keydepth} \settodepth {\keydepth} {\keyUP} \addtolength{\keydepth} {5pt} - - \newcommand{\keytabpar}[1]{\parbox[t]{.2\textwidth}{\rule{0pt}{\keyheight} \centering #1 \rule[-\keydepth]{0pt}{0pt}}} - \newcommand{\sfbf}[1]{\textsf{\textbf{#1}}} - - \begin{longtable}{|c|c|p{.55\textwidth}|} - \endfirsthead - \hline - \endhead - \hline - \endfoot - \endlastfoot - \hline - \sfbf{Moves} - & \keytabpar{\keyUP \keyDOWN \\ \keyLEFT \keyRIGHT} - & Shift the view \\ - \hline - \sfbf{Fit} - & \keytabpar{\keyf} - & Fit contents to window \\ - \hline - \sfbf{Refresh} - & \keytabpar{\keyCTRL\keyPlus\keyL} - & Triggers a complete display redraw \\ - \hline - \sfbf{Goto} - & \keytabpar{\keyG} - & \texttt{aperture} is the minimum side of the area displayed around - the point to go to. It's an alternative way of setting the zoom level \\ - \hline - \sfbf{Zoom} - & \keytabpar{\keyz \keym} - & \keyz zoom by 2, \keym unzoom by 2 \\ - \cline{2-3} - & \keytabpar{\BigMouse \\ \texttt{Area Zoom}} - & You can perform a zoom to an area. - Define the zoom area by \textit{holding down the left mouse button}\ - while moving the mouse. \\ - \hline - \sfbf{Selection} - & \keytabpar{\BigMouse \\ \texttt{Area Selection}} - & You can select displayed object under an area. Define the selection area - by \textit{holding down the right mouse button}\ while moving the mouse. \\ - \cline{2-3} - & \keytabpar{\BigMouse \\ \texttt{Toggle Selection}} - & You can toggle the selection of one object under the mouse position by - pressing \keyCTRL and pressing down \textit{the right mouse button}. - A popup list of what's under the position shows up into which you can - toggle the selection state of one item. \\ - \cline{2-3} - & \keytabpar{\keys} - & Toggle the selection visibility \\ - \hline - \sfbf{Controller} - & \keytabpar{\keyCTRL\keyPlus\keyI} - & Show/hide the controller window. - - It's the Swiss Army Knife of the viewer. From it, you can fine-control - the display and inspect almost everything in your design. \\ - \hline - \sfbf{Rulers} - & \keytabpar{\keyk \\ \keyESC} - & One stroke on \keyk enters the ruler mode, in which you can draw one - ruler. You can exit the ruler mode by pressing \keyESC. - Once in ruler mode, the first click on the \textit{left mouse button} - sets the ruler's starting point and the second click the ruler's end - point. The second click exits automatically the ruler mode. \\ - \cline{2-3} - & \keytabpar{\keyK} - & Clears all the drawn rulers \\ - \hline - \sfbf{Print} - & \keytabpar{\keyCTRL\keyPlus\keyP} - & Currently rather crude. It's a direct copy of what's displayed in pixels. - So the resulting picture will be a little blurred due to anti-aliasing - mechanism. \\ - \hline - \sfbf{Open/Close} - & \keytabpar{\keyCTRL\keyPlus\keyO} - & Opens a new design. The design name must be given without path or extention. \\ - \cline{2-3} - & \keytabpar{\keyCTRL\keyPlus\keyW} - & Close the current viewer window, but do not quit the application. \\ - \cline{2-3} - & \keytabpar{\keyCTRL\keyPlus\keyQ} - & CTRL+Q quit the application (closing all windows). \\ - \hline - \sfbf{Hierarchy} - & \keytabpar{\keyCTRL\keyPlus\keyDOWN} - & Go one hierarchy level down. That is, if there is an \textit{instance}\ under - the cursor position, load it's \textit{model}\ (\Cell) in place of the current one. \\ - \cline{2-3} - & \keytabpar{\keyCTRL\keyPlus\keyUP} - & Go one hierarchy level up. if we have entered the current model through - \keyCTRL\keyPlus\keyDOWN, reload the previous model (the one in which this model is - instanciated). \\ - \latex{\hline} - \end{longtable} - \end{center} - - \newpage - - \subsection{Running \cgt in text mode} - - \begin{center} - \begin{longtable}{|c|p{.55\textwidth}|} - \hline - \textbf{Argument} & Meaning \\ - \latex{\hline} - \hline - \endfirsthead - \hline - \textbf{Argument} & Meaning \\ - \latex{\hline} - \hline - \endhead - \hline - \endfoot - \endlastfoot - \latex{\hline} - \texttt{-t|--text} - & Instruct \cgt to run in text mode. \\ - \hline - \texttt{-L|--log-mode} - & Disable the uses of \ANSI escape sequence on the \tty. Useful when - the output is redirected to a file. \\ - \hline - \texttt{-c|--cell=} - & The name of the design to load, without leading path or - extention. \\ - \hline - \texttt{-g|--load-global} - & Reload a global routing solution from disk. \linebreak - The file containing the solution must be named \texttt{.kgr}. \\ - \hline - \texttt{--save-global} - & Save the global routing solution, into a file named \texttt{.kgr}. \\ - \hline - \texttt{--edge|-e } - & Change the edge capacity for the global router, between 0 and 1 (\Knik). \\ - \hline - \texttt{--global-route|-G} - & Run the global router (\Knik). \\ - \hline - \texttt{--detailed-route|-R} - & Run the detailed router (\Kite). \\ - \hline - \multicolumn{2}{|l|}{\texttt{-s|--save-design=}} \\ - \cline{1-1} - & The design into which the routed layout will be saved. It is strongly - recommanded to choose a different name from the source (unrouted) - design. \\ - \hline - \texttt{--events-limit=} - & The maximal number of events after which the router will stops. This is - mainly a failsafe against looping. The limit is sets to 4 millions of - iteration which should suffice to any design of \texttt{100K}\xspace - gates. For bigger designs you may wants to increase this limit. \\ - \latex{\hline} - \end{longtable} - \end{center} - - \noindent - Some examples~: - \begin{itemize} - \item Run both global and detailed router, then save the routed design~: \\ - \texttt{> cgt -v -t -G -R --cell=design --save-design=design\_kite} - \item Load a previous global solution, run the detailed router, then save the - routed design~: \\ - \texttt{> cgt -v -t --load-global -R --cell=design --save-design=design\_kite} - \item Run the global router, then save the global routing solution~: \\ - \texttt{> cgt -v -t -G --save-global --cell=design} - \end{itemize} - - - \end{document} diff --git a/crlcore/doc/SoC.css b/crlcore/doc/SoC.css deleted file mode 100644 index 276a7c09..00000000 --- a/crlcore/doc/SoC.css +++ /dev/null @@ -1,559 +0,0 @@ - - -/* - * +-----------------------------------------------------------------+ - * | HTML Standart Tags | - * +-----------------------------------------------------------------+ - */ - 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3000 2025 P&R\001 --6 -2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 - 1 1 1.00 90.00 180.00 - 3300 1950 3600 1950 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 3600 1800 5700 1800 5700 2100 3600 2100 3600 1800 -4 1 0 50 -1 18 11 0.0000 4 135 1860 4650 2025 Kite - Detailed Route\001 diff --git a/crlcore/doc/images/PR-DetailedRoute.png b/crlcore/doc/images/PR-DetailedRoute.png deleted file mode 100644 index 97fef303..00000000 Binary files a/crlcore/doc/images/PR-DetailedRoute.png and /dev/null differ diff --git a/crlcore/doc/images/PR-FinalizeRoute.fig b/crlcore/doc/images/PR-FinalizeRoute.fig deleted file mode 100644 index ce28e67b..00000000 --- a/crlcore/doc/images/PR-FinalizeRoute.fig +++ /dev/null @@ -1,20 +0,0 @@ -#FIG 3.2 Produced by xfig version 3.2.5b -Landscape -Center -Inches -Letter -100.00 -Single --2 -1200 2 -6 2700 1800 3300 2100 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 2700 1800 3300 1800 3300 2100 2700 2100 2700 1800 -4 1 0 50 -1 18 11 0.0000 4 135 390 3000 2025 P&R\001 --6 -2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 - 1 1 1.00 90.00 180.00 - 3300 1950 3600 1950 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 3600 1800 5700 1800 5700 2100 3600 2100 3600 1800 -4 1 0 50 -1 18 11 0.0000 4 135 1785 4650 2025 Kite - Finalize Route\001 diff --git a/crlcore/doc/images/PR-FinalizeRoute.png b/crlcore/doc/images/PR-FinalizeRoute.png deleted file mode 100644 index bade52db..00000000 Binary files a/crlcore/doc/images/PR-FinalizeRoute.png and /dev/null differ diff --git a/crlcore/doc/images/PR-GlobalRoute.fig b/crlcore/doc/images/PR-GlobalRoute.fig deleted file mode 100644 index b9a852a7..00000000 --- a/crlcore/doc/images/PR-GlobalRoute.fig +++ /dev/null @@ -1,20 +0,0 @@ -#FIG 3.2 Produced by xfig version 3.2.5b -Landscape -Center -Inches -Letter -100.00 -Single --2 -1200 2 -6 2700 1800 3300 2100 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 2700 1800 3300 1800 3300 2100 2700 2100 2700 1800 -4 1 0 50 -1 18 11 0.0000 4 135 390 3000 2025 P&R\001 --6 -2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 - 1 1 1.00 90.00 180.00 - 3300 1950 3600 1950 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 3600 1800 5475 1800 5475 2100 3600 2100 3600 1800 -4 1 0 50 -1 18 11 0.0000 4 135 1695 4575 2025 Kite - Global Route\001 diff --git a/crlcore/doc/images/PR-GlobalRoute.png b/crlcore/doc/images/PR-GlobalRoute.png deleted file mode 100644 index 26d12d73..00000000 Binary files a/crlcore/doc/images/PR-GlobalRoute.png and /dev/null differ diff --git a/crlcore/doc/images/PR-SBS-LoadGlobal.fig b/crlcore/doc/images/PR-SBS-LoadGlobal.fig deleted file mode 100644 index 624e9df2..00000000 --- a/crlcore/doc/images/PR-SBS-LoadGlobal.fig +++ /dev/null @@ -1,28 +0,0 @@ -#FIG 3.2 Produced by xfig version 3.2.5b -Landscape -Center -Inches -Letter -100.00 -Single --2 -1200 2 -6 2700 1800 3300 2100 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 2700 1800 3300 1800 3300 2100 2700 2100 2700 1800 -4 1 0 50 -1 18 11 0.0000 4 135 390 3000 2025 P&R\001 --6 -6 3600 1800 4950 2100 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 3600 1800 4950 1800 4950 2100 3600 2100 3600 1800 -4 1 0 50 -1 18 11 0.0000 4 180 1185 4275 2025 Step by Step\001 --6 -2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 - 1 1 1.00 90.00 180.00 - 3300 1950 3600 1950 -2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 - 1 1 1.00 90.00 180.00 - 4950 1950 5250 1950 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 5250 1800 7800 1800 7800 2100 5250 2100 5250 1800 -4 1 0 50 -1 18 11 0.0000 4 180 2325 6525 2025 Kite - Load Global Routing\001 diff --git a/crlcore/doc/images/PR-SBS-LoadGlobal.png b/crlcore/doc/images/PR-SBS-LoadGlobal.png deleted file mode 100644 index ca90276c..00000000 Binary files a/crlcore/doc/images/PR-SBS-LoadGlobal.png and /dev/null differ diff --git a/crlcore/doc/images/PR-SBS-SaveGlobal.fig b/crlcore/doc/images/PR-SBS-SaveGlobal.fig deleted file mode 100644 index 9427c85c..00000000 --- a/crlcore/doc/images/PR-SBS-SaveGlobal.fig +++ /dev/null @@ -1,30 +0,0 @@ -#FIG 3.2 Produced by xfig version 3.2.5b -Landscape -Center -Inches -Letter -100.00 -Single --2 -1200 2 -6 2700 1800 3300 2100 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 2700 1800 3300 1800 3300 2100 2700 2100 2700 1800 -4 1 0 50 -1 18 11 0.0000 4 135 390 3000 2025 P&R\001 --6 -6 3600 1800 4950 2100 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 3600 1800 4950 1800 4950 2100 3600 2100 3600 1800 -4 1 0 50 -1 18 11 0.0000 4 180 1185 4275 2025 Step by Step\001 --6 -6 5250 1800 7800 2100 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 5250 1800 7800 1800 7800 2100 5250 2100 5250 1800 -4 1 0 50 -1 18 11 0.0000 4 180 2370 6525 2025 Kite - Save Global Routing\001 --6 -2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 - 1 1 1.00 90.00 180.00 - 3300 1950 3600 1950 -2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 - 1 1 1.00 90.00 180.00 - 4950 1950 5250 1950 diff --git a/crlcore/doc/images/PR-SBS-SaveGlobal.png b/crlcore/doc/images/PR-SBS-SaveGlobal.png deleted file mode 100644 index 5befad44..00000000 Binary files a/crlcore/doc/images/PR-SBS-SaveGlobal.png and /dev/null differ diff --git a/crlcore/doc/images/key_CTRL.fig b/crlcore/doc/images/key_CTRL.fig deleted file mode 100644 index 91e3dee5..00000000 --- a/crlcore/doc/images/key_CTRL.fig +++ /dev/null @@ -1,12 +0,0 @@ -#FIG 3.2 Produced by xfig version 3.2.5b -Landscape -Center -Inches -Letter -100.00 -Single --2 -1200 2 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 2700 1800 3300 1800 3300 2100 2700 2100 2700 1800 -4 1 0 50 -1 18 11 0.0000 4 135 480 3000 2025 CTRL\001 diff --git a/crlcore/doc/images/key_CTRL.png b/crlcore/doc/images/key_CTRL.png deleted file mode 100644 index 7d20a23d..00000000 Binary files a/crlcore/doc/images/key_CTRL.png and /dev/null differ diff --git a/crlcore/doc/images/key_DOWN.fig b/crlcore/doc/images/key_DOWN.fig deleted file mode 100644 index f9014128..00000000 --- a/crlcore/doc/images/key_DOWN.fig +++ /dev/null @@ -1,12 +0,0 @@ -#FIG 3.2 Produced by xfig version 3.2.5b -Landscape -Center -Inches -Letter -100.00 -Single --2 -1200 2 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 2625 1800 3375 1800 3375 2100 2625 2100 2625 1800 -4 1 0 50 -1 18 11 0.0000 4 135 570 3000 2025 DOWN\001 diff --git a/crlcore/doc/images/key_DOWN.png b/crlcore/doc/images/key_DOWN.png deleted file mode 100644 index f5e55226..00000000 Binary files a/crlcore/doc/images/key_DOWN.png and /dev/null differ diff --git a/crlcore/doc/images/key_ESC.fig b/crlcore/doc/images/key_ESC.fig deleted file mode 100644 index af0f6f87..00000000 --- a/crlcore/doc/images/key_ESC.fig +++ /dev/null @@ -1,12 +0,0 @@ -#FIG 3.2 Produced by xfig version 3.2.5b -Landscape -Center -Inches -Letter -100.00 -Single --2 -1200 2 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 2775 1800 3225 1800 3225 2100 2775 2100 2775 1800 -4 1 0 50 -1 18 11 0.0000 4 135 375 3000 2025 ESC\001 diff --git a/crlcore/doc/images/key_ESC.png b/crlcore/doc/images/key_ESC.png deleted file mode 100644 index ef08e857..00000000 Binary files a/crlcore/doc/images/key_ESC.png and /dev/null differ diff --git a/crlcore/doc/images/key_F.fig b/crlcore/doc/images/key_F.fig deleted file mode 100644 index 0a784eea..00000000 --- a/crlcore/doc/images/key_F.fig +++ /dev/null @@ -1,12 +0,0 @@ -#FIG 3.2 Produced by xfig version 3.2.5b -Landscape -Center -Inches -Letter -100.00 -Single --2 -1200 2 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 2850 1800 3150 1800 3150 2100 2850 2100 2850 1800 -4 1 0 50 -1 14 18 0.0000 4 150 105 3000 2025 f\001 diff --git a/crlcore/doc/images/key_F.png b/crlcore/doc/images/key_F.png deleted file mode 100644 index 345c256d..00000000 Binary files a/crlcore/doc/images/key_F.png and /dev/null differ diff --git a/crlcore/doc/images/key_Gcap.fig b/crlcore/doc/images/key_Gcap.fig deleted file mode 100644 index 89eba5c4..00000000 --- a/crlcore/doc/images/key_Gcap.fig +++ /dev/null @@ -1,12 +0,0 @@ -#FIG 3.2 Produced by xfig version 3.2.5b -Landscape -Center -Inches -Letter -100.00 -Single --2 -1200 2 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 2850 1800 3150 1800 3150 2100 2850 2100 2850 1800 -4 1 0 50 -1 14 18 0.0000 4 150 105 3000 2025 G\001 diff --git a/crlcore/doc/images/key_Gcap.png b/crlcore/doc/images/key_Gcap.png deleted file mode 100644 index 8e02a836..00000000 Binary files a/crlcore/doc/images/key_Gcap.png and /dev/null differ diff --git a/crlcore/doc/images/key_Icap.fig b/crlcore/doc/images/key_Icap.fig deleted file mode 100644 index 0a902821..00000000 --- a/crlcore/doc/images/key_Icap.fig +++ /dev/null @@ -1,12 +0,0 @@ -#FIG 3.2 Produced by xfig version 3.2.5b -Landscape -Center -Inches -Letter -100.00 -Single --2 -1200 2 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 2850 1800 3150 1800 3150 2100 2850 2100 2850 1800 -4 1 0 50 -1 14 18 0.0000 4 150 105 3000 2025 I\001 diff --git a/crlcore/doc/images/key_Icap.png b/crlcore/doc/images/key_Icap.png deleted file mode 100644 index 8d16346f..00000000 Binary files a/crlcore/doc/images/key_Icap.png and /dev/null differ diff --git a/crlcore/doc/images/key_K.fig b/crlcore/doc/images/key_K.fig deleted file mode 100644 index cbceda59..00000000 --- a/crlcore/doc/images/key_K.fig +++ /dev/null @@ -1,12 +0,0 @@ -#FIG 3.2 Produced by xfig version 3.2.5b -Landscape -Center -Inches -Letter -100.00 -Single --2 -1200 2 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 2850 1800 3150 1800 3150 2100 2850 2100 2850 1800 -4 1 0 50 -1 14 18 0.0000 4 150 105 3000 2025 k\001 diff --git a/crlcore/doc/images/key_K.png b/crlcore/doc/images/key_K.png deleted file mode 100644 index 95984ed0..00000000 Binary files a/crlcore/doc/images/key_K.png and /dev/null differ diff --git a/crlcore/doc/images/key_Kcap.fig b/crlcore/doc/images/key_Kcap.fig deleted file mode 100644 index ee903bd6..00000000 --- a/crlcore/doc/images/key_Kcap.fig +++ /dev/null @@ -1,12 +0,0 @@ -#FIG 3.2 Produced by xfig version 3.2.5b -Landscape -Center -Inches -Letter -100.00 -Single --2 -1200 2 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 2850 1800 3150 1800 3150 2100 2850 2100 2850 1800 -4 1 0 50 -1 14 18 0.0000 4 150 105 3000 2025 K\001 diff --git a/crlcore/doc/images/key_Kcap.png b/crlcore/doc/images/key_Kcap.png deleted file mode 100644 index d23d72e9..00000000 Binary files a/crlcore/doc/images/key_Kcap.png and /dev/null differ diff --git a/crlcore/doc/images/key_LEFT.fig b/crlcore/doc/images/key_LEFT.fig deleted file mode 100644 index 4b113389..00000000 --- a/crlcore/doc/images/key_LEFT.fig +++ /dev/null @@ -1,12 +0,0 @@ -#FIG 3.2 Produced by xfig version 3.2.5b -Landscape -Center -Inches -Letter -100.00 -Single --2 -1200 2 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 2700 1800 3300 1800 3300 2100 2700 2100 2700 1800 -4 1 0 50 -1 18 11 0.0000 4 135 450 3000 2025 LEFT\001 diff --git a/crlcore/doc/images/key_LEFT.png b/crlcore/doc/images/key_LEFT.png deleted file mode 100644 index ffc811cb..00000000 Binary files a/crlcore/doc/images/key_LEFT.png and /dev/null differ diff --git a/crlcore/doc/images/key_Lcap.fig b/crlcore/doc/images/key_Lcap.fig deleted file mode 100644 index 7c67c8e5..00000000 --- a/crlcore/doc/images/key_Lcap.fig +++ /dev/null @@ -1,12 +0,0 @@ -#FIG 3.2 Produced by xfig version 3.2.5b -Landscape -Center -Inches -Letter -100.00 -Single --2 -1200 2 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 2850 1800 3150 1800 3150 2100 2850 2100 2850 1800 -4 1 0 50 -1 14 18 0.0000 4 150 105 3000 2025 L\001 diff --git a/crlcore/doc/images/key_Lcap.png b/crlcore/doc/images/key_Lcap.png deleted file mode 100644 index a6a398cb..00000000 Binary files a/crlcore/doc/images/key_Lcap.png and /dev/null differ diff --git a/crlcore/doc/images/key_M.fig b/crlcore/doc/images/key_M.fig deleted file mode 100644 index ff1a9ded..00000000 --- a/crlcore/doc/images/key_M.fig +++ /dev/null @@ -1,12 +0,0 @@ -#FIG 3.2 Produced by xfig version 3.2.5b -Landscape -Center -Inches -Letter -100.00 -Single --2 -1200 2 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 2850 1800 3150 1800 3150 2100 2850 2100 2850 1800 -4 1 0 50 -1 14 18 0.0000 4 150 105 3000 2025 m\001 diff --git a/crlcore/doc/images/key_M.png b/crlcore/doc/images/key_M.png deleted file mode 100644 index daaa5693..00000000 Binary files a/crlcore/doc/images/key_M.png and /dev/null differ diff --git a/crlcore/doc/images/key_Ocap.fig b/crlcore/doc/images/key_Ocap.fig deleted file mode 100644 index 783308d7..00000000 --- a/crlcore/doc/images/key_Ocap.fig +++ /dev/null @@ -1,12 +0,0 @@ -#FIG 3.2 Produced by xfig version 3.2.5b -Landscape -Center -Inches -Letter -100.00 -Single --2 -1200 2 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 2850 1800 3150 1800 3150 2100 2850 2100 2850 1800 -4 1 0 50 -1 14 18 0.0000 4 150 105 3000 2025 O\001 diff --git a/crlcore/doc/images/key_Ocap.png b/crlcore/doc/images/key_Ocap.png deleted file mode 100644 index 32980f4d..00000000 Binary files a/crlcore/doc/images/key_Ocap.png and /dev/null differ diff --git a/crlcore/doc/images/key_PLUS.fig b/crlcore/doc/images/key_PLUS.fig deleted file mode 100644 index 6a656522..00000000 --- a/crlcore/doc/images/key_PLUS.fig +++ /dev/null @@ -1,13 +0,0 @@ -#FIG 3.2 Produced by xfig version 3.2.5b -Landscape -Center -Inches -Letter -100.00 -Single --2 -1200 2 -2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 - 3375 1950 3525 1950 -2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 - 3450 1875 3450 2025 diff --git a/crlcore/doc/images/key_PLUS.png b/crlcore/doc/images/key_PLUS.png deleted file mode 100644 index 24687195..00000000 Binary files a/crlcore/doc/images/key_PLUS.png and /dev/null differ diff --git a/crlcore/doc/images/key_Pcap.fig b/crlcore/doc/images/key_Pcap.fig deleted file mode 100644 index 3a0295d8..00000000 --- a/crlcore/doc/images/key_Pcap.fig +++ /dev/null @@ -1,12 +0,0 @@ -#FIG 3.2 Produced by xfig version 3.2.5b -Landscape -Center -Inches -Letter -100.00 -Single --2 -1200 2 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 2850 1800 3150 1800 3150 2100 2850 2100 2850 1800 -4 1 0 50 -1 14 18 0.0000 4 150 105 3000 2025 P\001 diff --git a/crlcore/doc/images/key_Pcap.png b/crlcore/doc/images/key_Pcap.png deleted file mode 100644 index 5ec52051..00000000 Binary files a/crlcore/doc/images/key_Pcap.png and /dev/null differ diff --git a/crlcore/doc/images/key_Qcap.fig b/crlcore/doc/images/key_Qcap.fig deleted file mode 100644 index 0c183737..00000000 --- a/crlcore/doc/images/key_Qcap.fig +++ /dev/null @@ -1,12 +0,0 @@ -#FIG 3.2 Produced by xfig version 3.2.5b -Landscape -Center -Inches -Letter -100.00 -Single --2 -1200 2 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 2850 1800 3150 1800 3150 2100 2850 2100 2850 1800 -4 1 0 50 -1 14 18 0.0000 4 150 105 3000 2025 Q\001 diff --git a/crlcore/doc/images/key_Qcap.png b/crlcore/doc/images/key_Qcap.png deleted file mode 100644 index e6d7c257..00000000 Binary files a/crlcore/doc/images/key_Qcap.png and /dev/null differ diff --git a/crlcore/doc/images/key_RIGHT.fig b/crlcore/doc/images/key_RIGHT.fig deleted file mode 100644 index 4f234e1d..00000000 --- a/crlcore/doc/images/key_RIGHT.fig +++ /dev/null @@ -1,12 +0,0 @@ -#FIG 3.2 Produced by xfig version 3.2.5b -Landscape -Center -Inches -Letter -100.00 -Single --2 -1200 2 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 2625 1800 3375 1800 3375 2100 2625 2100 2625 1800 -4 1 0 50 -1 18 11 0.0000 4 135 600 3000 2025 RIGHT\001 diff --git a/crlcore/doc/images/key_RIGHT.png b/crlcore/doc/images/key_RIGHT.png deleted file mode 100644 index 799e6bc9..00000000 Binary files a/crlcore/doc/images/key_RIGHT.png and /dev/null differ diff --git a/crlcore/doc/images/key_S.fig b/crlcore/doc/images/key_S.fig deleted file mode 100644 index a5940541..00000000 --- a/crlcore/doc/images/key_S.fig +++ /dev/null @@ -1,12 +0,0 @@ -#FIG 3.2 Produced by xfig version 3.2.5b -Landscape -Center -Inches -Letter -100.00 -Single --2 -1200 2 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 2850 1800 3150 1800 3150 2100 2850 2100 2850 1800 -4 1 0 50 -1 14 18 0.0000 4 150 105 3000 2025 s\001 diff --git a/crlcore/doc/images/key_S.png b/crlcore/doc/images/key_S.png deleted file mode 100644 index a411ce3c..00000000 Binary files a/crlcore/doc/images/key_S.png and /dev/null differ diff --git a/crlcore/doc/images/key_Scap.fig b/crlcore/doc/images/key_Scap.fig deleted file mode 100644 index 3f35d07c..00000000 --- a/crlcore/doc/images/key_Scap.fig +++ /dev/null @@ -1,12 +0,0 @@ -#FIG 3.2 Produced by xfig version 3.2.5b -Landscape -Center -Inches -Letter -100.00 -Single --2 -1200 2 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 2850 1800 3150 1800 3150 2100 2850 2100 2850 1800 -4 1 0 50 -1 14 18 0.0000 4 150 105 3000 2025 S\001 diff --git a/crlcore/doc/images/key_Scap.png b/crlcore/doc/images/key_Scap.png deleted file mode 100644 index fde82079..00000000 Binary files a/crlcore/doc/images/key_Scap.png and /dev/null differ diff --git a/crlcore/doc/images/key_UP.fig b/crlcore/doc/images/key_UP.fig deleted file mode 100644 index 317dcc68..00000000 --- a/crlcore/doc/images/key_UP.fig +++ /dev/null @@ -1,12 +0,0 @@ -#FIG 3.2 Produced by xfig version 3.2.5b -Landscape -Center -Inches -Letter -100.00 -Single --2 -1200 2 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 2775 1800 3225 1800 3225 2100 2775 2100 2775 1800 -4 1 0 50 -1 18 11 0.0000 4 135 255 3000 2025 UP\001 diff --git a/crlcore/doc/images/key_UP.png b/crlcore/doc/images/key_UP.png deleted file mode 100644 index 090a03ac..00000000 Binary files a/crlcore/doc/images/key_UP.png and /dev/null differ diff --git a/crlcore/doc/images/key_Wcap.fig b/crlcore/doc/images/key_Wcap.fig deleted file mode 100644 index 05918a90..00000000 --- a/crlcore/doc/images/key_Wcap.fig +++ /dev/null @@ -1,12 +0,0 @@ -#FIG 3.2 Produced by xfig version 3.2.5b -Landscape -Center -Inches -Letter -100.00 -Single --2 -1200 2 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 2850 1800 3150 1800 3150 2100 2850 2100 2850 1800 -4 1 0 50 -1 14 18 0.0000 4 150 105 3000 2025 W\001 diff --git a/crlcore/doc/images/key_Wcap.png b/crlcore/doc/images/key_Wcap.png deleted file mode 100644 index c42508a1..00000000 Binary files a/crlcore/doc/images/key_Wcap.png and /dev/null differ diff --git a/crlcore/doc/images/key_Z.fig b/crlcore/doc/images/key_Z.fig deleted file mode 100644 index ee28f3a7..00000000 --- a/crlcore/doc/images/key_Z.fig +++ /dev/null @@ -1,12 +0,0 @@ -#FIG 3.2 Produced by xfig version 3.2.5b -Landscape -Center -Inches -Letter -100.00 -Single --2 -1200 2 -2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 - 2850 1800 3150 1800 3150 2100 2850 2100 2850 1800 -4 1 0 50 -1 14 18 0.0000 4 150 105 3000 2025 z\001 diff --git a/crlcore/doc/images/key_Z.png b/crlcore/doc/images/key_Z.png deleted file mode 100644 index 0ec952b0..00000000 Binary files a/crlcore/doc/images/key_Z.png and /dev/null differ diff --git a/crlcore/etc/kite.conf b/crlcore/etc/kite.conf index 9b6f7426..f5196466 100644 --- a/crlcore/etc/kite.conf +++ b/crlcore/etc/kite.conf @@ -5,22 +5,14 @@ parametersTable = \ ( ("katabatic.globalLengthThreshold",TypeInt ,1450 ) # Katabatic parameters. , ("katabatic.saturateRatio" ,TypePercentage,80 ) , ("katabatic.saturateRp" ,TypeInt ,8 ) - , ("kite.borderRipupLimit" ,TypeInt ,26 ) # Kite parameters. - , ("kite.edgeCapacity" ,TypePercentage,75 , { 'min':0, 'max':110 } ) + , ("kite.edgeCapacity" ,TypePercentage,85 , { 'min':0, 'max':110 } ) , ("kite.eventsLimit" ,TypeInt ,4000002) , ("kite.ripupCost" ,TypeInt ,3 , { 'min':0 } ) - , ("kite.globalRipupLimit" ,TypeInt ,5 , { 'min':1 } ) - , ("kite.localRipupLimit" ,TypeInt ,9 , { 'min':1 } ) - , ("kite.longGlobalRipupLimit" ,TypeInt ,5 , { 'min':1 } ) , ("kite.strapRipupLimit" ,TypeInt ,16 , { 'min':1 } ) - , ("kite.metal1MinBreak" ,TypeDouble ,100 ) - , ("kite.metal2MinBreak" ,TypeDouble ,100 ) - , ("kite.metal3MinBreak" ,TypeDouble ,100 ) - , ("kite.metal4MinBreak" ,TypeDouble ,1450 ) - , ("kite.metal5MinBreak" ,TypeDouble ,1450 ) - , ("kite.metal6MinBreak" ,TypeDouble ,1450 ) - , ("kite.metal7MinBreak" ,TypeDouble ,1450 ) + , ("kite.localRipupLimit" ,TypeInt ,9 , { 'min':1 } ) + , ("kite.globalRipupLimit" ,TypeInt ,5 , { 'min':1 } ) + , ("kite.longGlobalRipupLimit" ,TypeInt ,5 , { 'min':1 } ) ) # Kite Layout. @@ -35,15 +27,7 @@ layoutTable = \ , (TypeOption , "kite.edgeCapacity" , "Edge Capacity (%)" , 0 ) , (TypeOption , "kite.eventsLimit" , "Events Limit" , 0 ) , (TypeOption , "kite.ripupCost" , "Ripup Cost" , 1, 1, Cfg.ParameterWidgetFlags.UseSpinBox ) - , (TypeOption , "kite.metal1MinBreak", "METAL1 Length Min Break", 0 ) - , (TypeOption , "kite.metal2MinBreak", "METAL2 Length Min Break", 0 ) - , (TypeOption , "kite.metal3MinBreak", "METAL3 Length Min Break", 0 ) - , (TypeOption , "kite.metal4MinBreak", "METAL4 Length Min Break", 0 ) - , (TypeOption , "kite.metal5MinBreak", "METAL5 Length Min Break", 0 ) - , (TypeOption , "kite.metal6MinBreak", "METAL6 Length Min Break", 0 ) - , (TypeOption , "kite.metal7MinBreak", "METAL7 Length Min Break", 0 ) , (TypeSection, "Ripup Limits", 1 ) - , (TypeOption , "kite.borderRipupLimit" , "Borders" , 1, 1, Cfg.ParameterWidgetFlags.UseSpinBox ) , (TypeOption , "kite.strapRipupLimit" , "Straps" , 1, 1, Cfg.ParameterWidgetFlags.UseSpinBox ) , (TypeOption , "kite.localRipupLimit" , "Locals" , 1, 1, Cfg.ParameterWidgetFlags.UseSpinBox ) , (TypeOption , "kite.globalRipupLimit" , "Globals" , 1, 1, Cfg.ParameterWidgetFlags.UseSpinBox ) diff --git a/documentation/CMakeLists.txt b/documentation/CMakeLists.txt new file mode 100644 index 00000000..d9e11d06 --- /dev/null +++ b/documentation/CMakeLists.txt @@ -0,0 +1,31 @@ +# -*- mode: CMAKE; explicit-buffer-name: "CMakeLists.txt" -*- + + project(DOCUMENTATION) + + cmake_minimum_required(VERSION 2.4.0) + + OPTION(BUILD_DOC "Build the documentation (html+latex)" OFF) + + list(INSERT CMAKE_MODULE_PATH 0 "${DESTDIR}/$ENV{CORIOLIS_TOP}/share/cmake/Modules/") + find_package(Bootstrap REQUIRED) + setup_project_paths(CORIOLIS) + list(INSERT CMAKE_MODULE_PATH 0 "${CRLCORE_SOURCE_DIR}/cmake_modules/") + print_cmake_module_path() + + set_cmake_policies() + check_distribution() + +#if(BUILD_DOC) +# include(UseLATEX) +#endif(BUILD_DOC) + + add_subdirectory(examples) + if(BUILD_DOC) + add_subdirectory(UsersGuide) + endif(BUILD_DOC) + + set ( htmlInstallDir share/doc/coriolis2/ ) + set ( latexInstallDir share/doc/coriolis2/ ) + + install ( FILES general-index.html DESTINATION ${htmlInstallDir} RENAME index.html ) + diff --git a/documentation/UsersGuide/CMakeLists.txt b/documentation/UsersGuide/CMakeLists.txt new file mode 100644 index 00000000..bd3a201a --- /dev/null +++ b/documentation/UsersGuide/CMakeLists.txt @@ -0,0 +1,27 @@ + + set ( htmlInstallDir share/doc/coriolis2/en/html/users-guide ) + set ( latexInstallDir share/doc/coriolis2/en/latex/users-guide ) + + add_custom_target ( doc_HTML ALL + cd ${DOCUMENTATION_SOURCE_DIR}/UsersGuide + && rst2html --link-stylesheet --stylesheet=./SoC.css,./Pygments.css UsersGuide_HTML.rst UsersGuide.html ) + + add_custom_target ( doc_LaTeX ALL + cd ${DOCUMENTATION_SOURCE_DIR}/UsersGuide + && rst2latex --use-latex-toc --stylesheet=./socstyle.tex UsersGuide_LaTeX.rst UsersGuide-raw.tex + && sed 's, \& \\\\multicolumn{2}{l|}{, \& \\\\multicolumn{2}{p{0.6\\\\DUtablewidth}|}{,' UsersGuide-raw.tex > UsersGuide.tex ) + + install ( DIRECTORY images/ + DESTINATION ${htmlInstallDir}/images + FILES_MATCHING PATTERN "*.png" ) + install ( FILES SoC.css + Pygments.css + UsersGuide.html DESTINATION ${htmlInstallDir} ) + + install ( DIRECTORY images/ + DESTINATION ${latexInstallDir}/images + FILES_MATCHING PATTERN "*.pdf" + PATTERN "*.eps" ) + + install ( FILES socstyle.tex + UsersGuide.tex DESTINATION ${latexInstallDir} ) diff --git a/crlcore/doc/UsersGuide/HTML_defs.rst b/documentation/UsersGuide/HTML_defs.rst similarity index 92% rename from crlcore/doc/UsersGuide/HTML_defs.rst rename to documentation/UsersGuide/HTML_defs.rst index 5438c67f..52e72cae 100644 --- a/crlcore/doc/UsersGuide/HTML_defs.rst +++ b/documentation/UsersGuide/HTML_defs.rst @@ -4,6 +4,11 @@ .. role:: raw-html(raw) :format: html +.. URLs that changes between the various backends. +.. _Coriolis Tools Documentation: file:///usr/share/doc/coriolis2/index.html +.. _Stratus Documentation: file:///usr/share/doc/coriolis2/en/html/stratus/index.html +.. _Here: file:///usr/share/doc/coriolis2/en/latex/users-guide/UsersGuide.pdf + .. For HTML backend .. |Key_ESC| image:: ./images/key_ESC.png .. |Key_CTRL| image:: ./images/key_CTRL.png diff --git a/crlcore/doc/UsersGuide/LaTeX_defs.rst b/documentation/UsersGuide/LaTeX_defs.rst similarity index 94% rename from crlcore/doc/UsersGuide/LaTeX_defs.rst rename to documentation/UsersGuide/LaTeX_defs.rst index 5df7b965..ed121b17 100644 --- a/crlcore/doc/UsersGuide/LaTeX_defs.rst +++ b/documentation/UsersGuide/LaTeX_defs.rst @@ -4,6 +4,10 @@ .. role:: raw-latex(raw) :format: latex +.. URLs that changes between the various backends. +.. _Coriolis Tools Documentation: https://www-soc.lip6.fr/sesi-docs/coriolis2-docs/coriolis2/ +.. _Stratus Documentation: https://www-soc.lip6.fr/sesi-docs/coriolis2-docs/coriolis2/en/html/stratus/index.html + .. |DONE| replace:: :raw-latex:`\marginpar{\fbox{\small\ding{56}}}` .. For LaTeX/PDF backend. @@ -50,7 +54,7 @@ .. |ControllerInspector_3| replace:: :raw-latex:`\begin{center}\includegraphics[width=.7\textwidth]{./images/Controller-Inspector-3.eps}\end{center}` .. |ControllerSettings_1| replace:: :raw-latex:`\begin{center}\includegraphics[width=.7\textwidth]{./images/Controller-Settings-1.eps}\end{center}` -.. |BigMouse| image:: ./images/ComputerMouse.png +.. |BigMouse| image:: ./images/ComputerMouse.eps :scale: 25% .. Direct LaTeX commands encapsulation. diff --git a/crlcore/doc/UsersGuide/Pygments.css b/documentation/UsersGuide/Pygments.css similarity index 100% rename from crlcore/doc/UsersGuide/Pygments.css rename to documentation/UsersGuide/Pygments.css diff --git a/crlcore/doc/UsersGuide/SoC.css b/documentation/UsersGuide/SoC.css similarity index 97% rename from crlcore/doc/UsersGuide/SoC.css rename to documentation/UsersGuide/SoC.css index ec6d2f2e..8bc16800 100644 --- a/crlcore/doc/UsersGuide/SoC.css +++ b/documentation/UsersGuide/SoC.css @@ -1,7 +1,10 @@ html, body, th, td, tr, p, li, h1, h2, h3, h4, h5, h6 { font-size: 96%; + /* font-family: verdana, sans-serif; + */ + font-family: "Open Sans", sans-serif; } body { @@ -26,12 +29,12 @@ body.gsummary { } h1, h2, h3, h4, h5, h6 { - font-family: verdana, sans-serif; + font-family: "Open Sans", sans-serif; } h1 { text-align: left; } h2, h3, h4, h5, h6 { text-align: left; } -h1, h2, h3 { font-family: "Liberation Serif"; +h1, h2, h3 { font-family: "Serif"; } h1 { font-weight: normal; font-size: 170%; padding-top: 7pt; margin-top: 25pt; } h2 { font-weight: normal; font-size: 140%; padding-top: 7pt; margin-top: 25pt; } @@ -50,6 +53,12 @@ hr { padding-bottom: 10pt; } +div#contents { + margin: 30pt; + padding: 2pt 10pt; + background-color: #fff676; +} + div#centered { margin-left: auto; margin-right: auto; @@ -624,8 +633,8 @@ table.wiki th, table th { } table.docutils { - margin-left: 10%; - margin-right: 10%; + margin-left: 5%; + margin-right: 5%; } table.wiki, table.wiki th, table.wiki td { border: 1px solid black; } @@ -691,6 +700,14 @@ span.cb { white-space: pre; } +span.fboxtt { + border: 1px solid black; + padding: 0px 4px; + font-family: "andale mono", monospace; + font-weight: bold; + white-space: pre; +} + #notice.system-message, .notice.system-message { color: black; background: #DDFFDD; diff --git a/documentation/UsersGuide/UsersGuide.aux b/documentation/UsersGuide/UsersGuide.aux new file mode 100644 index 00000000..9e4ffbb1 --- /dev/null +++ b/documentation/UsersGuide/UsersGuide.aux @@ -0,0 +1,165 @@ +\relax +\providecommand\HyperFirstAtBeginDocument{\AtBeginDocument} +\HyperFirstAtBeginDocument{\ifx\hyper@anchor\@undefined +\global\let\oldcontentsline\contentsline +\gdef\contentsline#1#2#3#4{\oldcontentsline{#1}{#2}{#3}} +\global\let\oldnewlabel\newlabel +\gdef\newlabel#1#2{\newlabelxx{#1}#2} +\gdef\newlabelxx#1#2#3#4#5#6{\oldnewlabel{#1}{{#2}{#3}}} +\AtEndDocument{\ifx\hyper@anchor\@undefined +\let\contentsline\oldcontentsline +\let\newlabel\oldnewlabel +\fi} +\fi} +\global\let\hyper@last\relax +\gdef\HyperFirstAtBeginDocument#1{#1} +\providecommand*\HyPL@Entry[1]{} +\HyPL@Entry{0<>} +\select@language{english} +\@writefile{toc}{\select@language{english}} +\@writefile{lof}{\select@language{english}} +\@writefile{lot}{\select@language{english}} +\newlabel{coriolis-user-s-guide}{{}{1}{\relax }{section*.1}{}} +\newlabel{contents}{{}{1}{\relax }{section*.2}{}} +\HyPL@Entry{1<>} +\@writefile{toc}{\contentsline {section}{Credits \& License}{2}{section*.3}} +\newlabel{credits-license}{{}{2}{\relax }{section*.3}{}} +\HyPL@Entry{2<>} +\@writefile{toc}{\contentsline {section}{Release Notes}{3}{section*.4}} +\newlabel{release-notes}{{}{3}{\relax }{section*.4}{}} +\@writefile{toc}{\contentsline {subsection}{Release 1.0.1475}{3}{section*.5}} +\newlabel{release-1-0-1475}{{}{3}{\relax }{section*.5}{}} +\@writefile{toc}{\contentsline {subsection}{Release 1.0.1963}{3}{section*.6}} +\newlabel{release-1-0-1963}{{}{3}{\relax }{section*.6}{}} +\@writefile{toc}{\contentsline {subsection}{Release 1.0.2049}{3}{section*.7}} +\newlabel{release-1-0-2049}{{}{3}{\relax }{section*.7}{}} +\HyPL@Entry{3<>} +\@writefile{toc}{\contentsline {subsection}{Release v2.0.0 (c0b9992)}{4}{section*.8}} +\newlabel{release-v2-0-0-c0b9992}{{}{4}{\relax }{section*.8}{}} +\gdef \LT@i {\LT@entry + {1}{114.85526pt}\LT@entry + {1}{303.50418pt}} +\HyPL@Entry{4<>} +\@writefile{toc}{\contentsline {section}{Installation}{5}{section*.9}} +\newlabel{installation}{{}{5}{\relax }{section*.9}{}} +\@writefile{toc}{\contentsline {subsection}{Fixed Directory Tree}{5}{section*.10}} +\newlabel{fixed-directory-tree}{{}{5}{\relax }{section*.10}{}} +\HyPL@Entry{5<>} +\@writefile{toc}{\contentsline {subsection}{Building Coriolis}{6}{section*.11}} +\newlabel{building-coriolis}{{}{6}{\relax }{section*.11}{}} +\@writefile{toc}{\contentsline {subsection}{Packaging Coriolis}{6}{section*.12}} +\newlabel{packaging-coriolis}{{}{6}{\relax }{section*.12}{}} +\@writefile{toc}{\contentsline {subsection}{Hooking up into Alliance}{6}{section*.13}} +\newlabel{hooking-up-into-alliance}{{}{6}{\relax }{section*.13}{}} +\HyPL@Entry{6<>} +\@writefile{toc}{\contentsline {subsection}{Environment Helper}{7}{section*.14}} +\newlabel{environment-helper}{{}{7}{\relax }{section*.14}{}} +\gdef \LT@ii {\LT@entry + {1}{49.60522pt}\LT@entry + {1}{165.90092pt}\LT@entry + {1}{217.76141pt}} +\HyPL@Entry{7<>} +\@writefile{toc}{\contentsline {section}{Documentation}{8}{section*.15}} +\newlabel{documentation}{{}{8}{\relax }{section*.15}{}} +\@writefile{toc}{\contentsline {section}{Coriolis Configuration \& Initialisation}{8}{section*.16}} +\newlabel{coriolis-configuration-initialisation}{{}{8}{\relax }{section*.16}{}} +\@writefile{toc}{\contentsline {subsection}{Configuration Helpers}{8}{section*.17}} +\newlabel{configuration-helpers}{{}{8}{\relax }{section*.17}{}} +\@writefile{toc}{\contentsline {subsubsection}{Alliance Helper}{8}{section*.18}} +\newlabel{id1}{{}{8}{\relax }{section*.18}{}} +\newlabel{alliance-helper}{{}{8}{\relax }{section*.18}{}} +\HyPL@Entry{8<>} +\HyPL@Entry{9<>} +\@writefile{toc}{\contentsline {subsubsection}{Tools Configuration Helpers}{10}{section*.19}} +\newlabel{tools-configuration-helpers}{{}{10}{\relax }{section*.19}{}} +\HyPL@Entry{10<>} +\@writefile{toc}{\contentsline {section}{CGT - The Graphical Interface}{11}{section*.20}} +\newlabel{cgt-the-graphical-interface}{{}{11}{\relax }{section*.20}{}} +\HyPL@Entry{11<>} +\HyPL@Entry{12<>} +\@writefile{toc}{\contentsline {section}{Viewer \& Tools}{13}{section*.21}} +\newlabel{id2}{{}{13}{\relax }{section*.21}{}} +\newlabel{viewer-tools}{{}{13}{\relax }{section*.21}{}} +\@writefile{toc}{\contentsline {subsection}{Stratus Netlist Capture}{13}{section*.22}} +\newlabel{stratus-netlist-capture}{{}{13}{\relax }{section*.22}{}} +\@writefile{toc}{\contentsline {subsection}{The Hurricane Data-Base}{13}{section*.23}} +\newlabel{the-hurricane-data-base}{{}{13}{\relax }{section*.23}{}} +\HyPL@Entry{13<>} +\@writefile{toc}{\contentsline {subsection}{Mauka -{}- Placer}{14}{section*.24}} +\newlabel{mauka-placer}{{}{14}{\relax }{section*.24}{}} +\@writefile{toc}{\contentsline {subsection}{Knik -{}- Global Router}{14}{section*.25}} +\newlabel{knik-global-router}{{}{14}{\relax }{section*.25}{}} +\@writefile{toc}{\contentsline {subsection}{Kite -{}- Detailed Router}{14}{section*.26}} +\newlabel{kite-detailed-router}{{}{14}{\relax }{section*.26}{}} +\gdef \LT@iii {\LT@entry + {1}{170.48116pt}\LT@entry + {1}{88.52501pt}\LT@entry + {5}{587.85477pt}} +\HyPL@Entry{14<>} +\@writefile{toc}{\contentsline {subsubsection}{Kite Configuration Parameters}{15}{section*.27}} +\newlabel{kite-configuration-parameters}{{}{15}{\relax }{section*.27}{}} +\@writefile{toc}{\contentsline {subsection}{Executing Python Scripts in Cgt}{15}{section*.28}} +\newlabel{executing-python-scripts-in-cgt}{{}{15}{\relax }{section*.28}{}} +\newlabel{python-scripts-in-cgt}{{}{15}{\relax }{section*.28}{}} +\gdef \LT@iv {\LT@entry + {1}{85.57443pt}\LT@entry + {1}{93.96251pt}\LT@entry + {1}{253.3158pt}} +\HyPL@Entry{15<>} +\@writefile{toc}{\contentsline {subsection}{Printing \& Snapshots}{16}{section*.29}} +\newlabel{printing-snapshots}{{}{16}{\relax }{section*.29}{}} +\gdef \LT@v {\LT@entry + {1}{79.7221pt}\LT@entry + {1}{95.63461pt}\LT@entry + {1}{257.49603pt}} +\HyPL@Entry{16<>} +\@writefile{toc}{\contentsline {subsection}{Memento of Shortcuts in Graphic Mode}{17}{section*.30}} +\newlabel{memento-of-shortcuts-in-graphic-mode}{{}{17}{\relax }{section*.30}{}} +\gdef \LT@vi {\LT@entry + {1}{160.86342pt}\LT@entry + {1}{252.89458pt}} +\HyPL@Entry{17<>} +\@writefile{toc}{\contentsline {subsection}{Cgt Command Line Options}{18}{section*.31}} +\newlabel{cgt-command-line-options}{{}{18}{\relax }{section*.31}{}} +\gdef \LT@vii {\LT@entry + {1}{170.48116pt}\LT@entry + {1}{88.52501pt}\LT@entry + {5}{328.64403pt}} +\HyPL@Entry{18<>} +\@writefile{toc}{\contentsline {subsection}{Miscellaneous Settings}{19}{section*.32}} +\newlabel{miscellaneous-settings}{{}{19}{\relax }{section*.32}{}} +\@writefile{toc}{\contentsline {section}{The Controller}{19}{section*.33}} +\newlabel{id3}{{}{19}{\relax }{section*.33}{}} +\newlabel{the-controller}{{}{19}{\relax }{section*.33}{}} +\@writefile{toc}{\contentsline {subsection}{The Look Tab}{19}{section*.34}} +\newlabel{id4}{{}{19}{\relax }{section*.34}{}} +\newlabel{the-look-tab}{{}{19}{\relax }{section*.34}{}} +\HyPL@Entry{19<>} +\@writefile{toc}{\contentsline {subsection}{The Filter Tab}{20}{section*.35}} +\newlabel{id5}{{}{20}{\relax }{section*.35}{}} +\newlabel{the-filter-tab}{{}{20}{\relax }{section*.35}{}} +\HyPL@Entry{20<>} +\@writefile{toc}{\contentsline {subsection}{The Layers\&Go Tab}{21}{section*.36}} +\newlabel{id6}{{}{21}{\relax }{section*.36}{}} +\newlabel{the-layers-go-tab}{{}{21}{\relax }{section*.36}{}} +\HyPL@Entry{21<>} +\@writefile{toc}{\contentsline {subsection}{The Netlist Tab}{22}{section*.37}} +\newlabel{id7}{{}{22}{\relax }{section*.37}{}} +\newlabel{the-netlist-tab}{{}{22}{\relax }{section*.37}{}} +\HyPL@Entry{22<>} +\@writefile{toc}{\contentsline {subsection}{The Selection Tab}{23}{section*.38}} +\newlabel{id8}{{}{23}{\relax }{section*.38}{}} +\newlabel{the-selection-tab}{{}{23}{\relax }{section*.38}{}} +\HyPL@Entry{23<>} +\@writefile{toc}{\contentsline {subsection}{The Inspector Tab}{24}{section*.39}} +\newlabel{id9}{{}{24}{\relax }{section*.39}{}} +\newlabel{the-inspector-tab}{{}{24}{\relax }{section*.39}{}} +\HyPL@Entry{24<>} +\HyPL@Entry{25<>} +\@writefile{toc}{\contentsline {subsection}{The Settings Tab}{26}{section*.40}} +\newlabel{id10}{{}{26}{\relax }{section*.40}{}} +\newlabel{the-settings-tab}{{}{26}{\relax }{section*.40}{}} +\HyPL@Entry{26<>} +\@writefile{toc}{\contentsline {section}{A complete Example: AM2901}{27}{section*.41}} +\newlabel{a-complete-example-am2901}{{}{27}{\relax }{section*.41}{}} +\ttl@finishall diff --git a/crlcore/doc/UsersGuide/UsersGuide.rst b/documentation/UsersGuide/UsersGuide.rst similarity index 69% rename from crlcore/doc/UsersGuide/UsersGuide.rst rename to documentation/UsersGuide/UsersGuide.rst index 50169d93..9479db91 100644 --- a/crlcore/doc/UsersGuide/UsersGuide.rst +++ b/documentation/UsersGuide/UsersGuide.rst @@ -4,6 +4,7 @@ .. role:: ul .. role:: cb .. role:: sc +.. role:: fboxtt .. Acronyms & names. .. |GNU| replace:: :sc:`gnu` @@ -43,11 +44,13 @@ .. |hMetis| replace:: :sc:`hMetis` .. |Mauka| replace:: :sc:`Mauka` .. |Knik| replace:: :sc:`Knik` +.. |Katabatic| replace:: :sc:`Katabatic` .. |Kite| replace:: :sc:`Kite` .. |Stratus| replace:: :sc:`Stratus` .. |Stratus1| replace:: :sc:`Stratus1` .. |Stratus2| replace:: :sc:`Stratus2` .. |Unicorn| replace:: :sc:`Unicorn` +.. |ccb| replace:: :cb:`ccb` .. |cgt| replace:: :cb:`cgt` .. |Chams| replace:: :sc:`Chams` .. |OpenChams| replace:: :sc:`OpenChams` @@ -63,12 +66,18 @@ .. |RedHat| replace:: :sc:`RedHat` .. |Fedora| replace:: :sc:`Fedora` .. |FC13| replace:: :sc:`fc13` +.. |Debian| replace:: :sc:`Debian` .. |Ubuntu| replace:: :sc:`Ubuntu` .. |Qt| replace:: :sc:`qt` .. |tty| replace:: :cb:`tty` +.. |svn| replace:: :cb:`svn` +.. |git| replace:: :cb:`git` +.. |rpm| replace:: :cb:`rpm` .. URLs +.. _FGR: http://vlsicad.eecs.umich.edu/BK/FGR/ .. _Box Router: http://www.cerc.utexas.edu/~thyeros/boxrouter/boxrouter.htm +.. _hMETIS: http://glaros.dtc.umn.edu/gkhome/views/metis .. _Knik Thesis: http://www-soc.lip6.fr/en/users/damiendupuis/PhD/ .. _coriolis2-1.0.2049-1.slsoc6.i686.rpm: http://asim.lip6.fr/pub/coriolis/2.0/coriolis2-1.0.2049-1.slsoc6.i686.rpm @@ -110,10 +119,20 @@ .. |dot_conf| replace:: :cb:`.conf` +|medskip| + ===================== Coriolis User's Guide ===================== +|medskip| + +.. raw:: html + +
+ The pdf version of this document is available here:
+ Coriolis User's Guide +
.. contents:: @@ -159,9 +178,9 @@ Credits & License |medskip| -The |Hurricane| data-base is copyright© |Bull| 2000-2012 and is +The |Hurricane| data-base is copyright© |Bull| 2000-2014 and is released under the terms of the |LGPL| license. All other tools are -copyright© |UPMC| 2008-2012 and released under the |GPL| +copyright© |UPMC| 2008-2014 and released under the |GPL| license. The |Knik| router makes use of the |Flute| software, which is @@ -235,33 +254,148 @@ Release `2049` is Alpha. #. The |cgt| main has been rewritten in Python. +Release **v2.0.0** +~~~~~~~~~~~~~~~~~~ + +#. Migrated the repository from |svn| to |git|, and release complete sources. + As a consequence, we drop the distribution packaging support and give + public read-only access to the repository. +#. Deep rewrite of the |Katabatic| database and |Kite| detailed router, + achieve a speedup factor greater than 20... + + |newpage| Installation ============ -Binary packages avalaible: +.. note:: + As the sources are being released, the binary packaging is dropped. + You still may find older version here: http://asim.lip6.fr/pub/coriolis/2.0 . -+-----------------------+----------------------------------------------+ -| Distribution | Package | -+=======================+==============================================+ -| |Scientific Linux| 6 | | coriolis2-1.0.2049-1.slsoc6.i686.rpm_ | -| | | coriolis2-1.0.2049-1.slsoc6.x86_64.rpm_ | -+-----------------------+----------------------------------------------+ -| |Fedora| 16 | | coriolis2-1.0.2049-1.fc16.i686.rpm_ | -| | | coriolis2-1.0.2049-1.fc16.x86_64.rpm_ | -+-----------------------+----------------------------------------------+ -| |Ubuntu| 10.04 LTS | | `coriolis2_1.0-2049-1_.i386.rpm (10.04)`_ | -| | | `coriolis2_1.0-2049-1_.amd64.rpm (10.04)`_ | -+-----------------------+----------------------------------------------+ -| |Ubuntu| 12.04 LTS | | `coriolis2_1.0-2049-1_.i386.rpm (12.04)`_ | -| | | `coriolis2_1.0-2049-1_.amd64.rpm (12.04)`_ | -+-----------------------+----------------------------------------------+ +In a nutshell, building source consist in pulling the |git| repository then +running the |ccb| installer. -Older version can be found here: http://asim.lip6.fr/pub/coriolis/2.0 . +Main building prerequisites: -If you are installing from source, you should go to section `Installation From Sources`_. +* cmake +* g++ +* boost +* libxml2 +* yacc & lex. +* Qt 4 +* LEF/DEF (optional). +* hMetis (optional). +* doxygen. +* latex +* latex2html. +* python-docutils (for reStructuredText). + + +Fixed Directory Tree +~~~~~~~~~~~~~~~~~~~~ + +In order to simplificate the work of the |ccb| installer, the source, build +and installation tree is fixed. To successfully compile |Coriolis| you must +follow it exactly. The tree is relative to the home directory of the user +building it (noted :fboxtt:`~/` or :fboxtt:`$HOME/`). Only the source +directory needs to be manually created by the user, all others will be +automatically created either by |ccb| or the build system. + ++--------------------------+-----------------------------------------------------------------------------+ +| **Sources** | ++--------------------------+-----------------------------------------------------------------------------+ +| | Sources root | | ~/coriolis-2.x/src | +| | **under git** | | ~/coriolis-2.x/src/coriolis | ++--------------------------+-----------------------------------------------------------------------------+ +| **Architecture Dependant Build** | ++--------------------------+-----------------------------------------------------------------------------+ +| | Linux, SL 6, 32 bits | | ~/coriolis-2.x/Linux.slsoc6x/Release.Shared/build/ | +| | Linux, SL 6, 64 bits | | ~/coriolis-2.x/Linux.slsoc6x_64/Release.Shared/build/ | +| | FreeBSD 8, 32 bits | | ~/coriolis-2.x/FreeBSD.8x.i386/Release.Shared/build/ | +| | FreeBSD 8, 64 bits | | ~/coriolis-2.x/FreeBSD.8x.amd64/Release.Shared/build/ | ++--------------------------+-----------------------------------------------------------------------------+ +| **Architecture Dependant Install** | ++--------------------------+-----------------------------------------------------------------------------+ +| Linux, SL 6, 32 bits | ~/coriolis-2.x/Linux.slsoc6x/Release.Shared/install/ | ++--------------------------+-----------------------------------------------------------------------------+ +| **FHS Compliant Structure under Install** | ++--------------------------+-----------------------------------------------------------------------------+ +| | Binaries | | .../install/bin | +| | Libraries (Python) | | .../install/lib | +| | Include by tool | | .../install/include/coriolis2// | +| | Configuration files | | .../install/etc/coriolis2/ | +| | Doc, by tool | | .../install/share/doc/coriolis2/en/html/ | ++--------------------------+-----------------------------------------------------------------------------+ + +.. note:: *Alternate build types:* the ``Release.Shared`` means an optimized build + with shared libraries. But there are also available ``Static`` instead of ``Shared`` + and ``Debug`` instead of ``Release`` and any combination of them. + + ``Static`` do not work because I don't know yet to mix statically linked binaries + and Python modules (which must be dynamic). + + +Building Coriolis +~~~~~~~~~~~~~~~~~ + +The first step is to create the source directory and pull the |git| repository: :: + + dummy@lepka:~$ mkdir -p ~/coriolis-2.x/src + dummy@lepka:~$ cd ~/coriolis-2.x/src + dummy@lepka:~$ git clone https://www-soc.lip6.fr/git/coriolis.git + dummy@lepka:~$ cd coriolis + +Second and final step, build & install: :: + + dummy@lepka:src$ ./bootstrap/ccp.py --project=coriolis --make="-j4 install" + dummy@lepka:src$ ./bootstrap/ccb.py --project=coriolis --doc --make="-j1 install" + +We need two steps because the documentation do not support to be generated with +a parallel build. So we compile & install in a first step in ``-j4`` (or whatever) +then we generate the documentation in ``-j1`` + +The complete list of |ccb| functionalities can be accessed with the ``--help`` argument. +It also may be run in graphical mode (``--gui``). + + +Packaging Coriolis +~~~~~~~~~~~~~~~~~~ + +Packager should not uses |ccb|, instead ``bootstrap/Makefile.package`` is provided +to emulate a top-level ``autotool`` makefile. Just copy it in the root of the +|Coriolis| git repository (``~/corriolis-2.x/src/coriolis/``) and build. + +Sligthly outaded packaging configuration files can also be found under ``bootstrap/``: + +* ``bootstrap/coriolis2.spec.in`` for |rpm| based distributions. +* ``bootstrap/debian`` for |Debian| based distributions. + + +Hooking up into |Alliance| +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +|Coriolis| relies on |Alliance| for the cell libraries. So after installing or +packaging, you must configure it so that it can found those libraries. + +This is done by editing the one variable :cb:`cellsTop` in the |Alliance| helper +(see `Alliance Helper`_). This variable must point to the directory of the +cells libraries. In a typical installation, this is generally +:cb:`/usr/share/alliance/cells`. + + +Environment Helper +~~~~~~~~~~~~~~~~~~ + +To simplify the tedious task of configuring your environment, a helper is provided +in the ``bootstrap`` source directory: :: + + ~/coriolis-2.x/src/bootstrap/coriolisEnv.py + +Use it like this: :: + + dummy@lepka:~> eval `~/coriolis-2.x/src/bootstrap/coriolisEnv.py` |newpage| @@ -271,7 +405,25 @@ Documentation ============= The general index of the documentation for the various parts of Coriolis -are avalaibles here file:///usr/share/doc/coriolis2/index.html . +are avalaibles here `Coriolis Tools Documentation`_. + +.. note:: **Python Documentation:** + Most of the documentation is related to the C++ API and implemetation of + the tools. However, the |Python| bindings have been created so they + mimic *as closely as possible* the C++ interface, so the documentation + applies to both languages with only minor syntactic changes. + +**General Software Architecture** + +|Coriolis| has been build with respect of the classical paradigm that the +computational instensive parts have been written in C++, and almost +everything else in |Python|. To build the |Python| interface we used +two methods: + +* For self-contained modules :cb:`boost::python` (mainly in :cb:`vlsisapd`). +* For all modules based on |Hurricane|, we created our own wrappers due + to very specific requirements such as shared functions between modules + or C++/|Python| secure bi-directional object deletion. Coriolis Configuration & Initialisation @@ -290,7 +442,7 @@ file(s): +-------+----------------------------------+----------------------------------------------+ | Order | Meaning | File | +=======+==================================+==============================================+ -| **1** | The system initialization | :cb:`/etc/coriolis2/coriolisInit.py` | +| **1** | The system initialization | :cb:`/etc/coriolis2/.conf` | +-------+----------------------------------+----------------------------------------------+ | **2** | The user's global initialization | :cb:`${HOME}/.coriolis2.conf` | +-------+----------------------------------+----------------------------------------------+ @@ -298,7 +450,7 @@ file(s): +-------+----------------------------------+----------------------------------------------+ .. note:: *The loading policy is not hard-coded.* It is implemented - at Python level in :cb:`coriolisInit.py`, and thus may be easyly be + at Python level in :cb:`/etc/coriolis2/coriolisInit.py`, and thus may be easyly be amended to whatever site policy. The truly mandatory requirement is the existence of :cb:`coriolisInit.py` @@ -310,8 +462,14 @@ Configuration Helpers To ease the writing of configuration files, a set of small helpers is available. They allow to setup the configuration parameters through -simple assembly of tuples. +simple assembly of tuples. The helpers are installed under the directory: :: + /etc/coriolis2/ + +Where :cb:`/` is the root of the installation. + + +.. _Alliance Helper: |Alliance| Helper ----------------- @@ -319,7 +477,7 @@ simple assembly of tuples. The configuration file must provide a :cb:`allianceConfig` tuple of the form: :: - cellsTop = '/soc/alliance/cells/' + cellsTop = '/usr/share/alliance/cells/' allianceConfig = \ ( ( 'SYMBOLIC_TECHNOLOGY', helpers.sysConfDir+'/technology.symbolic.xml' ) @@ -459,7 +617,7 @@ Taxonomy of the file: * ``parametersTable``, defines & initialise the configuration variables. * ``layoutTables``, defines how the various parameters will be displayed - in the configuration window + in the configuration window (`The Settings Tab`_). * The ``parametersTable``, is a tuple (list) of tuples. Each entry in the list describe a configuration parameter. In it's simplest form, it's a quadruplet @@ -518,6 +676,14 @@ Features are detailed in `Viewer & Tools`_. Viewer & Tools ============== +|Stratus| Netlist Capture +~~~~~~~~~~~~~~~~~~~~~~~~~ + +|Stratus| is the replacement for |GenLib| procedural netlist capture language. +It is designed as a set of |Python| classes, and comes with it's own documentation +(`Stratus Documentation`_) + + The |Hurricane| Data-Base ~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -551,30 +717,39 @@ As for the first release, |Coriolis| can be used only for two purposes : Mauka -- Placer ~~~~~~~~~~~~~~~ -Mauka makes uses of hMetis. +|Mauka| was originally designed to be a recursive quadri-partionner. Unfortunatly +it is was based on the hMETIS_ library (*not* :sc:`METIS`) which is no longer +maintained (only an old binary 32 bits version is available). -To be completed... +So now it is only working in simulated annealing, with performances identical to +the |Alliance| placer :cb:`ocp`. In other words, it is slow... .. note:: *Instance Duplication Problem:* a same logical instance cannot have two different placements. So, either you manually make a clone of it or you supply a placement for it. This is currently a drawback of our *folded hierarchy* approach. +**Reseting the Placement** + +Once a placement has been done, the placer cannot reset it (will be implemented +later). To perform a new placement, you must restart |cgt|. In addition, if you +have saved the placement on disk, you must erase any :cb:`.ap` file, which are +automatically reloaded along with the netlist (:cb:`.vst`). + Knik -- Global Router ~~~~~~~~~~~~~~~~~~~~~ +The quality of |Knik| global routing solutions are equivalent to those of FGR_ 1.0. +For an in-depth description of |Knik| algorithms, you may download the thesis of +D. |Dupuis| avalaible from here~: `Knik Thesis`_. + The global router is (not yet) deterministic. To circumvent this limitation, -a global routing (also called a *solution*) can be saved to disk and reloaded -for later uses. +a global routing *solution* can be saved to disk and reloaded for later uses. A global routing is saved into a file with the same name as the design and a |kgr| extention. It is in `Box Router`_ output format. -For an in-depth description of |Knik| algorithms, you may download the thesis of -D. |Dupuis| avalaible from here~: `Knik Thesis`_. -|medskip| - |noindent| Menus: * |menu_P&R| |rightarrow| |menu_StepByStep| |rightarrow| |menu_KiteSaveGlobalRouting|. @@ -589,19 +764,29 @@ as its runtime and memory footprint is almost linear (with respect to the number of gates). It has successfully routed design of more than `150K` gates. |medskip| -|noindent| However, this first release has the following restrictions: +|noindent| However, this first release comes with the temporary the following +restrictions: * Works only with |SxLib| standard cell gauge. * Works always with 4 routing metal layers (`M2` through `M5`). * Do not allow (take into account) pre-routed wires on signals other than |POWER| or |GROUND|. +.. note:: + **Slow Layer Assignment.** Most of the time, the layer assignment stage is + fast (less than a dozen seconds), but in some instances it can take more + than a dozen *minutes*. This is a known bug and will be corrected in later + releases. + After each run, |Kite| displays a set of *completion ratios* which must all be equal to `100%` if the detailed routing has been successfull. -In the event of a failure, on saturated design, you may decrease the -`edge saturation ration` (argument `--edge`) to balance more evenly the design +In the event of a failure, on a saturated design, you may decrease the +`edge saturation ratio` (argument `--edge`) to balance more evenly the design saturation. That is, the maximum saturation decrease at the price of a wider -saturated area and increased wirelength. +saturated area and increased wirelength. This is the saturation of the +*global* router |Knik|, and you may increase/decrease by steps of ``5%``, +which represent one track. The maximum capacity of the |SxLib| gauge is +10 tracks in two layers, that makes 20 tracks by |Knik| edge. |newpage| @@ -618,7 +803,88 @@ the |Kite| data-structure and finish/cleanup the wiring so that its connex in the sense of |Hurricane|. *Do not* try to save your design before that step, you would get gaps in it. -The complete description of |Kite| parameters are described in `Detailed Routing Configuration Parameters`_. +You may visualize the density (saturation) of either |Knik| (on edges) or +|Kite| (on GCells) until the routing is finalized. Special layers appears +to that effect in the `The Layers&Go Tab`_. + + +Kite Configuration Parameters +----------------------------- + +As |Knik| is only called through |Kite|, it's parameters also have +the :cb:`kite.` prefix. + +The |Katabatic| parameters control the layer assignment step. + ++-----------------------------------+------------------+----------------------------+ +| Parameter Identifier | Type | Default | ++===================================+==================+============================+ +| **Katabatic Parameters** | ++-----------------------------------+------------------+----------------------------+ +|``katabatic.globalLengthThreshold``| TypeInt | :cb:`1450` | +| +------------------+----------------------------+ +| | This parameter is used by a layer assignment | +| | method which is no longer used (did not give | +| | good results) | ++-----------------------------------+------------------+----------------------------+ +| ``katabatic.saturateRatio`` | TypePercentage | :cb:`80` | +| +------------------+----------------------------+ +| | If ``M(x)`` density is above this ratio, | +| | move up feedthru global segments up from | +| | depth ``x`` to ``x+2`` | ++-----------------------------------+------------------+----------------------------+ +| ``katabatic.saturateRp`` | TypeInt | :cb:`8` | +| +------------------+----------------------------+ +| | If a GCell contains more terminals | +| | (:cb:`RoutingPad`) than that number, force a | +| | move up of the connecting segments to those | +| | in excess | ++-----------------------------------+------------------+----------------------------+ +| **Knik Parameters** | ++-----------------------------------+------------------+----------------------------+ +| ``kite.edgeCapacity`` | TypePercentage | :cb:`85` | +| +------------------+----------------------------+ +| | Adjust the maximum capacity of the global | +| | router's edges. The GCells would be too | +| | saturated for the detailed router if the edge | +| | capacity is left to 100%. | ++-----------------------------------+------------------+----------------------------+ +| **Kite Parameters** | ++-----------------------------------+------------------+----------------------------+ +| ``kite.eventsLimit`` | TypeInt | :cb:`4000002` | +| +------------------+----------------------------+ +| | The maximum number of segment displacements, | +| | this is a last ditch safety against infinite | +| | loop. It's perhaps a little too low for big | +| | designs | ++-----------------------------------+------------------+----------------------------+ +| ``kite.ripupCost`` | TypeInt | :cb:`3` | +| +------------------+----------------------------+ +| | Differential introduced between two ripup | +| | cost to avoid a loop between two ripped up | +| | segments | ++-----------------------------------+------------------+----------------------------+ +| ``kite.strapRipupLimit`` | TypeInt | :cb:`16` | +| +------------------+----------------------------+ +| | Maximum number of ripup for *strap* segments | ++-----------------------------------+------------------+----------------------------+ +| ``kite.localRipupLimit`` | TypeInt | :cb:`9` | +| +------------------+----------------------------+ +| | Maximum number of ripup for *local* segments | ++-----------------------------------+------------------+----------------------------+ +| ``kite.globalRipupLimit`` | TypeInt | :cb:`5` | +| +------------------+----------------------------+ +| | Maximum number of ripup for *global* segments,| +| | when this limit is reached, triggers topologic| +| | modification | ++-----------------------------------+------------------+----------------------------+ +| ``kite.longGlobalRipupLimit`` | TypeInt | :cb:`5` | +| +------------------+----------------------------+ +| | Maximum number of ripup for *long global* | +| | segments, when this limit is reached, triggers| +| | topological modification | ++-----------------------------------+------------------+----------------------------+ + .. _Python Scripts in Cgt: @@ -628,7 +894,7 @@ Executing Python Scripts in Cgt Python/Stratus scripts can be executed either in text or graphical mode. -.. note:: *How Cgt Locates Python Scripts.* +.. note:: **How Cgt Locates Python Scripts:** |cgt| uses the Python ``import`` mechanism to load Python scripts. So you must give the name of your script whitout ``.py`` extention and it must be reachable through the ``PYTHONPATH``. You may uses the @@ -638,6 +904,9 @@ A Python/Stratus script must contains a function called ``StratusScript`` with one optional argument, the graphical editor into which it may be running (will be set to ``None`` in text mode). +Asides for this requirement, the python script can contains anything valid +in |Python|, so don't hesitate to use any package or extention. + Any script given on the command line will be run immediatly *after* the initializations and *before* any other argument is processed. @@ -844,6 +1113,52 @@ Some Examples : > cgt -v -t -G --save-global --cell=design +Miscellaneous Settings +~~~~~~~~~~~~~~~~~~~~~~ + ++---------------------------------------+------------------+----------------------------+ +| Parameter Identifier | Type | Default | ++=======================================+==================+============================+ +| **Verbosity/Log Parameters** | ++---------------------------------------+------------------+----------------------------+ +| ``misc.info`` | TypeBool | :cb:`False` | +| +------------------+----------------------------+ +| | Enable display of *info* level message | +| | (:cb:`cinfo` stream) | ++---------------------------------------+------------------+----------------------------+ +| ``misc.bug`` | TypeBool | :cb:`False` | +| +------------------+----------------------------+ +| | Enable display of *bug* level message | +| | (:cb:`cbug` stream), messages can be a little | +| | scarry | ++---------------------------------------+------------------+----------------------------+ +| ``misc.logMode`` | TypeBool | :cb:`False` | +| +------------------+----------------------------+ +| | If enabled, assume that the output device | +| | is not a ``tty`` and suppress any escaped | +| | sequences | ++---------------------------------------+------------------+----------------------------+ +| ``misc.verboseLevel1`` | TypeBool | :cb:`True` | +| +------------------+----------------------------+ +| | First level of verbosity, disable level 2 | ++---------------------------------------+------------------+----------------------------+ +| ``misc.verboseLevel2`` | TypeBool | :cb:`False` | +| +------------------+----------------------------+ +| | Second level of verbosity | ++---------------------------------------+------------------+----------------------------+ +| **Development/Debug Parameters** | ++---------------------------------------+------------------+----------------------------+ +| ``misc.traceLevel`` | TypeInt | :cb:`0` | +| +------------------+----------------------------+ +| | Display trace information *below* that level | +| | (:cb:`ltrace` stream) | ++---------------------------------------+------------------+----------------------------+ +| ``misc.catchCore`` | TypeBool | :cb:`False` | +| +------------------+----------------------------+ +| | By default, |cgt| do not dump core. | +| | To generate one set this flag to :cb:`True` | ++---------------------------------------+------------------+----------------------------+ + .. _The Controller: The Controller @@ -1002,106 +1317,11 @@ Here comes the description of the *Settings* tab. |ControllerSettings_1| -Tools Fine Tuning -================= +A Simple Example: AM2901 +======================== +To illustrate the capabilities of |Coriolis| tools and |Python| scripting, a small +example, derived from the |Alliance| :cb:`AM2901` is supplied. -.. _`Detailed Routing Configuration Parameters`: - -Detailed Routing Configuration Parameters -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - - -+---------------------------------------+------------------+-----------+ -| Parameter Identifier | Type | Default | -+=======================================+==================+===========+ -| **Katabatic Parameters** | -+---------------------------------------+------------------+-----------+ -| | ``katabatic.globalLengthThreshold`` | | TypeInt | | 1450 | -| | ``katabatic.saturateRatio`` | | TypePercentage | | 80 | -| | ``katabatic.saturateRp`` | | TypeInt | | 8 | -| | ``kite.borderRipupLimit`` | | TypeInt | | 26 | -+---------------------------------------+------------------+-----------+ -| **Kite Parameters** | -+---------------------------------------+------------------+-----------+ -| | ``kite.edgeCapacity`` | | TypePercentage | | 65 | -| | ``kite.eventsLimit`` | | TypeInt | | 4000002 | -| | ``kite.ripupCost`` | | TypeInt | | 3 | -| | ``kite.globalRipupLimit`` | | TypeInt | | 5 | -| | ``kite.localRipupLimit`` | | TypeInt | | 7 | -| | ``kite.longGlobalRipupLimit`` | | TypeInt | | 5 | -| | ``kite.strapRipupLimit`` | | TypeInt | | 16 | -| | ``kite.metal1MinBreak`` | | TypeDouble | | 100 | -| | ``kite.metal2MinBreak`` | | TypeDouble | | 100 | -| | ``kite.metal3MinBreak`` | | TypeDouble | | 100 | -| | ``kite.metal4MinBreak`` | | TypeDouble | | 1450 | -| | ``kite.metal5MinBreak`` | | TypeDouble | | 1450 | -| | ``kite.metal6MinBreak`` | | TypeDouble | | 1450 | -| | ``kite.metal7MinBreak`` | | TypeDouble | | 1450 | -+---------------------------------------+------------------+-----------+ - - -.. _Installation from Sources: - -Installation from Sources -========================= - -Installation from source is done differently than what is done in the packaging -procedure. The archive is also structured differently and meant to be unpacked -and compiled under a user's home directory. - -Main building prerequisites: - -* cmake -* g++ -* boost -* libxml2 -* yacc & lex. -* Qt 4 -* LEF/DEF (optional). -* hMetis (optional). -* doxygen. -* latex -* latex2html. -* python-docutils (for reStructuredText). - -Simple building procedure: :: - - dummy@lepka:~$ tar jxvf coriolis2-1.0-20121103.tar.bz2 - dummy@lepka:~$ cd coriolis-2.x/src - dummy@lepka:src$ ./bootstrap/buildCoriolis.py \ - --project=bootstrap --project=vlsisapd --project=coriolis \ - --make="-j4 install" - dummy@lepka:src$ ./bootstrap/buildCoriolis.py \ - --project=bootstrap --project=vlsisapd --project=coriolis \ - --doc --make="-j1 install" - -Installation is done according to the following tree structure: - -========================= ========================================================================= -Linux, SL 6, 32 bits ~/coriolis-2.x/Linux.slsoc6x/Release.Shared/install -Linux, SL 6, 64 bits ~/coriolis-2.x/Linux.slsoc6x_64/Release.Shared/install -FreeBSD 8, 32 bits ~/coriolis-2.x/FreeBSD.8x.i386/Release.Shared/install -FreeBSD 8, 64 bits ~/coriolis-2.x/FreeBSD.8x.amd64/Release.Shared/install -========================= ========================================================================= - -.. note:: *Alternate build types:* the ``Release.Shared`` means an optimized build - with shared libraries. But there are also available ``Static`` instead of ``Shared`` - and ``Debug`` instead of ``Release`` and any combination of them. - - ``Static`` do not work because I don't know yet to mix statically linked binaries - and Python modules (which must be dynamic). - - -Environment Helper -~~~~~~~~~~~~~~~~~~ - -To simplify the tedious task of configuring your environment, a helper is provided -in the ``bootstrap`` source directory: :: - - ~/coriolis-2.x/src/bootstrap/coriolisEnv.py - -Use it like this: :: - - dummy@lepka:~> eval `~/coriolis-2.x/src/bootstrap/coriolisEnv.py` - +This example contains only the synthetized netlists and the :cb:`design.py` script +which perform the whole P&R of the design. Just lanch |cgt| then execute :cb:`design.py`. diff --git a/crlcore/doc/UsersGuide/UsersGuide_HTML.rst b/documentation/UsersGuide/UsersGuide_HTML.rst similarity index 100% rename from crlcore/doc/UsersGuide/UsersGuide_HTML.rst rename to documentation/UsersGuide/UsersGuide_HTML.rst diff --git a/crlcore/doc/UsersGuide/UsersGuide_LaTeX.rst b/documentation/UsersGuide/UsersGuide_LaTeX.rst similarity index 100% rename from crlcore/doc/UsersGuide/UsersGuide_LaTeX.rst rename to documentation/UsersGuide/UsersGuide_LaTeX.rst diff --git a/crlcore/doc/UsersGuide/WWW_defs.rst b/documentation/UsersGuide/WWW_defs.rst similarity index 93% rename from crlcore/doc/UsersGuide/WWW_defs.rst rename to documentation/UsersGuide/WWW_defs.rst index ceb5d7af..4f988421 100644 --- a/crlcore/doc/UsersGuide/WWW_defs.rst +++ b/documentation/UsersGuide/WWW_defs.rst @@ -6,6 +6,11 @@ .. stored at a different URL on the website. Namely: .. https://soc-extras.lip6.fr/media/filer/2012/12/07/ +.. URLs that changes between the various backends. +.. _Coriolis Tools Documentation: https://www-soc.lip6.fr/sesi-docs/coriolis2-docs/coriolis2/ +.. _Stratus Documentation: https://www-soc.lip6.fr/sesi-docs/coriolis2-docs/coriolis2/en/html/stratus/index.html +.. _Here: https://www-soc.lip6.fr/sesi-docs/coriolis2-docs/coriolis2/en/latex/users-guide/UsersGuide.pdf + .. role:: raw-html(raw) :format: html @@ -61,4 +66,3 @@ .. |noindent| replace:: :raw-html:`

` .. |medskip| replace:: :raw-html:`
` .. |newpage| replace:: :raw-html:`
` - diff --git a/crlcore/doc/UsersGuide/images/ComputerMouse.eps b/documentation/UsersGuide/images/ComputerMouse.eps similarity index 100% rename from crlcore/doc/UsersGuide/images/ComputerMouse.eps rename to documentation/UsersGuide/images/ComputerMouse.eps diff --git a/crlcore/doc/UsersGuide/images/ComputerMouse.jpg b/documentation/UsersGuide/images/ComputerMouse.jpg similarity index 100% rename from crlcore/doc/UsersGuide/images/ComputerMouse.jpg rename to documentation/UsersGuide/images/ComputerMouse.jpg diff --git a/crlcore/doc/UsersGuide/images/ComputerMouse.png b/documentation/UsersGuide/images/ComputerMouse.png similarity index 100% rename from crlcore/doc/UsersGuide/images/ComputerMouse.png rename to documentation/UsersGuide/images/ComputerMouse.png diff --git a/crlcore/doc/UsersGuide/images/Controller-1-eps-converted-to.pdf b/documentation/UsersGuide/images/Controller-1-eps-converted-to.pdf similarity index 100% rename from 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documentation/UsersGuide/images/key_Wcap.png diff --git a/crlcore/doc/UsersGuide/images/key_Z.fig b/documentation/UsersGuide/images/key_Z.fig similarity index 100% rename from crlcore/doc/UsersGuide/images/key_Z.fig rename to documentation/UsersGuide/images/key_Z.fig diff --git a/crlcore/doc/UsersGuide/images/key_Z.png b/documentation/UsersGuide/images/key_Z.png similarity index 100% rename from crlcore/doc/UsersGuide/images/key_Z.png rename to documentation/UsersGuide/images/key_Z.png diff --git a/crlcore/doc/UsersGuide/socstyle.tex b/documentation/UsersGuide/socstyle.tex similarity index 94% rename from crlcore/doc/UsersGuide/socstyle.tex rename to documentation/UsersGuide/socstyle.tex index 7d344a39..21f564fa 100644 --- a/crlcore/doc/UsersGuide/socstyle.tex +++ b/documentation/UsersGuide/socstyle.tex @@ -41,6 +41,7 @@ \newcommand{\DUroleul}[1]{\underline{#1}\xspace} \newcommand{\DUrolesc}[1]{\textsc{#1}\xspace} \newcommand{\DUrolecb}[1]{\textbf{\texttt{#1}}\xspace} + \newcommand{\DUrolefboxtt}[1]{\fbox{\texttt{#1}}\xspace} \newcommand{\DUtitlenote}[1]{\noindent\textbf{#1}\smallskip} @@ -68,6 +69,7 @@ \end{center} } + \newcommand{\UPMC} {\textsc{upmc}\xspace} \newcommand{\LIP} {\textsc{lip6}\xspace} \newcommand{\SoC} {\textsc{S}o\textsc{C}\xspace} @@ -76,8 +78,8 @@ \renewcommand{\sectionmark}[1]{\markboth{\thesection\ #1}{\thesection\ #1}} \renewcommand{\subsectionmark}[1]{} \lhead[]{Documentation \SoC} - \rhead[]{Avril 2012} - \lfoot[]{\LIP/\SoC} + \rhead[]{March 2014} + \lfoot[]{\UPMC/\LIP/\SoC} \rfoot[]{\thepage} \cfoot[]{} diff --git a/documentation/examples/AM2901/CMakeLists.txt b/documentation/examples/AM2901/CMakeLists.txt new file mode 100644 index 00000000..f53d027f --- /dev/null +++ b/documentation/examples/AM2901/CMakeLists.txt @@ -0,0 +1,13 @@ + + set ( examplesInstallDir share/doc/coriolis2/examples ) + + install ( FILES accu.vst + alu.vst + amd2901.vst + coeur.vst + muxe.vst + muxs.vst + ram.vst + design.py + DESTINATION ${examplesInstallDir}/AM2901 ) + diff --git a/documentation/examples/AM2901/accu.vst b/documentation/examples/AM2901/accu.vst new file mode 100644 index 00000000..65d16bdd --- /dev/null +++ b/documentation/examples/AM2901/accu.vst @@ -0,0 +1,611 @@ +entity accu is + port ( + cke : in bit; + i : in bit_vector(2 downto 0); + alu_out : in bit_vector(3 downto 0); + q0_from : in bit; + q3_from : in bit; + q0_to : out mux_bit bus; + q3_to : out mux_bit bus; + accu : inout bit_vector(3 downto 0); + vdd : in bit; + vss : in bit + ); +end accu; + +architecture structural of accu is +Component o2_x2 + port ( + i0 : in bit; + i1 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component no2_x1 + port ( + i0 : in bit; + i1 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component inv_x2 + port ( + i : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component ao22_x2 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component an12_x1 + port ( + i0 : in bit; + i1 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component nao22_x1 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component na2_x1 + port ( + i0 : in bit; + i1 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component on12_x1 + port ( + i0 : in bit; + i1 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component na3_x1 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component sff1_x4 + port ( + ck : in bit; + i : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component buf_x2 + port ( + i : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component no3_x1 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component ts_x8 + port ( + cmd : in bit; + i : in bit; + q : out mux_bit bus; + vdd : in bit; + vss : in bit + ); +end component; + +signal not_i : bit_vector( 2 downto 1); +signal rtlalc_0 : bit_vector( 3 downto 0); +signal on12_x1_sig : bit; +signal on12_x1_6_sig : bit; +signal on12_x1_5_sig : bit; +signal on12_x1_4_sig : bit; +signal on12_x1_3_sig : bit; +signal on12_x1_2_sig : bit; +signal not_aux2 : bit; +signal no3_x1_sig : bit; +signal no3_x1_2_sig : bit; +signal nao22_x1_sig : bit; +signal nao22_x1_4_sig : bit; +signal nao22_x1_3_sig : bit; +signal nao22_x1_2_sig : bit; +signal na3_x1_sig : bit; +signal na3_x1_8_sig : bit; +signal na3_x1_7_sig : bit; +signal na3_x1_6_sig : bit; +signal na3_x1_5_sig : bit; +signal na3_x1_4_sig : bit; +signal na3_x1_3_sig : bit; +signal na3_x1_2_sig : bit; +signal na2_x1_sig : bit; +signal na2_x1_4_sig : bit; +signal na2_x1_3_sig : bit; +signal na2_x1_2_sig : bit; +signal inv_x2_sig : bit; +signal inv_x2_2_sig : bit; +signal aux3 : bit; +signal aux1 : bit; +signal aux0 : bit; +signal ao22_x2_sig : bit; +signal ao22_x2_2_sig : bit; +signal an12_x1_sig : bit; +signal an12_x1_2_sig : bit; + +begin + +not_aux2_ins : o2_x2 + port map ( + i0 => i(0), + i1 => not_i(1), + q => not_aux2, + vdd => vdd, + vss => vss + ); + +not_i_2_ins : inv_x2 + port map ( + i => i(2), + nq => not_i(2), + vdd => vdd, + vss => vss + ); + +not_i_1_ins : inv_x2 + port map ( + i => i(1), + nq => not_i(1), + vdd => vdd, + vss => vss + ); + +aux3_ins : no2_x1 + port map ( + i0 => i(1), + i1 => i(0), + nq => aux3, + vdd => vdd, + vss => vss + ); + +aux1_ins : on12_x1 + port map ( + i0 => i(2), + i1 => accu(2), + q => aux1, + vdd => vdd, + vss => vss + ); + +aux0_ins : on12_x1 + port map ( + i0 => i(2), + i1 => accu(1), + q => aux0, + vdd => vdd, + vss => vss + ); + +inv_x2_ins : inv_x2 + port map ( + i => not_aux2, + nq => inv_x2_sig, + vdd => vdd, + vss => vss + ); + +ao22_x2_ins : ao22_x2 + port map ( + i0 => not_i(2), + i1 => q0_from, + i2 => inv_x2_sig, + q => ao22_x2_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_ins : nao22_x1 + port map ( + i0 => rtlalc_0(0), + i1 => i(2), + i2 => ao22_x2_sig, + nq => nao22_x1_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_ins : na2_x1 + port map ( + i0 => i(0), + i1 => rtlalc_0(0), + nq => na2_x1_sig, + vdd => vdd, + vss => vss + ); + +on12_x1_ins : on12_x1 + port map ( + i0 => not_i(2), + i1 => alu_out(0), + q => on12_x1_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_2_ins : na3_x1 + port map ( + i0 => aux3, + i1 => on12_x1_sig, + i2 => aux0, + nq => na3_x1_2_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_ins : na3_x1 + port map ( + i0 => na3_x1_2_sig, + i1 => na2_x1_sig, + i2 => nao22_x1_sig, + nq => na3_x1_sig, + vdd => vdd, + vss => vss + ); + +rtlalc_0_0_ins : sff1_x4 + port map ( + ck => cke, + i => na3_x1_sig, + q => rtlalc_0(0), + vdd => vdd, + vss => vss + ); + +inv_x2_2_ins : inv_x2 + port map ( + i => not_aux2, + nq => inv_x2_2_sig, + vdd => vdd, + vss => vss + ); + +ao22_x2_2_ins : ao22_x2 + port map ( + i0 => not_i(2), + i1 => accu(0), + i2 => inv_x2_2_sig, + q => ao22_x2_2_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_2_ins : nao22_x1 + port map ( + i0 => rtlalc_0(1), + i1 => i(2), + i2 => ao22_x2_2_sig, + nq => nao22_x1_2_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_2_ins : na2_x1 + port map ( + i0 => i(0), + i1 => rtlalc_0(1), + nq => na2_x1_2_sig, + vdd => vdd, + vss => vss + ); + +on12_x1_2_ins : on12_x1 + port map ( + i0 => not_i(2), + i1 => alu_out(1), + q => on12_x1_2_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_4_ins : na3_x1 + port map ( + i0 => aux3, + i1 => on12_x1_2_sig, + i2 => aux1, + nq => na3_x1_4_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_3_ins : na3_x1 + port map ( + i0 => na3_x1_4_sig, + i1 => na2_x1_2_sig, + i2 => nao22_x1_2_sig, + nq => na3_x1_3_sig, + vdd => vdd, + vss => vss + ); + +rtlalc_0_1_ins : sff1_x4 + port map ( + ck => cke, + i => na3_x1_3_sig, + q => rtlalc_0(1), + vdd => vdd, + vss => vss + ); + +an12_x1_ins : an12_x1 + port map ( + i0 => not_aux2, + i1 => aux0, + q => an12_x1_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_3_ins : nao22_x1 + port map ( + i0 => rtlalc_0(2), + i1 => i(2), + i2 => an12_x1_sig, + nq => nao22_x1_3_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_3_ins : na2_x1 + port map ( + i0 => i(0), + i1 => rtlalc_0(2), + nq => na2_x1_3_sig, + vdd => vdd, + vss => vss + ); + +on12_x1_3_ins : on12_x1 + port map ( + i0 => i(2), + i1 => accu(3), + q => on12_x1_3_sig, + vdd => vdd, + vss => vss + ); + +on12_x1_4_ins : on12_x1 + port map ( + i0 => not_i(2), + i1 => alu_out(2), + q => on12_x1_4_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_6_ins : na3_x1 + port map ( + i0 => on12_x1_4_sig, + i1 => on12_x1_3_sig, + i2 => aux3, + nq => na3_x1_6_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_5_ins : na3_x1 + port map ( + i0 => na3_x1_6_sig, + i1 => na2_x1_3_sig, + i2 => nao22_x1_3_sig, + nq => na3_x1_5_sig, + vdd => vdd, + vss => vss + ); + +rtlalc_0_2_ins : sff1_x4 + port map ( + ck => cke, + i => na3_x1_5_sig, + q => rtlalc_0(2), + vdd => vdd, + vss => vss + ); + +an12_x1_2_ins : an12_x1 + port map ( + i0 => not_aux2, + i1 => aux1, + q => an12_x1_2_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_4_ins : nao22_x1 + port map ( + i0 => rtlalc_0(3), + i1 => i(2), + i2 => an12_x1_2_sig, + nq => nao22_x1_4_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_4_ins : na2_x1 + port map ( + i0 => i(0), + i1 => rtlalc_0(3), + nq => na2_x1_4_sig, + vdd => vdd, + vss => vss + ); + +on12_x1_5_ins : on12_x1 + port map ( + i0 => i(2), + i1 => q3_from, + q => on12_x1_5_sig, + vdd => vdd, + vss => vss + ); + +on12_x1_6_ins : on12_x1 + port map ( + i0 => not_i(2), + i1 => alu_out(3), + q => on12_x1_6_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_8_ins : na3_x1 + port map ( + i0 => on12_x1_6_sig, + i1 => on12_x1_5_sig, + i2 => aux3, + nq => na3_x1_8_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_7_ins : na3_x1 + port map ( + i0 => na3_x1_8_sig, + i1 => na2_x1_4_sig, + i2 => nao22_x1_4_sig, + nq => na3_x1_7_sig, + vdd => vdd, + vss => vss + ); + +rtlalc_0_3_ins : sff1_x4 + port map ( + ck => cke, + i => na3_x1_7_sig, + q => rtlalc_0(3), + vdd => vdd, + vss => vss + ); + +accu_0_ins : buf_x2 + port map ( + i => rtlalc_0(0), + q => accu(0), + vdd => vdd, + vss => vss + ); + +accu_1_ins : buf_x2 + port map ( + i => rtlalc_0(1), + q => accu(1), + vdd => vdd, + vss => vss + ); + +accu_2_ins : buf_x2 + port map ( + i => rtlalc_0(2), + q => accu(2), + vdd => vdd, + vss => vss + ); + +accu_3_ins : buf_x2 + port map ( + i => rtlalc_0(3), + q => accu(3), + vdd => vdd, + vss => vss + ); + +no3_x1_ins : no3_x1 + port map ( + i0 => not_i(1), + i1 => not_i(2), + i2 => i(0), + nq => no3_x1_sig, + vdd => vdd, + vss => vss + ); + +q3_to_ins : ts_x8 + port map ( + cmd => no3_x1_sig, + i => alu_out(3), + q => q3_to, + vdd => vdd, + vss => vss + ); + +no3_x1_2_ins : no3_x1 + port map ( + i0 => i(1), + i1 => not_i(2), + i2 => i(0), + nq => no3_x1_2_sig, + vdd => vdd, + vss => vss + ); + +q0_to_ins : ts_x8 + port map ( + cmd => no3_x1_2_sig, + i => alu_out(0), + q => q0_to, + vdd => vdd, + vss => vss + ); + + +end structural; diff --git a/documentation/examples/AM2901/alu.vst b/documentation/examples/AM2901/alu.vst new file mode 100644 index 00000000..8e761169 --- /dev/null +++ b/documentation/examples/AM2901/alu.vst @@ -0,0 +1,4766 @@ +entity alu is + port ( + alu_out : inout bit_vector(3 downto 0); + cin : in bit; + cout : out bit; + i : in bit_vector(2 downto 0); + ng : out bit; + np : out bit; + ovr : out bit; + r : in bit_vector(3 downto 0); + s : in bit_vector(3 downto 0); + f3 : out bit; + vdd : in bit; + vss : in bit; + zero : out bit + ); +end alu; + +architecture structural of alu is +Component oa2a2a23_x2 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + i3 : in bit; + i4 : in bit; + i5 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component buf_x2 + port ( + i : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component nmx2_x1 + port ( + cmd : in bit; + i0 : in bit; + i1 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component noa2a2a2a24_x1 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + i3 : in bit; + i4 : in bit; + i5 : in bit; + i6 : in bit; + i7 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component an12_x1 + port ( + i0 : in bit; + i1 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component noa2ao222_x1 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + i3 : in bit; + i4 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component ao2o22_x2 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + i3 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component a3_x2 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component noa2a2a23_x1 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + i3 : in bit; + i4 : in bit; + i5 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component oa22_x2 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component nxr2_x1 + port ( + i0 : in bit; + i1 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component a2_x2 + port ( + i0 : in bit; + i1 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component o3_x2 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component noa22_x1 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component na4_x1 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + i3 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component oa2a22_x2 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + i3 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component xr2_x1 + port ( + i0 : in bit; + i1 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component oa2ao222_x2 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + i3 : in bit; + i4 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component mx2_x2 + port ( + cmd : in bit; + i0 : in bit; + i1 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component inv_x2 + port ( + i : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component o2_x2 + port ( + i0 : in bit; + i1 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component no4_x1 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + i3 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component on12_x1 + port ( + i0 : in bit; + i1 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component no2_x1 + port ( + i0 : in bit; + i1 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component no3_x1 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component nao22_x1 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component na2_x1 + port ( + i0 : in bit; + i1 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component ao22_x2 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component na3_x1 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component a4_x2 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + i3 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component nao2o22_x1 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + i3 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component mx3_x2 + port ( + cmd0 : in bit; + cmd1 : in bit; + i0 : in bit; + i1 : in bit; + i2 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +signal not_i : bit_vector( 2 downto 0); +signal not_r : bit_vector( 3 downto 0); +signal not_s : bit_vector( 3 downto 0); +signal xr2_x1_sig : bit; +signal xr2_x1_9_sig : bit; +signal xr2_x1_8_sig : bit; +signal xr2_x1_7_sig : bit; +signal xr2_x1_6_sig : bit; +signal xr2_x1_5_sig : bit; +signal xr2_x1_4_sig : bit; +signal xr2_x1_3_sig : bit; +signal xr2_x1_2_sig : bit; +signal xr2_x1_11_sig : bit; +signal xr2_x1_10_sig : bit; +signal on12_x1_sig : bit; +signal on12_x1_7_sig : bit; +signal on12_x1_6_sig : bit; +signal on12_x1_5_sig : bit; +signal on12_x1_4_sig : bit; +signal on12_x1_3_sig : bit; +signal on12_x1_2_sig : bit; +signal oa2ao222_x2_sig : bit; +signal oa2ao222_x2_2_sig : bit; +signal oa2a2a23_x2_sig : bit; +signal oa2a22_x2_sig : bit; +signal oa2a22_x2_4_sig : bit; +signal oa2a22_x2_3_sig : bit; +signal oa2a22_x2_2_sig : bit; +signal oa22_x2_sig : bit; +signal oa22_x2_9_sig : bit; +signal oa22_x2_8_sig : bit; +signal oa22_x2_7_sig : bit; +signal oa22_x2_6_sig : bit; +signal oa22_x2_5_sig : bit; +signal oa22_x2_4_sig : bit; +signal oa22_x2_3_sig : bit; +signal oa22_x2_2_sig : bit; +signal o3_x2_sig : bit; +signal o3_x2_9_sig : bit; +signal o3_x2_8_sig : bit; +signal o3_x2_7_sig : bit; +signal o3_x2_6_sig : bit; +signal o3_x2_5_sig : bit; +signal o3_x2_4_sig : bit; +signal o3_x2_3_sig : bit; +signal o3_x2_2_sig : bit; +signal o3_x2_11_sig : bit; +signal o3_x2_10_sig : bit; +signal o2_x2_sig : bit; +signal o2_x2_9_sig : bit; +signal o2_x2_8_sig : bit; +signal o2_x2_7_sig : bit; +signal o2_x2_6_sig : bit; +signal o2_x2_5_sig : bit; +signal o2_x2_4_sig : bit; +signal o2_x2_3_sig : bit; +signal o2_x2_2_sig : bit; +signal o2_x2_17_sig : bit; +signal o2_x2_16_sig : bit; +signal o2_x2_15_sig : bit; +signal o2_x2_14_sig : bit; +signal o2_x2_13_sig : bit; +signal o2_x2_12_sig : bit; +signal o2_x2_11_sig : bit; +signal o2_x2_10_sig : bit; +signal nxr2_x1_sig : bit; +signal nxr2_x1_2_sig : bit; +signal not_cin : bit; +signal not_aux99 : bit; +signal not_aux98 : bit; +signal not_aux97 : bit; +signal not_aux95 : bit; +signal not_aux92 : bit; +signal not_aux90 : bit; +signal not_aux86 : bit; +signal not_aux85 : bit; +signal not_aux84 : bit; +signal not_aux82 : bit; +signal not_aux80 : bit; +signal not_aux8 : bit; +signal not_aux79 : bit; +signal not_aux78 : bit; +signal not_aux75 : bit; +signal not_aux74 : bit; +signal not_aux73 : bit; +signal not_aux71 : bit; +signal not_aux70 : bit; +signal not_aux7 : bit; +signal not_aux68 : bit; +signal not_aux67 : bit; +signal not_aux66 : bit; +signal not_aux65 : bit; +signal not_aux64 : bit; +signal not_aux62 : bit; +signal not_aux61 : bit; +signal not_aux60 : bit; +signal not_aux58 : bit; +signal not_aux57 : bit; +signal not_aux55 : bit; +signal not_aux54 : bit; +signal not_aux53 : bit; +signal not_aux5 : bit; +signal not_aux47 : bit; +signal not_aux43 : bit; +signal not_aux40 : bit; +signal not_aux34 : bit; +signal not_aux30 : bit; +signal not_aux3 : bit; +signal not_aux28 : bit; +signal not_aux26 : bit; +signal not_aux22 : bit; +signal not_aux21 : bit; +signal not_aux2 : bit; +signal not_aux17 : bit; +signal not_aux16 : bit; +signal not_aux15 : bit; +signal not_aux134 : bit; +signal not_aux133 : bit; +signal not_aux132 : bit; +signal not_aux131 : bit; +signal not_aux130 : bit; +signal not_aux13 : bit; +signal not_aux129 : bit; +signal not_aux128 : bit; +signal not_aux127 : bit; +signal not_aux126 : bit; +signal not_aux124 : bit; +signal not_aux120 : bit; +signal not_aux117 : bit; +signal not_aux116 : bit; +signal not_aux115 : bit; +signal not_aux113 : bit; +signal not_aux112 : bit; +signal not_aux11 : bit; +signal not_aux109 : bit; +signal not_aux108 : bit; +signal not_aux107 : bit; +signal not_aux105 : bit; +signal not_aux104 : bit; +signal not_aux102 : bit; +signal not_aux101 : bit; +signal not_aux100 : bit; +signal not_aux10 : bit; +signal not_aux0 : bit; +signal noa2ao222_x1_sig : bit; +signal noa2a2a2a24_x1_sig : bit; +signal noa2a2a23_x1_sig : bit; +signal noa22_x1_sig : bit; +signal noa22_x1_9_sig : bit; +signal noa22_x1_8_sig : bit; +signal noa22_x1_7_sig : bit; +signal noa22_x1_6_sig : bit; +signal noa22_x1_5_sig : bit; +signal noa22_x1_4_sig : bit; +signal noa22_x1_3_sig : bit; +signal noa22_x1_2_sig : bit; +signal noa22_x1_10_sig : bit; +signal no4_x1_sig : bit; +signal no4_x1_4_sig : bit; +signal no4_x1_3_sig : bit; +signal no4_x1_2_sig : bit; +signal no3_x1_sig : bit; +signal no3_x1_9_sig : bit; +signal no3_x1_8_sig : bit; +signal no3_x1_7_sig : bit; +signal no3_x1_6_sig : bit; +signal no3_x1_5_sig : bit; +signal no3_x1_4_sig : bit; +signal no3_x1_3_sig : bit; +signal no3_x1_2_sig : bit; +signal no3_x1_17_sig : bit; +signal no3_x1_16_sig : bit; +signal no3_x1_15_sig : bit; +signal no3_x1_14_sig : bit; +signal no3_x1_13_sig : bit; +signal no3_x1_12_sig : bit; +signal no3_x1_11_sig : bit; +signal no3_x1_10_sig : bit; +signal no2_x1_sig : bit; +signal no2_x1_9_sig : bit; +signal no2_x1_8_sig : bit; +signal no2_x1_7_sig : bit; +signal no2_x1_6_sig : bit; +signal no2_x1_5_sig : bit; +signal no2_x1_4_sig : bit; +signal no2_x1_3_sig : bit; +signal no2_x1_2_sig : bit; +signal no2_x1_27_sig : bit; +signal no2_x1_26_sig : bit; +signal no2_x1_25_sig : bit; +signal no2_x1_24_sig : bit; +signal no2_x1_23_sig : bit; +signal no2_x1_22_sig : bit; +signal no2_x1_21_sig : bit; +signal no2_x1_20_sig : bit; +signal no2_x1_19_sig : bit; +signal no2_x1_18_sig : bit; +signal no2_x1_17_sig : bit; +signal no2_x1_16_sig : bit; +signal no2_x1_15_sig : bit; +signal no2_x1_14_sig : bit; +signal no2_x1_13_sig : bit; +signal no2_x1_12_sig : bit; +signal no2_x1_11_sig : bit; +signal no2_x1_10_sig : bit; +signal nmx2_x1_sig : bit; +signal nao2o22_x1_sig : bit; +signal nao2o22_x1_3_sig : bit; +signal nao2o22_x1_2_sig : bit; +signal nao22_x1_sig : bit; +signal nao22_x1_9_sig : bit; +signal nao22_x1_8_sig : bit; +signal nao22_x1_7_sig : bit; +signal nao22_x1_6_sig : bit; +signal nao22_x1_5_sig : bit; +signal nao22_x1_4_sig : bit; +signal nao22_x1_3_sig : bit; +signal nao22_x1_2_sig : bit; +signal nao22_x1_25_sig : bit; +signal nao22_x1_24_sig : bit; +signal nao22_x1_23_sig : bit; +signal nao22_x1_22_sig : bit; +signal nao22_x1_21_sig : bit; +signal nao22_x1_20_sig : bit; +signal nao22_x1_19_sig : bit; +signal nao22_x1_18_sig : bit; +signal nao22_x1_17_sig : bit; +signal nao22_x1_16_sig : bit; +signal nao22_x1_15_sig : bit; +signal nao22_x1_14_sig : bit; +signal nao22_x1_13_sig : bit; +signal nao22_x1_12_sig : bit; +signal nao22_x1_11_sig : bit; +signal nao22_x1_10_sig : bit; +signal na4_x1_sig : bit; +signal na4_x1_6_sig : bit; +signal na4_x1_5_sig : bit; +signal na4_x1_4_sig : bit; +signal na4_x1_3_sig : bit; +signal na4_x1_2_sig : bit; +signal na3_x1_sig : bit; +signal na3_x1_9_sig : bit; +signal na3_x1_8_sig : bit; +signal na3_x1_7_sig : bit; +signal na3_x1_6_sig : bit; +signal na3_x1_5_sig : bit; +signal na3_x1_4_sig : bit; +signal na3_x1_3_sig : bit; +signal na3_x1_2_sig : bit; +signal na3_x1_21_sig : bit; +signal na3_x1_20_sig : bit; +signal na3_x1_19_sig : bit; +signal na3_x1_18_sig : bit; +signal na3_x1_17_sig : bit; +signal na3_x1_16_sig : bit; +signal na3_x1_15_sig : bit; +signal na3_x1_14_sig : bit; +signal na3_x1_13_sig : bit; +signal na3_x1_12_sig : bit; +signal na3_x1_11_sig : bit; +signal na3_x1_10_sig : bit; +signal na2_x1_sig : bit; +signal na2_x1_9_sig : bit; +signal na2_x1_8_sig : bit; +signal na2_x1_7_sig : bit; +signal na2_x1_6_sig : bit; +signal na2_x1_5_sig : bit; +signal na2_x1_4_sig : bit; +signal na2_x1_3_sig : bit; +signal na2_x1_2_sig : bit; +signal na2_x1_29_sig : bit; +signal na2_x1_28_sig : bit; +signal na2_x1_27_sig : bit; +signal na2_x1_26_sig : bit; +signal na2_x1_25_sig : bit; +signal na2_x1_24_sig : bit; +signal na2_x1_23_sig : bit; +signal na2_x1_22_sig : bit; +signal na2_x1_21_sig : bit; +signal na2_x1_20_sig : bit; +signal na2_x1_19_sig : bit; +signal na2_x1_18_sig : bit; +signal na2_x1_17_sig : bit; +signal na2_x1_16_sig : bit; +signal na2_x1_15_sig : bit; +signal na2_x1_14_sig : bit; +signal na2_x1_13_sig : bit; +signal na2_x1_12_sig : bit; +signal na2_x1_11_sig : bit; +signal na2_x1_10_sig : bit; +signal mx3_x2_sig : bit; +signal mx3_x2_7_sig : bit; +signal mx3_x2_6_sig : bit; +signal mx3_x2_5_sig : bit; +signal mx3_x2_4_sig : bit; +signal mx3_x2_3_sig : bit; +signal mx3_x2_2_sig : bit; +signal mx2_x2_sig : bit; +signal mx2_x2_2_sig : bit; +signal inv_x2_sig : bit; +signal inv_x2_9_sig : bit; +signal inv_x2_8_sig : bit; +signal inv_x2_7_sig : bit; +signal inv_x2_6_sig : bit; +signal inv_x2_5_sig : bit; +signal inv_x2_4_sig : bit; +signal inv_x2_3_sig : bit; +signal inv_x2_2_sig : bit; +signal inv_x2_18_sig : bit; +signal inv_x2_17_sig : bit; +signal inv_x2_16_sig : bit; +signal inv_x2_15_sig : bit; +signal inv_x2_14_sig : bit; +signal inv_x2_13_sig : bit; +signal inv_x2_12_sig : bit; +signal inv_x2_11_sig : bit; +signal inv_x2_10_sig : bit; +signal aux97 : bit; +signal aux96 : bit; +signal aux90 : bit; +signal aux9 : bit; +signal aux87 : bit; +signal aux86 : bit; +signal aux83 : bit; +signal aux8 : bit; +signal aux76 : bit; +signal aux65 : bit; +signal aux58 : bit; +signal aux57 : bit; +signal aux56 : bit; +signal aux54 : bit; +signal aux49 : bit; +signal aux47 : bit; +signal aux43 : bit; +signal aux36 : bit; +signal aux30 : bit; +signal aux3 : bit; +signal aux28 : bit; +signal aux25 : bit; +signal aux21 : bit; +signal aux20 : bit; +signal aux2 : bit; +signal aux138 : bit; +signal aux137 : bit; +signal aux136 : bit; +signal aux135 : bit; +signal aux125 : bit; +signal aux122 : bit; +signal aux118 : bit; +signal aux11 : bit; +signal aux108 : bit; +signal aux106 : bit; +signal aux105 : bit; +signal aux10 : bit; +signal aux1 : bit; +signal ao2o22_x2_sig : bit; +signal ao2o22_x2_3_sig : bit; +signal ao2o22_x2_2_sig : bit; +signal ao22_x2_sig : bit; +signal ao22_x2_6_sig : bit; +signal ao22_x2_5_sig : bit; +signal ao22_x2_4_sig : bit; +signal ao22_x2_3_sig : bit; +signal ao22_x2_2_sig : bit; +signal an12_x1_sig : bit; +signal an12_x1_6_sig : bit; +signal an12_x1_5_sig : bit; +signal an12_x1_4_sig : bit; +signal an12_x1_3_sig : bit; +signal an12_x1_2_sig : bit; +signal a4_x2_sig : bit; +signal a4_x2_6_sig : bit; +signal a4_x2_5_sig : bit; +signal a4_x2_4_sig : bit; +signal a4_x2_3_sig : bit; +signal a4_x2_2_sig : bit; +signal a3_x2_sig : bit; +signal a3_x2_7_sig : bit; +signal a3_x2_6_sig : bit; +signal a3_x2_5_sig : bit; +signal a3_x2_4_sig : bit; +signal a3_x2_3_sig : bit; +signal a3_x2_2_sig : bit; +signal a2_x2_sig : bit; +signal a2_x2_9_sig : bit; +signal a2_x2_8_sig : bit; +signal a2_x2_7_sig : bit; +signal a2_x2_6_sig : bit; +signal a2_x2_5_sig : bit; +signal a2_x2_4_sig : bit; +signal a2_x2_3_sig : bit; +signal a2_x2_2_sig : bit; +signal a2_x2_19_sig : bit; +signal a2_x2_18_sig : bit; +signal a2_x2_17_sig : bit; +signal a2_x2_16_sig : bit; +signal a2_x2_15_sig : bit; +signal a2_x2_14_sig : bit; +signal a2_x2_13_sig : bit; +signal a2_x2_12_sig : bit; +signal a2_x2_11_sig : bit; +signal a2_x2_10_sig : bit; + +begin + +not_aux126_ins : nxr2_x1 + port map ( + i0 => aux108, + i1 => aux36, + nq => not_aux126, + vdd => vdd, + vss => vss + ); + +not_aux128_ins : nxr2_x1 + port map ( + i0 => aux108, + i1 => aux43, + nq => not_aux128, + vdd => vdd, + vss => vss + ); + +not_aux129_ins : o2_x2 + port map ( + i0 => r(1), + i1 => not_aux108, + q => not_aux129, + vdd => vdd, + vss => vss + ); + +not_aux130_ins : na2_x1 + port map ( + i0 => r(1), + i1 => not_aux108, + nq => not_aux130, + vdd => vdd, + vss => vss + ); + +not_aux131_ins : nxr2_x1 + port map ( + i0 => aux49, + i1 => aux108, + nq => not_aux131, + vdd => vdd, + vss => vss + ); + +not_aux132_ins : nxr2_x1 + port map ( + i0 => aux108, + i1 => aux30, + nq => not_aux132, + vdd => vdd, + vss => vss + ); + +not_aux133_ins : a2_x2 + port map ( + i0 => not_aux22, + i1 => not_aux60, + q => not_aux133, + vdd => vdd, + vss => vss + ); + +not_aux127_ins : nxr2_x1 + port map ( + i0 => aux108, + i1 => i(0), + nq => not_aux127, + vdd => vdd, + vss => vss + ); + +nxr2_x1_ins : nxr2_x1 + port map ( + i0 => s(0), + i1 => cin, + nq => nxr2_x1_sig, + vdd => vdd, + vss => vss + ); + +not_aux124_ins : a2_x2 + port map ( + i0 => nxr2_x1_sig, + i1 => not_i(0), + q => not_aux124, + vdd => vdd, + vss => vss + ); + +not_aux115_ins : o2_x2 + port map ( + i0 => not_aux101, + i1 => not_s(1), + q => not_aux115, + vdd => vdd, + vss => vss + ); + +not_aux116_ins : o2_x2 + port map ( + i0 => not_aux102, + i1 => not_s(2), + q => not_aux116, + vdd => vdd, + vss => vss + ); + +not_aux117_ins : a2_x2 + port map ( + i0 => not_aux8, + i1 => not_s(3), + q => not_aux117, + vdd => vdd, + vss => vss + ); + +not_aux120_ins : a2_x2 + port map ( + i0 => not_aux64, + i1 => not_aux57, + q => not_aux120, + vdd => vdd, + vss => vss + ); + +not_aux104_ins : o2_x2 + port map ( + i0 => not_s(0), + i1 => not_aux54, + q => not_aux104, + vdd => vdd, + vss => vss + ); + +not_aux105_ins : inv_x2 + port map ( + i => aux105, + nq => not_aux105, + vdd => vdd, + vss => vss + ); + +not_aux107_ins : a2_x2 + port map ( + i0 => not_aux8, + i1 => not_aux57, + q => not_aux107, + vdd => vdd, + vss => vss + ); + +not_aux108_ins : inv_x2 + port map ( + i => aux108, + nq => not_aux108, + vdd => vdd, + vss => vss + ); + +not_aux109_ins : a2_x2 + port map ( + i0 => not_aux2, + i1 => not_aux57, + q => not_aux109, + vdd => vdd, + vss => vss + ); + +o2_x2_ins : o2_x2 + port map ( + i0 => not_aux10, + i1 => not_i(0), + q => o2_x2_sig, + vdd => vdd, + vss => vss + ); + +not_aux112_ins : oa22_x2 + port map ( + i0 => o2_x2_sig, + i1 => not_s(3), + i2 => aux8, + q => not_aux112, + vdd => vdd, + vss => vss + ); + +not_aux113_ins : o2_x2 + port map ( + i0 => not_aux80, + i1 => not_i(0), + q => not_aux113, + vdd => vdd, + vss => vss + ); + +not_aux100_ins : na2_x1 + port map ( + i0 => not_aux55, + i1 => not_s(3), + nq => not_aux100, + vdd => vdd, + vss => vss + ); + +not_aux101_ins : nxr2_x1 + port map ( + i0 => i(0), + i1 => r(1), + nq => not_aux101, + vdd => vdd, + vss => vss + ); + +not_aux102_ins : nxr2_x1 + port map ( + i0 => i(0), + i1 => r(2), + nq => not_aux102, + vdd => vdd, + vss => vss + ); + +not_aux15_ins : nao22_x1 + port map ( + i0 => not_aux13, + i1 => not_r(1), + i2 => aux9, + nq => not_aux15, + vdd => vdd, + vss => vss + ); + +not_aux7_ins : nao22_x1 + port map ( + i0 => not_aux5, + i1 => r(1), + i2 => aux1, + nq => not_aux7, + vdd => vdd, + vss => vss + ); + +not_aux13_ins : nao22_x1 + port map ( + i0 => not_aux11, + i1 => cin, + i2 => aux10, + nq => not_aux13, + vdd => vdd, + vss => vss + ); + +not_aux5_ins : nao22_x1 + port map ( + i0 => not_aux3, + i1 => cin, + i2 => aux2, + nq => not_aux5, + vdd => vdd, + vss => vss + ); + +inv_x2_ins : inv_x2 + port map ( + i => aux49, + nq => inv_x2_sig, + vdd => vdd, + vss => vss + ); + +no4_x1_ins : no4_x1 + port map ( + i0 => not_r(1), + i1 => r(3), + i2 => inv_x2_sig, + i3 => s(3), + nq => no4_x1_sig, + vdd => vdd, + vss => vss + ); + +a4_x2_ins : a4_x2 + port map ( + i0 => not_r(1), + i1 => r(3), + i2 => s(3), + i3 => not_aux43, + q => a4_x2_sig, + vdd => vdd, + vss => vss + ); + +not_aux53_ins : no2_x1 + port map ( + i0 => a4_x2_sig, + i1 => no4_x1_sig, + nq => not_aux53, + vdd => vdd, + vss => vss + ); + +not_aux43_ins : inv_x2 + port map ( + i => aux43, + nq => not_aux43, + vdd => vdd, + vss => vss + ); + +not_aux47_ins : inv_x2 + port map ( + i => aux47, + nq => not_aux47, + vdd => vdd, + vss => vss + ); + +not_aux17_ins : o2_x2 + port map ( + i0 => s(3), + i1 => not_aux16, + q => not_aux17, + vdd => vdd, + vss => vss + ); + +inv_x2_2_ins : inv_x2 + port map ( + i => aux36, + nq => inv_x2_2_sig, + vdd => vdd, + vss => vss + ); + +no4_x1_2_ins : no4_x1 + port map ( + i0 => not_r(1), + i1 => r(3), + i2 => inv_x2_2_sig, + i3 => not_s(3), + nq => no4_x1_2_sig, + vdd => vdd, + vss => vss + ); + +a4_x2_2_ins : a4_x2 + port map ( + i0 => not_s(3), + i1 => r(3), + i2 => not_aux30, + i3 => not_r(1), + q => a4_x2_2_sig, + vdd => vdd, + vss => vss + ); + +not_aux40_ins : no2_x1 + port map ( + i0 => a4_x2_2_sig, + i1 => no4_x1_2_sig, + nq => not_aux40, + vdd => vdd, + vss => vss + ); + +not_aux30_ins : inv_x2 + port map ( + i => aux30, + nq => not_aux30, + vdd => vdd, + vss => vss + ); + +not_aux34_ins : o2_x2 + port map ( + i0 => not_aux28, + i1 => not_i(0), + q => not_aux34, + vdd => vdd, + vss => vss + ); + +not_aux26_ins : o2_x2 + port map ( + i0 => s(0), + i1 => cin, + q => not_aux26, + vdd => vdd, + vss => vss + ); + +not_aux22_ins : o2_x2 + port map ( + i0 => s(3), + i1 => not_aux21, + q => not_aux22, + vdd => vdd, + vss => vss + ); + +not_aux54_ins : inv_x2 + port map ( + i => aux54, + nq => not_aux54, + vdd => vdd, + vss => vss + ); + +not_aux28_ins : inv_x2 + port map ( + i => aux28, + nq => not_aux28, + vdd => vdd, + vss => vss + ); + +not_aux58_ins : inv_x2 + port map ( + i => aux58, + nq => not_aux58, + vdd => vdd, + vss => vss + ); + +not_aux62_ins : o2_x2 + port map ( + i0 => not_aux61, + i1 => not_s(1), + q => not_aux62, + vdd => vdd, + vss => vss + ); + +not_aux61_ins : xr2_x1 + port map ( + i0 => r(1), + i1 => r(2), + q => not_aux61, + vdd => vdd, + vss => vss + ); + +not_aux67_ins : o2_x2 + port map ( + i0 => not_aux66, + i1 => not_r(2), + q => not_aux67, + vdd => vdd, + vss => vss + ); + +not_aux134_ins : o2_x2 + port map ( + i0 => r(2), + i1 => not_s(1), + q => not_aux134, + vdd => vdd, + vss => vss + ); + +not_aux70_ins : no2_x1 + port map ( + i0 => not_aux64, + i1 => not_r(1), + nq => not_aux70, + vdd => vdd, + vss => vss + ); + +not_aux71_ins : na2_x1 + port map ( + i0 => r(3), + i1 => not_aux64, + nq => not_aux71, + vdd => vdd, + vss => vss + ); + +not_aux68_ins : o2_x2 + port map ( + i0 => s(3), + i1 => not_r(3), + q => not_aux68, + vdd => vdd, + vss => vss + ); + +not_aux79_ins : a2_x2 + port map ( + i0 => i(0), + i1 => r(1), + q => not_aux79, + vdd => vdd, + vss => vss + ); + +not_aux73_ins : o3_x2 + port map ( + i0 => r(3), + i1 => not_aux64, + i2 => not_s(3), + q => not_aux73, + vdd => vdd, + vss => vss + ); + +not_aux74_ins : o2_x2 + port map ( + i0 => not_aux21, + i1 => not_s(3), + q => not_aux74, + vdd => vdd, + vss => vss + ); + +not_aux80_ins : no2_x1 + port map ( + i0 => r(3), + i1 => s(3), + nq => not_aux80, + vdd => vdd, + vss => vss + ); + +not_aux85_ins : na2_x1 + port map ( + i0 => i(0), + i1 => s(3), + nq => not_aux85, + vdd => vdd, + vss => vss + ); + +not_aux86_ins : inv_x2 + port map ( + i => aux86, + nq => not_aux86, + vdd => vdd, + vss => vss + ); + +not_aux78_ins : nao22_x1 + port map ( + i0 => not_r(0), + i1 => cin, + i2 => aux76, + nq => not_aux78, + vdd => vdd, + vss => vss + ); + +not_aux90_ins : inv_x2 + port map ( + i => aux90, + nq => not_aux90, + vdd => vdd, + vss => vss + ); + +a3_x2_ins : a3_x2 + port map ( + i0 => not_r(1), + i1 => not_aux95, + i2 => aux96, + q => a3_x2_sig, + vdd => vdd, + vss => vss + ); + +oa22_x2_ins : oa22_x2 + port map ( + i0 => not_aux57, + i1 => not_aux16, + i2 => a3_x2_sig, + q => oa22_x2_sig, + vdd => vdd, + vss => vss + ); + +o2_x2_3_ins : o2_x2 + port map ( + i0 => not_aux95, + i1 => not_r(1), + q => o2_x2_3_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_2_ins : a3_x2 + port map ( + i0 => r(2), + i1 => aux96, + i2 => o2_x2_3_sig, + q => a3_x2_2_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_ins : no3_x1 + port map ( + i0 => not_aux92, + i1 => not_aux65, + i2 => r(2), + nq => no3_x1_sig, + vdd => vdd, + vss => vss + ); + +o2_x2_2_ins : o2_x2 + port map ( + i0 => no3_x1_sig, + i1 => a3_x2_2_sig, + q => o2_x2_2_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_2_ins : no3_x1 + port map ( + i0 => not_r(1), + i1 => not_aux92, + i2 => not_aux64, + nq => no3_x1_2_sig, + vdd => vdd, + vss => vss + ); + +oa22_x2_2_ins : oa22_x2 + port map ( + i0 => not_aux60, + i1 => not_aux21, + i2 => no3_x1_2_sig, + q => oa22_x2_2_sig, + vdd => vdd, + vss => vss + ); + +oa2a2a23_x2_ins : oa2a2a23_x2 + port map ( + i0 => oa22_x2_2_sig, + i1 => not_r(2), + i2 => not_s(1), + i3 => o2_x2_2_sig, + i4 => oa22_x2_sig, + i5 => r(2), + q => oa2a2a23_x2_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_ins : na2_x1 + port map ( + i0 => not_aux97, + i1 => not_aux66, + nq => na2_x1_sig, + vdd => vdd, + vss => vss + ); + +ao22_x2_2_ins : ao22_x2 + port map ( + i0 => not_aux82, + i1 => not_r(0), + i2 => aux76, + q => ao22_x2_2_sig, + vdd => vdd, + vss => vss + ); + +ao22_x2_ins : ao22_x2 + port map ( + i0 => ao22_x2_2_sig, + i1 => na2_x1_sig, + i2 => not_r(2), + q => ao22_x2_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_3_ins : inv_x2 + port map ( + i => aux87, + nq => inv_x2_3_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_2_ins : na3_x1 + port map ( + i0 => not_aux98, + i1 => not_aux97, + i2 => inv_x2_3_sig, + nq => na3_x1_2_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_ins : a2_x2 + port map ( + i0 => na3_x1_2_sig, + i1 => r(2), + q => a2_x2_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_ins : nao22_x1 + port map ( + i0 => a2_x2_sig, + i1 => ao22_x2_sig, + i2 => not_s(1), + nq => nao22_x1_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_3_ins : na2_x1 + port map ( + i0 => r(1), + i1 => r(2), + nq => na2_x1_3_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_4_ins : na2_x1 + port map ( + i0 => i(0), + i1 => not_s(3), + nq => na2_x1_4_sig, + vdd => vdd, + vss => vss + ); + +oa22_x2_3_ins : oa22_x2 + port map ( + i0 => na2_x1_4_sig, + i1 => not_aux64, + i2 => na2_x1_3_sig, + q => oa22_x2_3_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_2_ins : nao22_x1 + port map ( + i0 => not_aux95, + i1 => aux56, + i2 => aux137, + nq => nao22_x1_2_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_3_ins : na3_x1 + port map ( + i0 => not_aux97, + i1 => nao22_x1_2_sig, + i2 => oa22_x2_3_sig, + nq => na3_x1_3_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_2_ins : na2_x1 + port map ( + i0 => s(1), + i1 => na3_x1_3_sig, + nq => na2_x1_2_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_ins : na3_x1 + port map ( + i0 => s(2), + i1 => na2_x1_2_sig, + i2 => nao22_x1_sig, + nq => na3_x1_sig, + vdd => vdd, + vss => vss + ); + +not_aux99_ins : a2_x2 + port map ( + i0 => na3_x1_sig, + i1 => oa2a2a23_x2_sig, + q => not_aux99, + vdd => vdd, + vss => vss + ); + +not_aux21_ins : inv_x2 + port map ( + i => aux21, + nq => not_aux21, + vdd => vdd, + vss => vss + ); + +not_aux60_ins : na2_x1 + port map ( + i0 => r(3), + i1 => s(3), + nq => not_aux60, + vdd => vdd, + vss => vss + ); + +not_aux16_ins : na2_x1 + port map ( + i0 => i(0), + i1 => r(3), + nq => not_aux16, + vdd => vdd, + vss => vss + ); + +not_aux57_ins : inv_x2 + port map ( + i => aux57, + nq => not_aux57, + vdd => vdd, + vss => vss + ); + +not_aux92_ins : a2_x2 + port map ( + i0 => s(3), + i1 => not_aux8, + q => not_aux92, + vdd => vdd, + vss => vss + ); + +not_aux8_ins : inv_x2 + port map ( + i => aux8, + nq => not_aux8, + vdd => vdd, + vss => vss + ); + +not_aux65_ins : inv_x2 + port map ( + i => aux65, + nq => not_aux65, + vdd => vdd, + vss => vss + ); + +not_aux0_ins : o2_x2 + port map ( + i0 => r(3), + i1 => not_i(0), + q => not_aux0, + vdd => vdd, + vss => vss + ); + +not_aux66_ins : o2_x2 + port map ( + i0 => r(1), + i1 => not_i(0), + q => not_aux66, + vdd => vdd, + vss => vss + ); + +not_aux84_ins : na2_x1 + port map ( + i0 => not_aux75, + i1 => not_i(0), + nq => not_aux84, + vdd => vdd, + vss => vss + ); + +not_aux75_ins : o2_x2 + port map ( + i0 => cin, + i1 => not_s(0), + q => not_aux75, + vdd => vdd, + vss => vss + ); + +not_aux82_ins : a2_x2 + port map ( + i0 => cin, + i1 => not_s(0), + q => not_aux82, + vdd => vdd, + vss => vss + ); + +not_aux98_ins : o2_x2 + port map ( + i0 => i(0), + i1 => not_r(1), + q => not_aux98, + vdd => vdd, + vss => vss + ); + +not_aux95_ins : nao22_x1 + port map ( + i0 => not_aux11, + i1 => not_cin, + i2 => aux10, + nq => not_aux95, + vdd => vdd, + vss => vss + ); + +not_aux10_ins : inv_x2 + port map ( + i => aux10, + nq => not_aux10, + vdd => vdd, + vss => vss + ); + +not_aux11_ins : inv_x2 + port map ( + i => aux11, + nq => not_aux11, + vdd => vdd, + vss => vss + ); + +not_aux64_ins : ao22_x2 + port map ( + i0 => not_aux3, + i1 => not_cin, + i2 => aux2, + q => not_aux64, + vdd => vdd, + vss => vss + ); + +not_aux2_ins : inv_x2 + port map ( + i => aux2, + nq => not_aux2, + vdd => vdd, + vss => vss + ); + +not_aux3_ins : inv_x2 + port map ( + i => aux3, + nq => not_aux3, + vdd => vdd, + vss => vss + ); + +not_aux97_ins : inv_x2 + port map ( + i => aux97, + nq => not_aux97, + vdd => vdd, + vss => vss + ); + +not_aux55_ins : nxr2_x1 + port map ( + i0 => i(0), + i1 => r(3), + nq => not_aux55, + vdd => vdd, + vss => vss + ); + +not_cin_ins : inv_x2 + port map ( + i => cin, + nq => not_cin, + vdd => vdd, + vss => vss + ); + +not_i_2_ins : inv_x2 + port map ( + i => i(2), + nq => not_i(2), + vdd => vdd, + vss => vss + ); + +not_i_1_ins : inv_x2 + port map ( + i => i(1), + nq => not_i(1), + vdd => vdd, + vss => vss + ); + +not_i_0_ins : inv_x2 + port map ( + i => i(0), + nq => not_i(0), + vdd => vdd, + vss => vss + ); + +not_r_3_ins : inv_x2 + port map ( + i => r(3), + nq => not_r(3), + vdd => vdd, + vss => vss + ); + +not_r_2_ins : inv_x2 + port map ( + i => r(2), + nq => not_r(2), + vdd => vdd, + vss => vss + ); + +not_r_1_ins : inv_x2 + port map ( + i => r(1), + nq => not_r(1), + vdd => vdd, + vss => vss + ); + +not_r_0_ins : inv_x2 + port map ( + i => r(0), + nq => not_r(0), + vdd => vdd, + vss => vss + ); + +not_s_3_ins : inv_x2 + port map ( + i => s(3), + nq => not_s(3), + vdd => vdd, + vss => vss + ); + +not_s_2_ins : inv_x2 + port map ( + i => s(2), + nq => not_s(2), + vdd => vdd, + vss => vss + ); + +not_s_1_ins : inv_x2 + port map ( + i => s(1), + nq => not_s(1), + vdd => vdd, + vss => vss + ); + +not_s_0_ins : inv_x2 + port map ( + i => s(0), + nq => not_s(0), + vdd => vdd, + vss => vss + ); + +aux138_ins : na2_x1 + port map ( + i0 => r(2), + i1 => not_s(1), + nq => aux138, + vdd => vdd, + vss => vss + ); + +aux137_ins : no2_x1 + port map ( + i0 => r(1), + i1 => r(2), + nq => aux137, + vdd => vdd, + vss => vss + ); + +aux136_ins : no2_x1 + port map ( + i0 => r(2), + i1 => not_r(1), + nq => aux136, + vdd => vdd, + vss => vss + ); + +aux135_ins : a2_x2 + port map ( + i0 => r(2), + i1 => not_r(1), + q => aux135, + vdd => vdd, + vss => vss + ); + +aux125_ins : xr2_x1 + port map ( + i0 => r(1), + i1 => s(1), + q => aux125, + vdd => vdd, + vss => vss + ); + +aux122_ins : xr2_x1 + port map ( + i0 => aux54, + i1 => s(0), + q => aux122, + vdd => vdd, + vss => vss + ); + +aux118_ins : na2_x1 + port map ( + i0 => not_aux0, + i1 => not_s(3), + nq => aux118, + vdd => vdd, + vss => vss + ); + +aux108_ins : na2_x1 + port map ( + i0 => not_aux68, + i1 => not_aux57, + nq => aux108, + vdd => vdd, + vss => vss + ); + +aux106_ins : na2_x1 + port map ( + i0 => not_aux60, + i1 => not_aux0, + nq => aux106, + vdd => vdd, + vss => vss + ); + +aux105_ins : no2_x1 + port map ( + i0 => not_aux55, + i1 => not_s(3), + nq => aux105, + vdd => vdd, + vss => vss + ); + +aux97_ins : no2_x1 + port map ( + i0 => s(3), + i1 => not_aux55, + nq => aux97, + vdd => vdd, + vss => vss + ); + +aux96_ins : na2_x1 + port map ( + i0 => s(3), + i1 => not_aux0, + nq => aux96, + vdd => vdd, + vss => vss + ); + +a2_x2_2_ins : a2_x2 + port map ( + i0 => r(0), + i1 => not_aux75, + q => a2_x2_2_sig, + vdd => vdd, + vss => vss + ); + +aux90_ins : no3_x1 + port map ( + i0 => i(0), + i1 => a2_x2_2_sig, + i2 => not_aux82, + nq => aux90, + vdd => vdd, + vss => vss + ); + +aux87_ins : an12_x1 + port map ( + i0 => not_aux84, + i1 => aux83, + q => aux87, + vdd => vdd, + vss => vss + ); + +aux86_ins : na2_x1 + port map ( + i0 => r(1), + i1 => r(2), + nq => aux86, + vdd => vdd, + vss => vss + ); + +aux83_ins : o2_x2 + port map ( + i0 => r(0), + i1 => not_aux82, + q => aux83, + vdd => vdd, + vss => vss + ); + +aux76_ins : a2_x2 + port map ( + i0 => i(0), + i1 => not_aux75, + q => aux76, + vdd => vdd, + vss => vss + ); + +aux65_ins : na2_x1 + port map ( + i0 => not_aux64, + i1 => not_r(1), + nq => aux65, + vdd => vdd, + vss => vss + ); + +aux58_ins : on12_x1 + port map ( + i0 => not_aux57, + i1 => aux56, + q => aux58, + vdd => vdd, + vss => vss + ); + +aux57_ins : no2_x1 + port map ( + i0 => r(3), + i1 => not_s(3), + nq => aux57, + vdd => vdd, + vss => vss + ); + +aux56_ins : no2_x1 + port map ( + i0 => i(0), + i1 => s(3), + nq => aux56, + vdd => vdd, + vss => vss + ); + +aux54_ins : xr2_x1 + port map ( + i0 => i(0), + i1 => r(0), + q => aux54, + vdd => vdd, + vss => vss + ); + +aux49_ins : ao22_x2 + port map ( + i0 => not_aux28, + i1 => r(0), + i2 => aux47, + q => aux49, + vdd => vdd, + vss => vss + ); + +aux47_ins : a2_x2 + port map ( + i0 => not_aux26, + i1 => not_i(0), + q => aux47, + vdd => vdd, + vss => vss + ); + +na2_x1_5_ins : na2_x1 + port map ( + i0 => r(0), + i1 => not_aux26, + nq => na2_x1_5_sig, + vdd => vdd, + vss => vss + ); + +aux43_ins : na3_x1 + port map ( + i0 => not_i(0), + i1 => na2_x1_5_sig, + i2 => aux28, + nq => aux43, + vdd => vdd, + vss => vss + ); + +aux36_ins : noa22_x1 + port map ( + i0 => not_r(0), + i1 => not_aux26, + i2 => not_aux34, + nq => aux36, + vdd => vdd, + vss => vss + ); + +a2_x2_3_ins : a2_x2 + port map ( + i0 => i(0), + i1 => not_aux26, + q => a2_x2_3_sig, + vdd => vdd, + vss => vss + ); + +aux30_ins : nao22_x1 + port map ( + i0 => not_aux28, + i1 => not_r(0), + i2 => a2_x2_3_sig, + nq => aux30, + vdd => vdd, + vss => vss + ); + +aux28_ins : na2_x1 + port map ( + i0 => s(0), + i1 => cin, + nq => aux28, + vdd => vdd, + vss => vss + ); + +aux25_ins : noa22_x1 + port map ( + i0 => not_r(1), + i1 => not_aux13, + i2 => not_aux22, + nq => aux25, + vdd => vdd, + vss => vss + ); + +aux21_ins : no2_x1 + port map ( + i0 => i(0), + i1 => r(3), + nq => aux21, + vdd => vdd, + vss => vss + ); + +aux20_ins : noa22_x1 + port map ( + i0 => not_aux5, + i1 => r(1), + i2 => not_aux17, + nq => aux20, + vdd => vdd, + vss => vss + ); + +aux11_ins : na2_x1 + port map ( + i0 => s(0), + i1 => r(0), + nq => aux11, + vdd => vdd, + vss => vss + ); + +aux10_ins : na2_x1 + port map ( + i0 => not_s(0), + i1 => not_r(0), + nq => aux10, + vdd => vdd, + vss => vss + ); + +aux9_ins : no2_x1 + port map ( + i0 => not_aux8, + i1 => not_s(3), + nq => aux9, + vdd => vdd, + vss => vss + ); + +aux8_ins : no2_x1 + port map ( + i0 => i(0), + i1 => not_r(3), + nq => aux8, + vdd => vdd, + vss => vss + ); + +aux3_ins : na2_x1 + port map ( + i0 => s(0), + i1 => not_r(0), + nq => aux3, + vdd => vdd, + vss => vss + ); + +aux2_ins : na2_x1 + port map ( + i0 => r(0), + i1 => not_s(0), + nq => aux2, + vdd => vdd, + vss => vss + ); + +aux1_ins : no2_x1 + port map ( + i0 => not_aux0, + i1 => not_s(3), + nq => aux1, + vdd => vdd, + vss => vss + ); + +zero_ins : no4_x1 + port map ( + i0 => alu_out(2), + i1 => alu_out(3), + i2 => alu_out(0), + i3 => alu_out(1), + nq => zero, + vdd => vdd, + vss => vss + ); + +f3_ins : buf_x2 + port map ( + i => alu_out(3), + q => f3, + vdd => vdd, + vss => vss + ); + +no3_x1_3_ins : no3_x1 + port map ( + i0 => not_r(3), + i1 => s(3), + i2 => not_aux86, + nq => no3_x1_3_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_4_ins : a2_x2 + port map ( + i0 => cin, + i1 => not_r(0), + q => a2_x2_4_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_5_ins : a2_x2 + port map ( + i0 => r(0), + i1 => not_i(0), + q => a2_x2_5_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_3_ins : nao22_x1 + port map ( + i0 => a2_x2_5_sig, + i1 => a2_x2_4_sig, + i2 => no3_x1_3_sig, + nq => nao22_x1_3_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_ins : no2_x1 + port map ( + i0 => not_aux90, + i1 => not_r(3), + nq => no2_x1_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_4_ins : inv_x2 + port map ( + i => not_aux0, + nq => inv_x2_4_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_4_ins : nao22_x1 + port map ( + i0 => inv_x2_4_sig, + i1 => no2_x1_sig, + i2 => not_s(3), + nq => nao22_x1_4_sig, + vdd => vdd, + vss => vss + ); + +na4_x1_2_ins : na4_x1 + port map ( + i0 => s(3), + i1 => not_r(3), + i2 => not_aux86, + i3 => aux87, + nq => na4_x1_2_sig, + vdd => vdd, + vss => vss + ); + +na4_x1_ins : na4_x1 + port map ( + i0 => na4_x1_2_sig, + i1 => not_aux78, + i2 => nao22_x1_4_sig, + i3 => nao22_x1_3_sig, + nq => na4_x1_sig, + vdd => vdd, + vss => vss + ); + +o2_x2_4_ins : o2_x2 + port map ( + i0 => r(1), + i1 => not_aux73, + q => o2_x2_4_sig, + vdd => vdd, + vss => vss + ); + +o2_x2_5_ins : o2_x2 + port map ( + i0 => not_aux74, + i1 => not_r(1), + q => o2_x2_5_sig, + vdd => vdd, + vss => vss + ); + +oa22_x2_5_ins : oa22_x2 + port map ( + i0 => o2_x2_5_sig, + i1 => o2_x2_4_sig, + i2 => not_r(2), + q => oa22_x2_5_sig, + vdd => vdd, + vss => vss + ); + +o3_x2_ins : o3_x2 + port map ( + i0 => cin, + i1 => not_aux80, + i2 => not_aux10, + q => o3_x2_sig, + vdd => vdd, + vss => vss + ); + +on12_x1_ins : on12_x1 + port map ( + i0 => o3_x2_sig, + i1 => not_i(0), + q => on12_x1_sig, + vdd => vdd, + vss => vss + ); + +o3_x2_2_ins : o3_x2 + port map ( + i0 => not_aux68, + i1 => r(2), + i2 => not_aux79, + q => o3_x2_2_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_4_ins : na3_x1 + port map ( + i0 => o3_x2_2_sig, + i1 => on12_x1_sig, + i2 => oa22_x2_5_sig, + nq => na3_x1_4_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_5_ins : inv_x2 + port map ( + i => aux83, + nq => inv_x2_5_sig, + vdd => vdd, + vss => vss + ); + +noa22_x1_ins : noa22_x1 + port map ( + i0 => not_aux84, + i1 => r(0), + i2 => inv_x2_5_sig, + nq => noa22_x1_sig, + vdd => vdd, + vss => vss + ); + +o2_x2_6_ins : o2_x2 + port map ( + i0 => s(3), + i1 => not_r(3), + q => o2_x2_6_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_5_ins : nao22_x1 + port map ( + i0 => o2_x2_6_sig, + i1 => noa22_x1_sig, + i2 => not_aux85, + nq => nao22_x1_5_sig, + vdd => vdd, + vss => vss + ); + +oa22_x2_4_ins : oa22_x2 + port map ( + i0 => nao22_x1_5_sig, + i1 => not_r(1), + i2 => na3_x1_4_sig, + q => oa22_x2_4_sig, + vdd => vdd, + vss => vss + ); + +o3_x2_3_ins : o3_x2 + port map ( + i0 => r(1), + i1 => s(3), + i2 => not_aux71, + q => o3_x2_3_sig, + vdd => vdd, + vss => vss + ); + +o2_x2_7_ins : o2_x2 + port map ( + i0 => not_aux73, + i1 => not_r(1), + q => o2_x2_7_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_5_ins : na3_x1 + port map ( + i0 => not_i(0), + i1 => o2_x2_7_sig, + i2 => o3_x2_3_sig, + nq => na3_x1_5_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_6_ins : na2_x1 + port map ( + i0 => not_r(2), + i1 => na3_x1_5_sig, + nq => na2_x1_6_sig, + vdd => vdd, + vss => vss + ); + +o2_x2_8_ins : o2_x2 + port map ( + i0 => s(3), + i1 => not_aux0, + q => o2_x2_8_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_6_ins : na3_x1 + port map ( + i0 => not_aux74, + i1 => not_aux78, + i2 => o2_x2_8_sig, + nq => na3_x1_6_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_7_ins : na2_x1 + port map ( + i0 => r(2), + i1 => na3_x1_6_sig, + nq => na2_x1_7_sig, + vdd => vdd, + vss => vss + ); + +o3_x2_4_ins : o3_x2 + port map ( + i0 => not_aux134, + i1 => not_aux68, + i2 => not_aux70, + q => o3_x2_4_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_4_ins : no3_x1 + port map ( + i0 => not_aux65, + i1 => not_aux57, + i2 => r(2), + nq => no3_x1_4_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_6_ins : inv_x2 + port map ( + i => not_aux67, + nq => inv_x2_6_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_6_ins : nao22_x1 + port map ( + i0 => inv_x2_6_sig, + i1 => no3_x1_4_sig, + i2 => not_s(1), + nq => nao22_x1_6_sig, + vdd => vdd, + vss => vss + ); + +na4_x1_3_ins : na4_x1 + port map ( + i0 => nao22_x1_6_sig, + i1 => o3_x2_4_sig, + i2 => na2_x1_7_sig, + i3 => na2_x1_6_sig, + nq => na4_x1_3_sig, + vdd => vdd, + vss => vss + ); + +mx3_x2_ins : mx3_x2 + port map ( + cmd0 => s(2), + cmd1 => not_s(1), + i0 => na4_x1_3_sig, + i1 => oa22_x2_4_sig, + i2 => na4_x1_sig, + q => mx3_x2_sig, + vdd => vdd, + vss => vss + ); + +an12_x1_ins : an12_x1 + port map ( + i0 => r(2), + i1 => aux25, + q => an12_x1_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_7_ins : a2_x2 + port map ( + i0 => r(2), + i1 => aux20, + q => a2_x2_7_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_7_ins : nao22_x1 + port map ( + i0 => a2_x2_7_sig, + i1 => an12_x1_sig, + i2 => s(1), + nq => nao22_x1_7_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_2_ins : no2_x1 + port map ( + i0 => not_aux7, + i1 => not_r(2), + nq => no2_x1_2_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_3_ins : no2_x1 + port map ( + i0 => r(2), + i1 => not_aux15, + nq => no2_x1_3_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_8_ins : nao22_x1 + port map ( + i0 => no2_x1_3_sig, + i1 => no2_x1_2_sig, + i2 => not_s(1), + nq => nao22_x1_8_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_8_ins : na2_x1 + port map ( + i0 => not_aux22, + i1 => not_aux40, + nq => na2_x1_8_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_9_ins : na2_x1 + port map ( + i0 => not_aux17, + i1 => not_aux53, + nq => na2_x1_9_sig, + vdd => vdd, + vss => vss + ); + +nmx2_x1_ins : nmx2_x1 + port map ( + cmd => r(2), + i0 => na2_x1_9_sig, + i1 => na2_x1_8_sig, + nq => nmx2_x1_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_7_ins : na3_x1 + port map ( + i0 => nmx2_x1_sig, + i1 => nao22_x1_8_sig, + i2 => nao22_x1_7_sig, + nq => na3_x1_7_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_6_ins : a2_x2 + port map ( + i0 => na3_x1_7_sig, + i1 => s(2), + q => a2_x2_6_sig, + vdd => vdd, + vss => vss + ); + +an12_x1_2_ins : an12_x1 + port map ( + i0 => aux9, + i1 => not_aux40, + q => an12_x1_2_sig, + vdd => vdd, + vss => vss + ); + +an12_x1_3_ins : an12_x1 + port map ( + i0 => aux1, + i1 => not_aux53, + q => an12_x1_3_sig, + vdd => vdd, + vss => vss + ); + +ao2o22_x2_ins : ao2o22_x2 + port map ( + i0 => not_r(2), + i1 => an12_x1_3_sig, + i2 => an12_x1_2_sig, + i3 => r(2), + q => ao2o22_x2_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_4_ins : no2_x1 + port map ( + i0 => not_aux15, + i1 => not_r(2), + nq => no2_x1_4_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_5_ins : no2_x1 + port map ( + i0 => r(2), + i1 => not_aux7, + nq => no2_x1_5_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_9_ins : nao22_x1 + port map ( + i0 => no2_x1_5_sig, + i1 => no2_x1_4_sig, + i2 => not_s(1), + nq => nao22_x1_9_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_9_ins : a2_x2 + port map ( + i0 => r(2), + i1 => aux25, + q => a2_x2_9_sig, + vdd => vdd, + vss => vss + ); + +an12_x1_4_ins : an12_x1 + port map ( + i0 => r(2), + i1 => aux20, + q => an12_x1_4_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_10_ins : nao22_x1 + port map ( + i0 => an12_x1_4_sig, + i1 => a2_x2_9_sig, + i2 => s(1), + nq => nao22_x1_10_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_8_ins : na3_x1 + port map ( + i0 => nao22_x1_10_sig, + i1 => nao22_x1_9_sig, + i2 => ao2o22_x2_sig, + nq => na3_x1_8_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_8_ins : a2_x2 + port map ( + i0 => na3_x1_8_sig, + i1 => not_s(2), + q => a2_x2_8_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_6_ins : no2_x1 + port map ( + i0 => not_aux54, + i1 => aux28, + nq => no2_x1_6_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_10_ins : na2_x1 + port map ( + i0 => cin, + i1 => s(1), + nq => na2_x1_10_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_7_ins : no2_x1 + port map ( + i0 => r(1), + i1 => not_aux58, + nq => no2_x1_7_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_10_ins : a2_x2 + port map ( + i0 => r(1), + i1 => not_aux58, + q => a2_x2_10_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_5_ins : no3_x1 + port map ( + i0 => a2_x2_10_sig, + i1 => no2_x1_7_sig, + i2 => na2_x1_10_sig, + nq => no3_x1_5_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_6_ins : no3_x1 + port map ( + i0 => not_s(3), + i1 => not_aux55, + i2 => not_cin, + nq => no3_x1_6_sig, + vdd => vdd, + vss => vss + ); + +no4_x1_3_ins : no4_x1 + port map ( + i0 => no3_x1_6_sig, + i1 => not_i(2), + i2 => no3_x1_5_sig, + i3 => no2_x1_6_sig, + nq => no4_x1_3_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_9_ins : na3_x1 + port map ( + i0 => cin, + i1 => s(2), + i2 => not_aux62, + nq => na3_x1_9_sig, + vdd => vdd, + vss => vss + ); + +xr2_x1_ins : xr2_x1 + port map ( + i0 => aux58, + i1 => r(2), + q => xr2_x1_sig, + vdd => vdd, + vss => vss + ); + +oa22_x2_6_ins : oa22_x2 + port map ( + i0 => xr2_x1_sig, + i1 => not_s(1), + i2 => na3_x1_9_sig, + q => oa22_x2_6_sig, + vdd => vdd, + vss => vss + ); + +oa2ao222_x2_ins : oa2ao222_x2 + port map ( + i0 => oa22_x2_6_sig, + i1 => no4_x1_3_sig, + i2 => a2_x2_8_sig, + i3 => a2_x2_6_sig, + i4 => not_i(2), + q => oa2ao222_x2_sig, + vdd => vdd, + vss => vss + ); + +ovr_ins : mx3_x2 + port map ( + cmd0 => i(1), + cmd1 => not_i(2), + i0 => oa2ao222_x2_sig, + i1 => mx3_x2_sig, + i2 => not_aux99, + q => ovr, + vdd => vdd, + vss => vss + ); + +noa2a2a2a24_x1_ins : noa2a2a2a24_x1 + port map ( + i0 => s(1), + i1 => not_aux101, + i2 => not_aux54, + i3 => s(0), + i4 => s(3), + i5 => not_aux55, + i6 => not_aux102, + i7 => s(2), + nq => noa2a2a2a24_x1_sig, + vdd => vdd, + vss => vss + ); + +an12_x1_5_ins : an12_x1 + port map ( + i0 => noa2a2a2a24_x1_sig, + i1 => i(1), + q => an12_x1_5_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_11_ins : na2_x1 + port map ( + i0 => s(1), + i1 => not_r(1), + nq => na2_x1_11_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_10_ins : na3_x1 + port map ( + i0 => not_s(0), + i1 => not_aux57, + i2 => na2_x1_11_sig, + nq => na3_x1_10_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_11_ins : a2_x2 + port map ( + i0 => na3_x1_10_sig, + i1 => not_i(0), + q => a2_x2_11_sig, + vdd => vdd, + vss => vss + ); + +o3_x2_5_ins : o3_x2 + port map ( + i0 => i(0), + i1 => r(2), + i2 => not_s(2), + q => o3_x2_5_sig, + vdd => vdd, + vss => vss + ); + +on12_x1_2_ins : on12_x1 + port map ( + i0 => o3_x2_5_sig, + i1 => i(2), + q => on12_x1_2_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_8_ins : no2_x1 + port map ( + i0 => i(1), + i1 => i(2), + nq => no2_x1_8_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_12_ins : na2_x1 + port map ( + i0 => not_aux101, + i1 => not_s(1), + nq => na2_x1_12_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_13_ins : na2_x1 + port map ( + i0 => not_aux102, + i1 => not_s(2), + nq => na2_x1_13_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_14_ins : na2_x1 + port map ( + i0 => not_s(0), + i1 => not_aux54, + nq => na2_x1_14_sig, + vdd => vdd, + vss => vss + ); + +na4_x1_4_ins : na4_x1 + port map ( + i0 => na2_x1_14_sig, + i1 => not_aux100, + i2 => na2_x1_13_sig, + i3 => na2_x1_12_sig, + nq => na4_x1_4_sig, + vdd => vdd, + vss => vss + ); + +np_ins : oa2ao222_x2 + port map ( + i0 => na4_x1_4_sig, + i1 => no2_x1_8_sig, + i2 => on12_x1_2_sig, + i3 => a2_x2_11_sig, + i4 => an12_x1_5_sig, + q => np, + vdd => vdd, + vss => vss + ); + +a2_x2_12_ins : a2_x2 + port map ( + i0 => not_aux62, + i1 => not_s(2), + q => a2_x2_12_sig, + vdd => vdd, + vss => vss + ); + +o2_x2_9_ins : o2_x2 + port map ( + i0 => not_aux16, + i1 => not_s(3), + q => o2_x2_9_sig, + vdd => vdd, + vss => vss + ); + +oa22_x2_7_ins : oa22_x2 + port map ( + i0 => o2_x2_9_sig, + i1 => a2_x2_12_sig, + i2 => not_i(2), + q => oa22_x2_7_sig, + vdd => vdd, + vss => vss + ); + +ao2o22_x2_2_ins : ao2o22_x2 + port map ( + i0 => r(2), + i1 => not_aux60, + i2 => not_aux113, + i3 => not_r(2), + q => ao2o22_x2_2_sig, + vdd => vdd, + vss => vss + ); + +an12_x1_6_ins : an12_x1 + port map ( + i0 => not_s(3), + i1 => aux135, + q => an12_x1_6_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_7_ins : inv_x2 + port map ( + i => aux136, + nq => inv_x2_7_sig, + vdd => vdd, + vss => vss + ); + +noa22_x1_3_ins : noa22_x1 + port map ( + i0 => not_aux16, + i1 => not_s(3), + i2 => inv_x2_7_sig, + nq => noa22_x1_3_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_11_ins : nao22_x1 + port map ( + i0 => noa22_x1_3_sig, + i1 => an12_x1_6_sig, + i2 => s(1), + nq => nao22_x1_11_sig, + vdd => vdd, + vss => vss + ); + +noa22_x1_2_ins : noa22_x1 + port map ( + i0 => nao22_x1_11_sig, + i1 => ao2o22_x2_2_sig, + i2 => oa22_x2_7_sig, + nq => noa22_x1_2_sig, + vdd => vdd, + vss => vss + ); + +on12_x1_3_ins : on12_x1 + port map ( + i0 => aux137, + i1 => not_aux2, + q => on12_x1_3_sig, + vdd => vdd, + vss => vss + ); + +o2_x2_10_ins : o2_x2 + port map ( + i0 => not_aux79, + i1 => not_aux57, + q => o2_x2_10_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_12_ins : na3_x1 + port map ( + i0 => aux86, + i1 => o2_x2_10_sig, + i2 => on12_x1_3_sig, + nq => na3_x1_12_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_15_ins : na2_x1 + port map ( + i0 => not_s(1), + i1 => na3_x1_12_sig, + nq => na2_x1_15_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_9_ins : no2_x1 + port map ( + i0 => not_aux112, + i1 => not_r(2), + nq => no2_x1_9_sig, + vdd => vdd, + vss => vss + ); + +o2_x2_11_ins : o2_x2 + port map ( + i0 => i(0), + i1 => r(2), + q => o2_x2_11_sig, + vdd => vdd, + vss => vss + ); + +noa22_x1_4_ins : noa22_x1 + port map ( + i0 => not_aux109, + i1 => r(1), + i2 => o2_x2_11_sig, + nq => noa22_x1_4_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_12_ins : nao22_x1 + port map ( + i0 => noa22_x1_4_sig, + i1 => no2_x1_9_sig, + i2 => s(1), + nq => nao22_x1_12_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_11_ins : na3_x1 + port map ( + i0 => not_s(2), + i1 => nao22_x1_12_sig, + i2 => na2_x1_15_sig, + nq => na3_x1_11_sig, + vdd => vdd, + vss => vss + ); + +o2_x2_12_ins : o2_x2 + port map ( + i0 => not_aux112, + i1 => not_r(1), + q => o2_x2_12_sig, + vdd => vdd, + vss => vss + ); + +o2_x2_13_ins : o2_x2 + port map ( + i0 => r(1), + i1 => not_aux109, + q => o2_x2_13_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_4_ins : a3_x2 + port map ( + i0 => r(2), + i1 => o2_x2_13_sig, + i2 => o2_x2_12_sig, + q => a3_x2_4_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_8_ins : inv_x2 + port map ( + i => not_aux66, + nq => inv_x2_8_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_13_ins : nao22_x1 + port map ( + i0 => inv_x2_8_sig, + i1 => a3_x2_4_sig, + i2 => not_s(1), + nq => nao22_x1_13_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_8_ins : no3_x1 + port map ( + i0 => not_i(0), + i1 => r(0), + i2 => s(0), + nq => no3_x1_8_sig, + vdd => vdd, + vss => vss + ); + +a4_x2_3_ins : a4_x2 + port map ( + i0 => not_aux2, + i1 => not_aux86, + i2 => not_aux108, + i3 => not_aux16, + q => a4_x2_3_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_7_ins : no3_x1 + port map ( + i0 => aux97, + i1 => a4_x2_3_sig, + i2 => no3_x1_8_sig, + nq => no3_x1_7_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_3_ins : a3_x2 + port map ( + i0 => no3_x1_7_sig, + i1 => nao22_x1_13_sig, + i2 => na3_x1_11_sig, + q => a3_x2_3_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_16_ins : na2_x1 + port map ( + i0 => s(1), + i1 => not_aux61, + nq => na2_x1_16_sig, + vdd => vdd, + vss => vss + ); + +a4_x2_4_ins : a4_x2 + port map ( + i0 => aux3, + i1 => i(0), + i2 => not_aux57, + i3 => r(2), + q => a4_x2_4_sig, + vdd => vdd, + vss => vss + ); + +a4_x2_5_ins : a4_x2 + port map ( + i0 => not_r(2), + i1 => not_i(0), + i2 => not_aux60, + i3 => aux11, + q => a4_x2_5_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_5_ins : a3_x2 + port map ( + i0 => not_aux104, + i1 => not_aux105, + i2 => not_s(2), + q => a3_x2_5_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_9_ins : no3_x1 + port map ( + i0 => not_s(0), + i1 => not_s(3), + i2 => r(0), + nq => no3_x1_9_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_17_ins : na2_x1 + port map ( + i0 => i(0), + i1 => r(1), + nq => na2_x1_17_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_10_ins : no2_x1 + port map ( + i0 => na2_x1_17_sig, + i1 => no3_x1_9_sig, + nq => no2_x1_10_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_11_ins : no2_x1 + port map ( + i0 => i(0), + i1 => r(1), + nq => no2_x1_11_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_13_ins : na3_x1 + port map ( + i0 => r(0), + i1 => s(0), + i2 => s(3), + nq => na3_x1_13_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_13_ins : a2_x2 + port map ( + i0 => na3_x1_13_sig, + i1 => no2_x1_11_sig, + q => a2_x2_13_sig, + vdd => vdd, + vss => vss + ); + +o3_x2_6_ins : o3_x2 + port map ( + i0 => not_s(1), + i1 => a2_x2_13_sig, + i2 => no2_x1_10_sig, + q => o3_x2_6_sig, + vdd => vdd, + vss => vss + ); + +noa2ao222_x1_ins : noa2ao222_x1 + port map ( + i0 => o3_x2_6_sig, + i1 => a3_x2_5_sig, + i2 => a4_x2_5_sig, + i3 => a4_x2_4_sig, + i4 => na2_x1_16_sig, + nq => noa2ao222_x1_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_14_ins : a2_x2 + port map ( + i0 => s(2), + i1 => not_aux100, + q => a2_x2_14_sig, + vdd => vdd, + vss => vss + ); + +o2_x2_14_ins : o2_x2 + port map ( + i0 => s(1), + i1 => not_aux61, + q => o2_x2_14_sig, + vdd => vdd, + vss => vss + ); + +oa22_x2_8_ins : oa22_x2 + port map ( + i0 => o2_x2_14_sig, + i1 => a2_x2_14_sig, + i2 => i(2), + q => oa22_x2_8_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_9_ins : inv_x2 + port map ( + i => aux106, + nq => inv_x2_9_sig, + vdd => vdd, + vss => vss + ); + +mx2_x2_ins : mx2_x2 + port map ( + cmd => r(2), + i0 => inv_x2_9_sig, + i1 => not_aux107, + q => mx2_x2_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_18_ins : na2_x1 + port map ( + i0 => s(3), + i1 => not_aux16, + nq => na2_x1_18_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_19_ins : na2_x1 + port map ( + i0 => s(3), + i1 => not_aux21, + nq => na2_x1_19_sig, + vdd => vdd, + vss => vss + ); + +oa2a22_x2_ins : oa2a22_x2 + port map ( + i0 => aux135, + i1 => na2_x1_19_sig, + i2 => na2_x1_18_sig, + i3 => aux136, + q => oa2a22_x2_sig, + vdd => vdd, + vss => vss + ); + +noa22_x1_5_ins : noa22_x1 + port map ( + i0 => oa2a22_x2_sig, + i1 => not_s(1), + i2 => mx2_x2_sig, + nq => noa22_x1_5_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_14_ins : nao22_x1 + port map ( + i0 => noa22_x1_5_sig, + i1 => oa22_x2_8_sig, + i2 => noa2ao222_x1_sig, + nq => nao22_x1_14_sig, + vdd => vdd, + vss => vss + ); + +ng_ins : oa2ao222_x2 + port map ( + i0 => nao22_x1_14_sig, + i1 => not_i(1), + i2 => a3_x2_3_sig, + i3 => noa22_x1_2_sig, + i4 => i(1), + q => ng, + vdd => vdd, + vss => vss + ); + +no2_x1_12_ins : no2_x1 + port map ( + i0 => not_aux99, + i1 => not_i(2), + nq => no2_x1_12_sig, + vdd => vdd, + vss => vss + ); + +noa22_x1_7_ins : noa22_x1 + port map ( + i0 => not_aux120, + i1 => not_r(1), + i2 => not_r(2), + nq => noa22_x1_7_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_13_ins : no2_x1 + port map ( + i0 => r(2), + i1 => not_aux66, + nq => no2_x1_13_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_15_ins : nao22_x1 + port map ( + i0 => no2_x1_13_sig, + i1 => noa22_x1_7_sig, + i2 => not_s(1), + nq => nao22_x1_15_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_14_ins : no2_x1 + port map ( + i0 => not_aux120, + i1 => not_r(1), + nq => no2_x1_14_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_16_ins : nao22_x1 + port map ( + i0 => i(0), + i1 => no2_x1_14_sig, + i2 => r(2), + nq => nao22_x1_16_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_6_ins : a3_x2 + port map ( + i0 => not_aux97, + i1 => s(2), + i2 => not_aux78, + q => a3_x2_6_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_14_ins : na3_x1 + port map ( + i0 => a3_x2_6_sig, + i1 => nao22_x1_16_sig, + i2 => nao22_x1_15_sig, + nq => na3_x1_14_sig, + vdd => vdd, + vss => vss + ); + +on12_x1_4_ins : on12_x1 + port map ( + i0 => na3_x1_14_sig, + i1 => i(2), + q => on12_x1_4_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_10_ins : no3_x1 + port map ( + i0 => aux57, + i1 => not_aux64, + i2 => not_r(1), + nq => no3_x1_10_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_20_ins : na2_x1 + port map ( + i0 => not_aux68, + i1 => not_i(0), + nq => na2_x1_20_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_17_ins : nao22_x1 + port map ( + i0 => na2_x1_20_sig, + i1 => no3_x1_10_sig, + i2 => not_r(2), + nq => nao22_x1_17_sig, + vdd => vdd, + vss => vss + ); + +o3_x2_7_ins : o3_x2 + port map ( + i0 => cin, + i1 => not_aux10, + i2 => not_i(0), + q => o3_x2_7_sig, + vdd => vdd, + vss => vss + ); + +noa22_x1_8_ins : noa22_x1 + port map ( + i0 => o3_x2_7_sig, + i1 => not_aux21, + i2 => not_aux80, + nq => noa22_x1_8_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_15_ins : na3_x1 + port map ( + i0 => not_r(2), + i1 => not_aux57, + i2 => aux65, + nq => na3_x1_15_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_15_ins : a2_x2 + port map ( + i0 => na3_x1_15_sig, + i1 => not_aux67, + q => a2_x2_15_sig, + vdd => vdd, + vss => vss + ); + +ao2o22_x2_3_ins : ao2o22_x2 + port map ( + i0 => s(1), + i1 => a2_x2_15_sig, + i2 => noa22_x1_8_sig, + i3 => not_r(2), + q => ao2o22_x2_3_sig, + vdd => vdd, + vss => vss + ); + +noa22_x1_6_ins : noa22_x1 + port map ( + i0 => ao2o22_x2_3_sig, + i1 => nao22_x1_17_sig, + i2 => on12_x1_4_sig, + nq => noa22_x1_6_sig, + vdd => vdd, + vss => vss + ); + +na4_x1_5_ins : na4_x1 + port map ( + i0 => not_aux116, + i1 => not_aux104, + i2 => not_aux115, + i3 => not_cin, + nq => na4_x1_5_sig, + vdd => vdd, + vss => vss + ); + +ao22_x2_3_ins : ao22_x2 + port map ( + i0 => aux105, + i1 => na4_x1_5_sig, + i2 => not_i(1), + q => ao22_x2_3_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_16_ins : a2_x2 + port map ( + i0 => s(3), + i1 => not_i(0), + q => a2_x2_16_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_19_ins : nao22_x1 + port map ( + i0 => a2_x2_16_sig, + i1 => aux2, + i2 => aux137, + nq => nao22_x1_19_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_22_ins : na2_x1 + port map ( + i0 => not_aux85, + i1 => not_aux10, + nq => na2_x1_22_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_17_ins : na3_x1 + port map ( + i0 => r(1), + i1 => r(2), + i2 => na2_x1_22_sig, + nq => na3_x1_17_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_16_ins : na3_x1 + port map ( + i0 => not_aux105, + i1 => na3_x1_17_sig, + i2 => nao22_x1_19_sig, + nq => na3_x1_16_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_21_ins : na2_x1 + port map ( + i0 => not_s(1), + i1 => na3_x1_16_sig, + nq => na2_x1_21_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_23_ins : na2_x1 + port map ( + i0 => not_aux105, + i1 => not_aux66, + nq => na2_x1_23_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_15_ins : no2_x1 + port map ( + i0 => not_aux2, + i1 => not_i(0), + nq => no2_x1_15_sig, + vdd => vdd, + vss => vss + ); + +ao22_x2_4_ins : ao22_x2 + port map ( + i0 => no2_x1_15_sig, + i1 => na2_x1_23_sig, + i2 => not_r(2), + q => ao22_x2_4_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_24_ins : na2_x1 + port map ( + i0 => not_aux98, + i1 => not_aux105, + nq => na2_x1_24_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_16_ins : no2_x1 + port map ( + i0 => i(0), + i1 => not_aux10, + nq => no2_x1_16_sig, + vdd => vdd, + vss => vss + ); + +ao22_x2_5_ins : ao22_x2 + port map ( + i0 => no2_x1_16_sig, + i1 => na2_x1_24_sig, + i2 => r(2), + q => ao22_x2_5_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_20_ins : nao22_x1 + port map ( + i0 => ao22_x2_5_sig, + i1 => ao22_x2_4_sig, + i2 => s(1), + nq => nao22_x1_20_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_7_ins : a3_x2 + port map ( + i0 => not_s(2), + i1 => nao22_x1_20_sig, + i2 => na2_x1_21_sig, + q => a3_x2_7_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_10_ins : inv_x2 + port map ( + i => aux118, + nq => inv_x2_10_sig, + vdd => vdd, + vss => vss + ); + +o3_x2_8_ins : o3_x2 + port map ( + i0 => r(1), + i1 => not_aux2, + i2 => inv_x2_10_sig, + q => o3_x2_8_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_25_ins : na2_x1 + port map ( + i0 => not_aux107, + i1 => o3_x2_8_sig, + nq => na2_x1_25_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_26_ins : na2_x1 + port map ( + i0 => r(1), + i1 => not_aux2, + nq => na2_x1_26_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_18_ins : na3_x1 + port map ( + i0 => r(2), + i1 => na2_x1_26_sig, + i2 => aux118, + nq => na3_x1_18_sig, + vdd => vdd, + vss => vss + ); + +o2_x2_15_ins : o2_x2 + port map ( + i0 => r(2), + i1 => not_aux117, + q => o2_x2_15_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_17_ins : a2_x2 + port map ( + i0 => not_aux10, + i1 => not_r(1), + q => a2_x2_17_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_21_ins : nao22_x1 + port map ( + i0 => a2_x2_17_sig, + i1 => o2_x2_15_sig, + i2 => na3_x1_18_sig, + nq => nao22_x1_21_sig, + vdd => vdd, + vss => vss + ); + +o3_x2_9_ins : o3_x2 + port map ( + i0 => not_aux117, + i1 => not_aux10, + i2 => not_r(1), + q => o3_x2_9_sig, + vdd => vdd, + vss => vss + ); + +on12_x1_5_ins : on12_x1 + port map ( + i0 => o3_x2_9_sig, + i1 => aux106, + q => on12_x1_5_sig, + vdd => vdd, + vss => vss + ); + +noa2a2a23_x1_ins : noa2a2a23_x1 + port map ( + i0 => on12_x1_5_sig, + i1 => not_r(2), + i2 => s(1), + i3 => nao22_x1_21_sig, + i4 => na2_x1_25_sig, + i5 => r(2), + nq => noa2a2a23_x1_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_18_ins : nao22_x1 + port map ( + i0 => noa2a2a23_x1_sig, + i1 => a3_x2_7_sig, + i2 => not_i(2), + nq => nao22_x1_18_sig, + vdd => vdd, + vss => vss + ); + +cout_ins : oa2ao222_x2 + port map ( + i0 => nao22_x1_18_sig, + i1 => ao22_x2_3_sig, + i2 => noa22_x1_6_sig, + i3 => no2_x1_12_sig, + i4 => i(1), + q => cout, + vdd => vdd, + vss => vss + ); + +inv_x2_11_ins : inv_x2 + port map ( + i => not_aux104, + nq => inv_x2_11_sig, + vdd => vdd, + vss => vss + ); + +xr2_x1_2_ins : xr2_x1 + port map ( + i0 => aux122, + i1 => cin, + q => xr2_x1_2_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_12_ins : inv_x2 + port map ( + i => not_aux124, + nq => inv_x2_12_sig, + vdd => vdd, + vss => vss + ); + +oa22_x2_9_ins : oa22_x2 + port map ( + i0 => i(0), + i1 => s(0), + i2 => not_aux124, + q => oa22_x2_9_sig, + vdd => vdd, + vss => vss + ); + +mx3_x2_2_ins : mx3_x2 + port map ( + cmd0 => not_i(2), + cmd1 => not_r(0), + i0 => aux122, + i1 => oa22_x2_9_sig, + i2 => inv_x2_12_sig, + q => mx3_x2_2_sig, + vdd => vdd, + vss => vss + ); + +alu_out_0_ins : mx3_x2 + port map ( + cmd0 => not_i(1), + cmd1 => not_i(2), + i0 => mx3_x2_2_sig, + i1 => xr2_x1_2_sig, + i2 => inv_x2_11_sig, + q => alu_out(0), + vdd => vdd, + vss => vss + ); + +xr2_x1_3_ins : xr2_x1 + port map ( + i0 => aux125, + i1 => i(0), + q => xr2_x1_3_sig, + vdd => vdd, + vss => vss + ); + +o2_x2_16_ins : o2_x2 + port map ( + i0 => r(1), + i1 => not_aux64, + q => o2_x2_16_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_27_ins : na2_x1 + port map ( + i0 => r(1), + i1 => not_aux64, + nq => na2_x1_27_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_19_ins : na3_x1 + port map ( + i0 => not_i(0), + i1 => na2_x1_27_sig, + i2 => o2_x2_16_sig, + nq => na3_x1_19_sig, + vdd => vdd, + vss => vss + ); + +xr2_x1_4_ins : xr2_x1 + port map ( + i0 => aux90, + i1 => r(1), + q => xr2_x1_4_sig, + vdd => vdd, + vss => vss + ); + +oa2a22_x2_2_ins : oa2a22_x2 + port map ( + i0 => not_s(1), + i1 => xr2_x1_4_sig, + i2 => na3_x1_19_sig, + i3 => s(1), + q => oa2a22_x2_2_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_17_ins : no2_x1 + port map ( + i0 => not_aux26, + i1 => not_i(0), + nq => no2_x1_17_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_18_ins : a2_x2 + port map ( + i0 => not_aux28, + i1 => not_i(0), + q => a2_x2_18_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_11_ins : no3_x1 + port map ( + i0 => a2_x2_18_sig, + i1 => no2_x1_17_sig, + i2 => r(0), + nq => no3_x1_11_sig, + vdd => vdd, + vss => vss + ); + +noa22_x1_9_ins : noa22_x1 + port map ( + i0 => not_aux47, + i1 => not_aux34, + i2 => no3_x1_11_sig, + nq => noa22_x1_9_sig, + vdd => vdd, + vss => vss + ); + +nxr2_x1_2_ins : nxr2_x1 + port map ( + i0 => noa22_x1_9_sig, + i1 => aux125, + nq => nxr2_x1_2_sig, + vdd => vdd, + vss => vss + ); + +nao2o22_x1_ins : nao2o22_x1 + port map ( + i0 => i(2), + i1 => nxr2_x1_2_sig, + i2 => not_aux115, + i3 => not_i(2), + nq => nao2o22_x1_sig, + vdd => vdd, + vss => vss + ); + +alu_out_1_ins : mx3_x2 + port map ( + cmd0 => i(1), + cmd1 => not_i(2), + i0 => nao2o22_x1_sig, + i1 => oa2a22_x2_2_sig, + i2 => xr2_x1_3_sig, + q => alu_out(1), + vdd => vdd, + vss => vss + ); + +inv_x2_13_ins : inv_x2 + port map ( + i => not_aux116, + nq => inv_x2_13_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_19_ins : no2_x1 + port map ( + i0 => not_aux34, + i1 => not_r(0), + nq => no2_x1_19_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_20_ins : no2_x1 + port map ( + i0 => r(0), + i1 => not_aux26, + nq => no2_x1_20_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_12_ins : no3_x1 + port map ( + i0 => no2_x1_20_sig, + i1 => no2_x1_19_sig, + i2 => r(1), + nq => no3_x1_12_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_18_ins : no2_x1 + port map ( + i0 => not_aux43, + i1 => no3_x1_12_sig, + nq => no2_x1_18_sig, + vdd => vdd, + vss => vss + ); + +xr2_x1_6_ins : xr2_x1 + port map ( + i0 => no2_x1_18_sig, + i1 => r(2), + q => xr2_x1_6_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_22_ins : no2_x1 + port map ( + i0 => not_aux47, + i1 => not_r(0), + nq => no2_x1_22_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_19_ins : a2_x2 + port map ( + i0 => not_aux28, + i1 => not_r(0), + q => a2_x2_19_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_13_ins : no3_x1 + port map ( + i0 => a2_x2_19_sig, + i1 => no2_x1_22_sig, + i2 => r(1), + nq => no3_x1_13_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_21_ins : no2_x1 + port map ( + i0 => not_aux30, + i1 => no3_x1_13_sig, + nq => no2_x1_21_sig, + vdd => vdd, + vss => vss + ); + +xr2_x1_7_ins : xr2_x1 + port map ( + i0 => no2_x1_21_sig, + i1 => r(2), + q => xr2_x1_7_sig, + vdd => vdd, + vss => vss + ); + +oa2a22_x2_3_ins : oa2a22_x2 + port map ( + i0 => s(1), + i1 => xr2_x1_7_sig, + i2 => xr2_x1_6_sig, + i3 => not_s(1), + q => oa2a22_x2_3_sig, + vdd => vdd, + vss => vss + ); + +xr2_x1_5_ins : xr2_x1 + port map ( + i0 => oa2a22_x2_3_sig, + i1 => s(2), + q => xr2_x1_5_sig, + vdd => vdd, + vss => vss + ); + +o3_x2_10_ins : o3_x2 + port map ( + i0 => not_s(1), + i1 => not_aux70, + i2 => not_r(2), + q => o3_x2_10_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_28_ins : na2_x1 + port map ( + i0 => not_aux70, + i1 => not_r(2), + nq => na2_x1_28_sig, + vdd => vdd, + vss => vss + ); + +o3_x2_11_ins : o3_x2 + port map ( + i0 => s(1), + i1 => r(2), + i2 => not_aux65, + q => o3_x2_11_sig, + vdd => vdd, + vss => vss + ); + +noa22_x1_10_ins : noa22_x1 + port map ( + i0 => not_aux65, + i1 => r(2), + i2 => i(0), + nq => noa22_x1_10_sig, + vdd => vdd, + vss => vss + ); + +na4_x1_6_ins : na4_x1 + port map ( + i0 => noa22_x1_10_sig, + i1 => o3_x2_11_sig, + i2 => na2_x1_28_sig, + i3 => o3_x2_10_sig, + nq => na4_x1_6_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_23_ins : no2_x1 + port map ( + i0 => i(0), + i1 => not_aux70, + nq => no2_x1_23_sig, + vdd => vdd, + vss => vss + ); + +xr2_x1_8_ins : xr2_x1 + port map ( + i0 => no2_x1_23_sig, + i1 => r(2), + q => xr2_x1_8_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_24_ins : no2_x1 + port map ( + i0 => r(1), + i1 => not_aux90, + nq => no2_x1_24_sig, + vdd => vdd, + vss => vss + ); + +xr2_x1_9_ins : xr2_x1 + port map ( + i0 => no2_x1_24_sig, + i1 => r(2), + q => xr2_x1_9_sig, + vdd => vdd, + vss => vss + ); + +oa2a22_x2_4_ins : oa2a22_x2 + port map ( + i0 => not_s(1), + i1 => xr2_x1_9_sig, + i2 => xr2_x1_8_sig, + i3 => s(1), + q => oa2a22_x2_4_sig, + vdd => vdd, + vss => vss + ); + +xr2_x1_11_ins : xr2_x1 + port map ( + i0 => i(0), + i1 => s(2), + q => xr2_x1_11_sig, + vdd => vdd, + vss => vss + ); + +xr2_x1_10_ins : xr2_x1 + port map ( + i0 => xr2_x1_11_sig, + i1 => r(2), + q => xr2_x1_10_sig, + vdd => vdd, + vss => vss + ); + +mx3_x2_3_ins : mx3_x2 + port map ( + cmd0 => not_i(2), + cmd1 => not_s(2), + i0 => xr2_x1_10_sig, + i1 => oa2a22_x2_4_sig, + i2 => na4_x1_6_sig, + q => mx3_x2_3_sig, + vdd => vdd, + vss => vss + ); + +alu_out_2_ins : mx3_x2 + port map ( + cmd0 => not_i(1), + cmd1 => not_i(2), + i0 => mx3_x2_3_sig, + i1 => xr2_x1_5_sig, + i2 => inv_x2_13_sig, + q => alu_out(2), + vdd => vdd, + vss => vss + ); + +inv_x2_14_ins : inv_x2 + port map ( + i => not_aux129, + nq => inv_x2_14_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_25_ins : no2_x1 + port map ( + i0 => not_aux131, + i1 => not_r(1), + nq => no2_x1_25_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_22_ins : nao22_x1 + port map ( + i0 => r(1), + i1 => not_aux132, + i2 => not_aux130, + nq => nao22_x1_22_sig, + vdd => vdd, + vss => vss + ); + +oa2ao222_x2_2_ins : oa2ao222_x2 + port map ( + i0 => nao22_x1_22_sig, + i1 => r(2), + i2 => no2_x1_25_sig, + i3 => inv_x2_14_sig, + i4 => not_r(2), + q => oa2ao222_x2_2_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_15_ins : inv_x2 + port map ( + i => not_aux132, + nq => inv_x2_15_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_16_ins : inv_x2 + port map ( + i => not_aux131, + nq => inv_x2_16_sig, + vdd => vdd, + vss => vss + ); + +mx2_x2_2_ins : mx2_x2 + port map ( + cmd => r(1), + i0 => inv_x2_16_sig, + i1 => not_aux127, + q => mx2_x2_2_sig, + vdd => vdd, + vss => vss + ); + +mx3_x2_5_ins : mx3_x2 + port map ( + cmd0 => r(2), + cmd1 => not_r(1), + i0 => mx2_x2_2_sig, + i1 => not_aux127, + i2 => inv_x2_15_sig, + q => mx3_x2_5_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_23_ins : nao22_x1 + port map ( + i0 => r(1), + i1 => not_aux128, + i2 => not_aux130, + nq => nao22_x1_23_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_24_ins : nao22_x1 + port map ( + i0 => not_aux126, + i1 => not_r(1), + i2 => not_aux129, + nq => nao22_x1_24_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_17_ins : inv_x2 + port map ( + i => not_aux128, + nq => inv_x2_17_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_18_ins : inv_x2 + port map ( + i => not_aux127, + nq => inv_x2_18_sig, + vdd => vdd, + vss => vss + ); + +nao2o22_x1_2_ins : nao2o22_x1 + port map ( + i0 => not_r(1), + i1 => not_aux127, + i2 => not_aux126, + i3 => r(1), + nq => nao2o22_x1_2_sig, + vdd => vdd, + vss => vss + ); + +mx3_x2_7_ins : mx3_x2 + port map ( + cmd0 => r(2), + cmd1 => not_r(1), + i0 => nao2o22_x1_2_sig, + i1 => inv_x2_18_sig, + i2 => inv_x2_17_sig, + q => mx3_x2_7_sig, + vdd => vdd, + vss => vss + ); + +mx3_x2_6_ins : mx3_x2 + port map ( + cmd0 => s(1), + cmd1 => not_r(2), + i0 => mx3_x2_7_sig, + i1 => nao22_x1_24_sig, + i2 => nao22_x1_23_sig, + q => mx3_x2_6_sig, + vdd => vdd, + vss => vss + ); + +mx3_x2_4_ins : mx3_x2 + port map ( + cmd0 => s(2), + cmd1 => s(1), + i0 => mx3_x2_6_sig, + i1 => mx3_x2_5_sig, + i2 => oa2ao222_x2_2_sig, + q => mx3_x2_4_sig, + vdd => vdd, + vss => vss + ); + +on12_x1_6_ins : on12_x1 + port map ( + i0 => aux65, + i1 => aux138, + q => on12_x1_6_sig, + vdd => vdd, + vss => vss + ); + +o2_x2_17_ins : o2_x2 + port map ( + i0 => not_aux64, + i1 => aux86, + q => o2_x2_17_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_26_ins : no2_x1 + port map ( + i0 => not_aux133, + i1 => not_s(2), + nq => no2_x1_26_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_20_ins : na3_x1 + port map ( + i0 => no2_x1_26_sig, + i1 => o2_x2_17_sig, + i2 => on12_x1_6_sig, + nq => na3_x1_20_sig, + vdd => vdd, + vss => vss + ); + +no4_x1_4_ins : no4_x1 + port map ( + i0 => not_aux108, + i1 => not_r(2), + i2 => not_aux64, + i3 => not_r(1), + nq => no4_x1_4_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_15_ins : no3_x1 + port map ( + i0 => aux138, + i1 => not_aux65, + i2 => not_aux108, + nq => no3_x1_15_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_16_ins : no3_x1 + port map ( + i0 => not_aux134, + i1 => not_aux133, + i2 => not_aux70, + nq => no3_x1_16_sig, + vdd => vdd, + vss => vss + ); + +on12_x1_7_ins : on12_x1 + port map ( + i0 => not_aux113, + i1 => no3_x1_16_sig, + q => on12_x1_7_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_14_ins : no3_x1 + port map ( + i0 => on12_x1_7_sig, + i1 => no3_x1_15_sig, + i2 => no4_x1_4_sig, + nq => no3_x1_14_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_27_ins : no2_x1 + port map ( + i0 => not_aux71, + i1 => not_s(3), + nq => no2_x1_27_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_17_ins : no3_x1 + port map ( + i0 => r(3), + i1 => not_aux90, + i2 => s(3), + nq => no3_x1_17_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_25_ins : nao22_x1 + port map ( + i0 => no3_x1_17_sig, + i1 => no2_x1_27_sig, + i2 => aux137, + nq => nao22_x1_25_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_29_ins : na2_x1 + port map ( + i0 => not_aux64, + i1 => aux137, + nq => na2_x1_29_sig, + vdd => vdd, + vss => vss + ); + +ao22_x2_6_ins : ao22_x2 + port map ( + i0 => not_aux70, + i1 => not_aux134, + i2 => not_s(2), + q => ao22_x2_6_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_21_ins : na3_x1 + port map ( + i0 => ao22_x2_6_sig, + i1 => na2_x1_29_sig, + i2 => aux108, + nq => na3_x1_21_sig, + vdd => vdd, + vss => vss + ); + +a4_x2_6_ins : a4_x2 + port map ( + i0 => na3_x1_21_sig, + i1 => nao22_x1_25_sig, + i2 => no3_x1_14_sig, + i3 => na3_x1_20_sig, + q => a4_x2_6_sig, + vdd => vdd, + vss => vss + ); + +nao2o22_x1_3_ins : nao2o22_x1 + port map ( + i0 => i(2), + i1 => a4_x2_6_sig, + i2 => not_aux127, + i3 => not_i(2), + nq => nao2o22_x1_3_sig, + vdd => vdd, + vss => vss + ); + +alu_out_3_ins : mx3_x2 + port map ( + cmd0 => not_i(1), + cmd1 => not_i(2), + i0 => nao2o22_x1_3_sig, + i1 => mx3_x2_4_sig, + i2 => aux105, + q => alu_out(3), + vdd => vdd, + vss => vss + ); + + +end structural; diff --git a/documentation/examples/AM2901/amd2901.vst b/documentation/examples/AM2901/amd2901.vst new file mode 100644 index 00000000..31eac8ee --- /dev/null +++ b/documentation/examples/AM2901/amd2901.vst @@ -0,0 +1,675 @@ +-- +-- Generated by VASY +-- +ENTITY amd2901 IS +PORT( + a : IN BIT_VECTOR(3 DOWNTO 0); + b : IN BIT_VECTOR(3 DOWNTO 0); + cin : IN BIT; + ck : IN BIT; + cout : OUT BIT; + d : IN BIT_VECTOR(3 DOWNTO 0); + i : IN BIT_VECTOR(8 DOWNTO 0); + ng : OUT BIT; + noe : IN BIT; + np : OUT BIT; + ovr : OUT BIT; + q0 : INOUT BIT; + q3 : INOUT BIT; + r0 : INOUT BIT; + r3 : INOUT BIT; + f3 : OUT BIT; + vdde : IN BIT; + vddi : IN BIT; + vsse : IN BIT; + vssi : IN BIT; + y : OUT BIT_VECTOR(3 DOWNTO 0); + zero : OUT BIT +); +END amd2901; + +ARCHITECTURE VST OF amd2901 IS + + SIGNAL a_from_pads : BIT_VECTOR(3 DOWNTO 0); + SIGNAL b_from_pads : BIT_VECTOR(3 DOWNTO 0); + SIGNAL cin_from_pads : BIT; + SIGNAL cki : BIT; + SIGNAL ckc : BIT; + SIGNAL cout_to_pads : BIT; + SIGNAL d_from_pads : BIT_VECTOR(3 DOWNTO 0); + SIGNAL i_from_pads : BIT_VECTOR(8 DOWNTO 0); + SIGNAL ng_to_pads : BIT; + SIGNAL noe_from_pads : BIT; + SIGNAL np_to_pads : BIT; + SIGNAL ovr_to_pads : BIT; + SIGNAL q0_from_pads : BIT; + SIGNAL q0_to_pads : BIT; + SIGNAL q3_from_pads : BIT; + SIGNAL q3_to_pads : BIT; + SIGNAL r0_from_pads : BIT; + SIGNAL r0_to_pads : BIT; + SIGNAL r3_from_pads : BIT; + SIGNAL r3_to_pads : BIT; + SIGNAL shift_l : BIT; + SIGNAL shift_r : BIT; + SIGNAL f3_to_pads : BIT; + SIGNAL y_oe : BIT; + SIGNAL y_to_pads : BIT_VECTOR(3 DOWNTO 0); + SIGNAL zero_to_pads : BIT; + + COMPONENT pck_px + PORT( + ck : OUT BIT; + pad : IN BIT; + vdde : IN BIT; + vddi : IN BIT; + vsse : IN BIT; + vssi : IN BIT + ); + END COMPONENT; + + COMPONENT pi_px + PORT( + ck : IN BIT; + pad : IN BIT; + t : OUT BIT; + vdde : IN BIT; + vddi : IN BIT; + vsse : IN BIT; + vssi : IN BIT + ); + END COMPONENT; + + COMPONENT coeur + PORT( + a_from_pads : IN BIT_VECTOR(3 DOWNTO 0); + b_from_pads : IN BIT_VECTOR(3 DOWNTO 0); + cin_from_pads : IN BIT; + ck : IN BIT; + cout_to_pads : OUT BIT; + d_from_pads : IN BIT_VECTOR(3 DOWNTO 0); + i_from_pads : IN BIT_VECTOR(8 DOWNTO 0); + ng_to_pads : OUT BIT; + noe_from_pads : IN BIT; + np_to_pads : OUT BIT; + ovr_to_pads : OUT BIT; + q0_from_pads : IN BIT; + q0_to_pads : OUT BIT; + q3_from_pads : IN BIT; + q3_to_pads : OUT BIT; + r0_from_pads : IN BIT; + r0_to_pads : OUT BIT; + r3_from_pads : IN BIT; + r3_to_pads : OUT BIT; + shift_l : OUT BIT; + shift_r : OUT BIT; + f3_to_pads : OUT BIT; + vdd : IN BIT; + vss : IN BIT; + y_oe : OUT BIT; + y_to_pads : OUT BIT_VECTOR(3 DOWNTO 0); + zero_to_pads : OUT BIT + ); + END COMPONENT; + + COMPONENT pvddick_px + PORT( + ck : IN BIT; + cko : OUT BIT; + vdde : IN BIT; + vddi : IN BIT; + vsse : IN BIT; + vssi : IN BIT + ); + END COMPONENT; + + COMPONENT po_px + PORT( + ck : IN BIT; + i : IN BIT; + pad : OUT BIT; + vdde : IN BIT; + vddi : IN BIT; + vsse : IN BIT; + vssi : IN BIT + ); + END COMPONENT; + + COMPONENT pot_px + PORT( + b : IN BIT; + ck : IN BIT; + i : IN BIT; + pad : OUT BIT; + vdde : IN BIT; + vddi : IN BIT; + vsse : IN BIT; + vssi : IN BIT + ); + END COMPONENT; + + COMPONENT piot_px + PORT( + b : IN BIT; + ck : IN BIT; + i : IN BIT; + pad : INOUT BIT; + t : OUT BIT; + vdde : IN BIT; + vddi : IN BIT; + vsse : IN BIT; + vssi : IN BIT + ); + END COMPONENT; + + COMPONENT pvssick_px + PORT( + ck : IN BIT; + cko : OUT BIT; + vdde : IN BIT; + vddi : IN BIT; + vsse : IN BIT; + vssi : IN BIT + ); + END COMPONENT; + + COMPONENT pvddeck_px + PORT( + ck : IN BIT; + cko : OUT BIT; + vdde : IN BIT; + vddi : IN BIT; + vsse : IN BIT; + vssi : IN BIT + ); + END COMPONENT; + + COMPONENT pvsseck_px + PORT( + ck : IN BIT; + cko : OUT BIT; + vdde : IN BIT; + vddi : IN BIT; + vsse : IN BIT; + vssi : IN BIT + ); + END COMPONENT; + +BEGIN + + p_i8 : pi_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + t => i_from_pads(8), + pad => i(8), + ck => cki + ); + p_y1 : pot_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + pad => y(1), + i => y_to_pads(1), + ck => cki, + b => y_oe + ); + p_vddeck0 : pvddeck_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + cko => ckc, + ck => cki + ); + p_i4 : pi_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + t => i_from_pads(4), + pad => i(4), + ck => cki + ); + p_b2 : pi_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + t => b_from_pads(2), + pad => b(2), + ck => cki + ); + p_noe : pi_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + t => noe_from_pads, + pad => noe, + ck => cki + ); + p_ng : po_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + pad => ng, + i => ng_to_pads, + ck => cki + ); + p_q0 : piot_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + t => q0_from_pads, + pad => q0, + i => q0_to_pads, + ck => cki, + b => shift_r + ); + p_r0 : piot_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + t => r0_from_pads, + pad => r0, + i => r0_to_pads, + ck => cki, + b => shift_r + ); + p_vddeck1 : pvddeck_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + cko => ckc, + ck => cki + ); + p_i3 : pi_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + t => i_from_pads(3), + pad => i(3), + ck => cki + ); + core : coeur + PORT MAP ( + a_from_pads => a_from_pads, + b_from_pads => b_from_pads, + d_from_pads => d_from_pads, + i_from_pads => i_from_pads, + y_to_pads => y_to_pads, + zero_to_pads => zero_to_pads, + y_oe => y_oe, + vss => vssi, + vdd => vddi, + f3_to_pads => f3_to_pads, + shift_r => shift_r, + shift_l => shift_l, + r3_to_pads => r3_to_pads, + r3_from_pads => r3_from_pads, + r0_to_pads => r0_to_pads, + r0_from_pads => r0_from_pads, + q3_to_pads => q3_to_pads, + q3_from_pads => q3_from_pads, + q0_to_pads => q0_to_pads, + q0_from_pads => q0_from_pads, + ovr_to_pads => ovr_to_pads, + np_to_pads => np_to_pads, + noe_from_pads => noe_from_pads, + ng_to_pads => ng_to_pads, + cout_to_pads => cout_to_pads, + ck => ckc, + cin_from_pads => cin_from_pads + ); + p_i5 : pi_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + t => i_from_pads(5), + pad => i(5), + ck => cki + ); + p_y2 : pot_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + pad => y(2), + i => y_to_pads(2), + ck => cki, + b => y_oe + ); + p_vssick0 : pvssick_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + cko => ckc, + ck => cki + ); + p_b3 : pi_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + t => b_from_pads(3), + pad => b(3), + ck => cki + ); + p_a3 : pi_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + t => a_from_pads(3), + pad => a(3), + ck => cki + ); + p_d2 : pi_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + t => d_from_pads(2), + pad => d(2), + ck => cki + ); + p_cin : pi_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + t => cin_from_pads, + pad => cin, + ck => cki + ); + p_i6 : pi_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + t => i_from_pads(6), + pad => i(6), + ck => cki + ); + p_cout : po_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + pad => cout, + i => cout_to_pads, + ck => cki + ); + p_zero : po_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + pad => zero, + i => zero_to_pads, + ck => cki + ); + p_f3 : po_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + pad => f3, + i => f3_to_pads, + ck => cki + ); + p_i2 : pi_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + t => i_from_pads(2), + pad => i(2), + ck => cki + ); + p_ck : pck_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + pad => ck, + ck => cki + ); + p_np : po_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + pad => np, + i => np_to_pads, + ck => cki + ); + p_y3 : pot_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + pad => y(3), + i => y_to_pads(3), + ck => cki, + b => y_oe + ); + p_q3 : piot_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + t => q3_from_pads, + pad => q3, + i => q3_to_pads, + ck => cki, + b => shift_l + ); + p_r3 : piot_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + t => r3_from_pads, + pad => r3, + i => r3_to_pads, + ck => cki, + b => shift_l + ); + p_vsseck1 : pvsseck_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + cko => ckc, + ck => cki + ); + p_a0 : pi_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + t => a_from_pads(0), + pad => a(0), + ck => cki + ); + p_b0 : pi_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + t => b_from_pads(0), + pad => b(0), + ck => cki + ); + p_d0 : pi_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + t => d_from_pads(0), + pad => d(0), + ck => cki + ); + p_d1 : pi_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + t => d_from_pads(1), + pad => d(1), + ck => cki + ); + p_i7 : pi_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + t => i_from_pads(7), + pad => i(7), + ck => cki + ); + p_ovr : po_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + pad => ovr, + i => ovr_to_pads, + ck => cki + ); + p_y0 : pot_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + pad => y(0), + i => y_to_pads(0), + ck => cki, + b => y_oe + ); + p_i0 : pi_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + t => i_from_pads(0), + pad => i(0), + ck => cki + ); + p_a1 : pi_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + t => a_from_pads(1), + pad => a(1), + ck => cki + ); + p_b1 : pi_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + t => b_from_pads(1), + pad => b(1), + ck => cki + ); + p_vddick0 : pvddick_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + cko => ckc, + ck => cki + ); + p_vsseck0 : pvsseck_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + cko => ckc, + ck => cki + ); + p_i1 : pi_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + t => i_from_pads(1), + pad => i(1), + ck => cki + ); + p_d3 : pi_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + t => d_from_pads(3), + pad => d(3), + ck => cki + ); + p_a2 : pi_px + PORT MAP ( + vssi => vssi, + vsse => vsse, + vddi => vddi, + vdde => vdde, + t => a_from_pads(2), + pad => a(2), + ck => cki + ); +END VST; diff --git a/documentation/examples/AM2901/coeur.vst b/documentation/examples/AM2901/coeur.vst new file mode 100644 index 00000000..3f003427 --- /dev/null +++ b/documentation/examples/AM2901/coeur.vst @@ -0,0 +1,197 @@ +-- +-- Generated by VASY +-- +ENTITY coeur IS +PORT( + a_from_pads : IN BIT_VECTOR(3 DOWNTO 0); + b_from_pads : IN BIT_VECTOR(3 DOWNTO 0); + cin_from_pads : IN BIT; + ck : IN BIT; + cout_to_pads : OUT BIT; + d_from_pads : IN BIT_VECTOR(3 DOWNTO 0); + i_from_pads : IN BIT_VECTOR(8 DOWNTO 0); + ng_to_pads : OUT BIT; + noe_from_pads : IN BIT; + np_to_pads : OUT BIT; + ovr_to_pads : OUT BIT; + q0_from_pads : IN BIT; + q0_to_pads : OUT BIT; + q3_from_pads : IN BIT; + q3_to_pads : OUT BIT; + r0_from_pads : IN BIT; + r0_to_pads : OUT BIT; + r3_from_pads : IN BIT; + r3_to_pads : OUT BIT; + shift_l : OUT BIT; + shift_r : OUT BIT; + f3_to_pads : OUT BIT; + vdd : IN BIT; + vss : IN BIT; + y_oe : OUT BIT; + y_to_pads : OUT BIT_VECTOR(3 DOWNTO 0); + zero_to_pads : OUT BIT +); +END coeur; + +ARCHITECTURE VST OF coeur IS + + SIGNAL alu_out : BIT_VECTOR(3 DOWNTO 0); + SIGNAL r : BIT_VECTOR(3 DOWNTO 0); + SIGNAL ra : BIT_VECTOR(3 DOWNTO 0); + SIGNAL rb : BIT_VECTOR(3 DOWNTO 0); + SIGNAL s : BIT_VECTOR(3 DOWNTO 0); + SIGNAL saccu : BIT_VECTOR(3 DOWNTO 0); + + COMPONENT muxs + PORT( + alu_out : IN BIT_VECTOR(3 DOWNTO 0); + i : IN BIT_VECTOR(2 DOWNTO 0); + noe : IN BIT; + oe : OUT BIT; + ra : IN BIT_VECTOR(3 DOWNTO 0); + shift_l : OUT BIT; + shift_r : OUT BIT; + vdd : IN BIT; + vss : IN BIT; + y : OUT BIT_VECTOR(3 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT alu + PORT( + alu_out : INOUT BIT_VECTOR(3 DOWNTO 0); + cin : IN BIT; + cout : OUT BIT; + i : IN BIT_VECTOR(2 DOWNTO 0); + ng : OUT BIT; + np : OUT BIT; + ovr : OUT BIT; + r : IN BIT_VECTOR(3 DOWNTO 0); + s : IN BIT_VECTOR(3 DOWNTO 0); + f3 : OUT BIT; + vdd : IN BIT; + vss : IN BIT; + zero : OUT BIT + ); + END COMPONENT; + + COMPONENT accu + PORT( + accu : INOUT BIT_VECTOR(3 DOWNTO 0); + alu_out : IN BIT_VECTOR(3 DOWNTO 0); + cke : IN BIT; + i : IN BIT_VECTOR(2 DOWNTO 0); + q0_from : IN BIT; + q0_to : OUT BIT; + q3_from : IN BIT; + q3_to : OUT BIT; + vdd : IN BIT; + vss : IN BIT + ); + END COMPONENT; + + COMPONENT ram + PORT( + a : IN BIT_VECTOR(3 DOWNTO 0); + alu_out : IN BIT_VECTOR(3 DOWNTO 0); + b : IN BIT_VECTOR(3 DOWNTO 0); + clk : IN BIT; + i : IN BIT_VECTOR(2 DOWNTO 0); + r0_from_pads : IN BIT; + r0_to_pads : OUT BIT; + r3_from_pads : IN BIT; + r3_to_pads : OUT BIT; + ra : OUT BIT_VECTOR(3 DOWNTO 0); + rb : OUT BIT_VECTOR(3 DOWNTO 0); + vdd : IN BIT; + vss : IN BIT + ); + END COMPONENT; + + COMPONENT muxe + PORT( + accu : IN BIT_VECTOR(3 DOWNTO 0); + d : IN BIT_VECTOR(3 DOWNTO 0); + i : IN BIT_VECTOR(2 DOWNTO 0); + r : OUT BIT_VECTOR(3 DOWNTO 0); + ra : IN BIT_VECTOR(3 DOWNTO 0); + rb : IN BIT_VECTOR(3 DOWNTO 0); + s : OUT BIT_VECTOR(3 DOWNTO 0); + vdd : IN BIT; + vss : IN BIT + ); + END COMPONENT; + +BEGIN + + iram : ram + PORT MAP ( + a(3 downto 0) => a_from_pads, + alu_out => alu_out, + b(3 downto 0) => b_from_pads, + i(2 downto 0) => i_from_pads(8 downto 6), + ra => ra, + rb => rb, + vss => vss, + vdd => vdd, + r3_to_pads => r3_to_pads, + r3_from_pads => r3_from_pads, + r0_to_pads => r0_to_pads, + r0_from_pads => r0_from_pads, + clk => ck + ); + iaccu : accu + PORT MAP ( + accu(3 downto 0) => saccu, + alu_out => alu_out, + i(2 downto 0) => i_from_pads(8 downto 6), + vss => vss, + vdd => vdd, + q3_to => q3_to_pads, + q3_from => q3_from_pads, + q0_to => q0_to_pads, + q0_from => q0_from_pads, + cke => ck + ); + ialu : alu + PORT MAP ( + alu_out => alu_out, + i(2 downto 0) => i_from_pads(5 downto 3), + r => r, + s => s, + zero => zero_to_pads, + vss => vss, + vdd => vdd, + f3 => f3_to_pads, + ovr => ovr_to_pads, + np => np_to_pads, + ng => ng_to_pads, + cout => cout_to_pads, + cin => cin_from_pads + ); + imuxs : muxs + PORT MAP ( + alu_out => alu_out, + i(2 downto 0) => i_from_pads(8 downto 6), + ra => ra, + y(3 downto 0) => y_to_pads, + vss => vss, + vdd => vdd, + shift_r => shift_r, + shift_l => shift_l, + oe => y_oe, + noe => noe_from_pads + ); + imuxe : muxe + PORT MAP ( + accu(3 downto 0) => saccu, + d(3 downto 0) => d_from_pads, + i(2 downto 0) => i_from_pads(2 downto 0), + r => r, + ra => ra, + rb => rb, + s => s, + vss => vss, + vdd => vdd + ); +END VST; diff --git a/documentation/examples/AM2901/design.py b/documentation/examples/AM2901/design.py new file mode 100755 index 00000000..7ee53f77 --- /dev/null +++ b/documentation/examples/AM2901/design.py @@ -0,0 +1,238 @@ +#!/usr/bin/env python + +try: + import sys + import traceback + import os.path + import optparse + import Cfg + import Hurricane + from Hurricane import DbU + from Hurricane import UpdateSession + from Hurricane import Breakpoint + import Viewer + import CRL + from helpers import ErrorMessage + import Nimbus + import Metis + import Mauka + import Katabatic + import Kite + import Unicorn + import placeandroute +except ImportError, e: + module = str(e).split()[-1] + + print '[ERROR] The <%s> python module or symbol cannot be loaded.' % module + print ' Please check the integrity of the package.' + sys.exit(1) +except Exception, e: + print '[ERROR] A strange exception occurred while loading the basic Coriolis/Python' + print ' modules. Something may be wrong at Python/C API level.\n' + print ' %s' % e + sys.exit(2) + + +# Check that all the instances have been placed by Mauka. +def checkForUnplaceds ( cell ): + unplaceds = [] + for instance in cell.getInstances(): + if instance.getPlacementStatus() == Hurricane.PlacementStatusUNPLACED: + unplaceds += [ instance ] + if unplaceds: + message = [ 'Some instances are still unplaceds:' ] + for instance in unplaceds: + message += [ '<%s> of model <%s>'%(str(instance.getName()) + ,str(instance.getMasterCell().getName())) ] + raise ErrorMessage( 3, message ) + return + + +# Small wrapper to display breakpoints, when in graphic mode only. +def breakpoint ( editor, level, message ): + if editor: + editor.fit() + editor.refresh() + Breakpoint.stop( level, message ) + return + + +def ScriptMain ( cell=None ): + # Force removal of any previouly generated placement (.ap files) + # as they would prevent the the placer to run again. + # This is a little bit inconvenient, but will change in the future. + print ' o Cleaning up any previous run.' + for fileName in os.listdir('.'): + if fileName.endswith('.ap'): + print ' - <%s>' % fileName + os.unlink(fileName) + + editor = None + if globals().has_key('__editor'): + print ' o Editor detected, running in graphic mode.' + editor = __editor + + Cfg.Configuration.pushDefaultPriority(Cfg.Parameter.Priority.CommandLine) + Cfg.getParamBool('misc.verboseLevel1').setBool(True) + Cfg.getParamBool('misc.verboseLevel2').setBool(True) + Cfg.Configuration.popDefaultPriority() + + errorCode = 0 + framework = CRL.AllianceFramework.get() + + padHeight = DbU.fromLambda( 400.0) + padWidth = DbU.fromLambda( 200.0) + coreSide = DbU.fromLambda(1400.0) + + # Cell must be loaded *before* opening the UpdateSession. + print ' o Placing .' + modelCoeur = framework.getCell('coeur',CRL.Catalog.State.Logical) + + UpdateSession.open() + try: + modelCoeur.setAbutmentBox( Hurricane.Box( DbU.fromLambda(0) + , DbU.fromLambda(0) + , coreSide + , coreSide + ) ) + # Cannot place a rail if at least one instance is placed. + # (to compute the orientation of the cells rows) + #placeandroute.pyAlimVerticalRail( modelCoeur, coreSide/DbU.fromLambda(5.0*2) ) + + except Exception, e: + print e; errorCode = 1 + + # For the geometrical modifications to be taken into account, we must + # close this UpdateSession now. So the chip will see the core correctly. + UpdateSession.close() + if errorCode: sys.exit(errorCode) + + print ' o Placing .' + amd2901 = framework.getCell('amd2901',CRL.Catalog.State.Logical) + if editor: editor.setCell(amd2901) + + UpdateSession.open() + try: + + chipSide = 11*padWidth + 2*padHeight # Le chip est carre, avec 11 plots par face. + abutmentBoxChip = Hurricane.Box( DbU.fromLambda(0.0) + , DbU.fromLambda(0.0) + , chipSide + , chipSide + ) + amd2901.setAbutmentBox( abutmentBoxChip ) + + instanceCoeur = amd2901.getInstance( 'core' ) + instanceCoeur.setTransformation(Hurricane.Transformation( (chipSide-coreSide)/2 + , (chipSide-coreSide)/2 + , Hurricane.OrientationID ) ) + instanceCoeur.setPlacementStatus( Hurricane.PlacementStatusPLACED ) + + # Placing Pads + southPads = [ 'p_a3' , 'p_a2', 'p_a1', 'p_r0', 'p_vddick0', 'p_vssick0', 'p_a0' , 'p_i6', 'p_i8' , 'p_i7' , 'p_r3' ] + eastPads = [ 'p_zero', 'p_i0', 'p_i1', 'p_i2', 'p_vddeck0', 'p_vsseck0', 'p_q3' , 'p_b0', 'p_b1' , 'p_b2' , 'p_b3' ] + northPads = [ 'p_noe' , 'p_y3', 'p_y2', 'p_y1', 'p_y0' , 'p_vddeck1', 'p_vsseck1', 'p_np', 'p_ovr', 'p_cout', 'p_ng' ] + westPads = [ 'p_cin' , 'p_i4', 'p_i5', 'p_i3', 'p_ck' , 'p_d0' , 'p_d1' , 'p_d2', 'p_d3' , 'p_q0' , 'p_f3' ] + + for (key,listPads) in {'south':southPads, 'east':eastPads, 'north':northPads, 'west':westPads}.iteritems(): + print ' o Pads on %s side:' %key + for ipad in range(len(listPads)): + pad = amd2901.getInstance( listPads[ipad] ) + print ' - Placing pad: <%s> (model:<%s>).' % (listPads[ipad],str(pad.getMasterCell().getName())) + + # south + if key == 'south' : + xpad = abutmentBoxChip.getXMin() + padHeight + ipad*(padWidth) + ypad = abutmentBoxChip.getYMin() + padHeight + pad.setTransformation( Hurricane.Transformation( xpad, ypad, Hurricane.OrientationMY) ) + + # east + if key == 'east' : + xpad = abutmentBoxChip.getXMax() - padHeight + ypad = padHeight + padWidth + ipad*(padWidth) + pad.setTransformation( Hurricane.Transformation( xpad, ypad, Hurricane.OrientationR3) ) + + # north + if key == 'north' : + xpad = padHeight + ipad*(padWidth) + ypad = abutmentBoxChip.getYMax() - padHeight + pad.setTransformation( Hurricane.Transformation( xpad, ypad, Hurricane.OrientationID) ) + + # west + if key == 'west' : + xpad = padHeight + ypad = padHeight + ipad*(padWidth) + pad.setTransformation( Hurricane.Transformation( xpad, ypad, Hurricane.OrientationR1) ) + + pad.setPlacementStatus( Hurricane.PlacementStatusPLACED ) + + except ErrorMessage, e: + print e; errorCode = e.code + except Exception, e: + print '\n\n', e; errorCode = 1 + traceback.print_tb(sys.exc_info()[2]) + + UpdateSession.close() + if errorCode: sys.exit(errorCode) + + breakpoint( editor, 1, 'Chip After Pad Placement' ) + + try: + # Now run the tools. + coeur = framework.getCell('coeur',CRL.Catalog.State.Logical) + + mauka = Mauka.MaukaEngine.create(coeur) + mauka.run() + mauka.destroy() + + breakpoint( editor, 1, 'Core After Standard Cell Placement' ) + + placeandroute.pyAlimConnectors(coeur) + + # This is gross. It's the ghost of Wu Yifei and his demonic code... + # Will not be needed in the future (dynamic detection based on the + # transformations). + for pad in southPads: placeandroute.pad_south += [ amd2901.getInstance(pad) ] + for pad in northPads: placeandroute.pad_north += [ amd2901.getInstance(pad) ] + for pad in eastPads: placeandroute.pad_east += [ amd2901.getInstance(pad) ] + for pad in westPads: placeandroute.pad_west += [ amd2901.getInstance(pad) ] + + placeandroute.pyPowerRing( amd2901, amd2901.getInstance('core'), 3 ) + placeandroute.pyRouteCk ( amd2901, amd2901.getNet('ckc') ) + breakpoint( editor, 1, 'Core After Clock & Power Routing' ) + + kite = Kite.KiteEngine.create( amd2901 ) + kite.runGlobalRouter( Kite.KtBuildGlobalRouting ) + kite.loadGlobalRouting( Katabatic.EngineLoadGrByNet, [] ) + kite.layerAssign( Katabatic.EngineNoNetLayerAssign ) + kite.runNegociate() + breakpoint( editor, 1, 'Routing done, but router still active for inspection.' ) + kite.finalizeLayout() + kite.destroy() + + # Write back layout to disk if everything has gone fine. + # Must write all the sub-blocks of the core but *not* the + # standard cell (mainly the feed-through). + for instance in modelCoeur.getInstances(): + masterCell = instance.getMasterCell() + if not masterCell.isTerminal(): + framework.saveCell( masterCell, CRL.Catalog.State.Physical ) + + framework.saveCell( modelCoeur, CRL.Catalog.State.Physical ) + framework.saveCell( amd2901 , CRL.Catalog.State.Physical ) + + except ErrorMessage, e: + print e; errorCode = e.code + except Exception, e: + print '\n\n', e; errorCode = 1 + traceback.print_tb(sys.exc_info()[2]) + + if editor: editor.setCell(amd2901) + + return 0 + + +if __name__ == '__main__': + ScriptMain() + + sys.exit(0) diff --git a/documentation/examples/AM2901/muxe.vst b/documentation/examples/AM2901/muxe.vst new file mode 100644 index 00000000..b0059fc0 --- /dev/null +++ b/documentation/examples/AM2901/muxe.vst @@ -0,0 +1,558 @@ +entity muxe is + port ( + accu : in bit_vector(3 downto 0); + d : in bit_vector(3 downto 0); + i : in bit_vector(2 downto 0); + r : out bit_vector(3 downto 0); + ra : in bit_vector(3 downto 0); + rb : in bit_vector(3 downto 0); + s : out bit_vector(3 downto 0); + vdd : in bit; + vss : in bit + ); +end muxe; + +architecture structural of muxe is +Component o2_x2 + port ( + i0 : in bit; + i1 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component on12_x1 + port ( + i0 : in bit; + i1 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component inv_x2 + port ( + i : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component o3_x2 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component no4_x1 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + i3 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component na3_x1 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component na2_x1 + port ( + i0 : in bit; + i1 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component a2_x2 + port ( + i0 : in bit; + i1 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component nao22_x1 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component no2_x1 + port ( + i0 : in bit; + i1 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component an12_x1 + port ( + i0 : in bit; + i1 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component no3_x1 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +signal not_i : bit_vector( 2 downto 0); +signal on12_x1_sig : bit; +signal on12_x1_2_sig : bit; +signal o3_x2_sig : bit; +signal o3_x2_2_sig : bit; +signal not_aux2 : bit; +signal not_aux1 : bit; +signal not_aux0 : bit; +signal no2_x1_sig : bit; +signal no2_x1_5_sig : bit; +signal no2_x1_4_sig : bit; +signal no2_x1_3_sig : bit; +signal no2_x1_2_sig : bit; +signal nao22_x1_sig : bit; +signal na3_x1_sig : bit; +signal na3_x1_6_sig : bit; +signal na3_x1_5_sig : bit; +signal na3_x1_4_sig : bit; +signal na3_x1_3_sig : bit; +signal na3_x1_2_sig : bit; +signal na2_x1_sig : bit; +signal na2_x1_3_sig : bit; +signal na2_x1_2_sig : bit; +signal inv_x2_sig : bit; +signal inv_x2_2_sig : bit; +signal aux4 : bit; +signal aux3 : bit; +signal an12_x1_sig : bit; +signal an12_x1_2_sig : bit; +signal a2_x2_sig : bit; +signal a2_x2_2_sig : bit; + +begin + +not_aux2_ins : a2_x2 + port map ( + i0 => not_aux0, + i1 => not_i(0), + q => not_aux2, + vdd => vdd, + vss => vss + ); + +not_aux1_ins : o2_x2 + port map ( + i0 => i(0), + i1 => not_aux0, + q => not_aux1, + vdd => vdd, + vss => vss + ); + +not_aux0_ins : a2_x2 + port map ( + i0 => i(2), + i1 => not_i(1), + q => not_aux0, + vdd => vdd, + vss => vss + ); + +not_i_2_ins : inv_x2 + port map ( + i => i(2), + nq => not_i(2), + vdd => vdd, + vss => vss + ); + +not_i_1_ins : inv_x2 + port map ( + i => i(1), + nq => not_i(1), + vdd => vdd, + vss => vss + ); + +not_i_0_ins : inv_x2 + port map ( + i => i(0), + nq => not_i(0), + vdd => vdd, + vss => vss + ); + +aux4_ins : an12_x1 + port map ( + i0 => i(1), + i1 => ra(3), + q => aux4, + vdd => vdd, + vss => vss + ); + +aux3_ins : an12_x1 + port map ( + i0 => i(1), + i1 => ra(1), + q => aux3, + vdd => vdd, + vss => vss + ); + +na3_x1_ins : na3_x1 + port map ( + i0 => rb(0), + i1 => i(0), + i2 => not_i(2), + nq => na3_x1_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_2_ins : na3_x1 + port map ( + i0 => ra(0), + i1 => i(2), + i2 => not_i(1), + nq => na3_x1_2_sig, + vdd => vdd, + vss => vss + ); + +on12_x1_ins : on12_x1 + port map ( + i0 => accu(0), + i1 => not_aux1, + q => on12_x1_sig, + vdd => vdd, + vss => vss + ); + +s_0_ins : na3_x1 + port map ( + i0 => on12_x1_sig, + i1 => na3_x1_2_sig, + i2 => na3_x1_sig, + nq => s(0), + vdd => vdd, + vss => vss + ); + +na2_x1_ins : na2_x1 + port map ( + i0 => i(2), + i1 => aux3, + nq => na2_x1_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_3_ins : na3_x1 + port map ( + i0 => rb(1), + i1 => i(0), + i2 => not_i(2), + nq => na3_x1_3_sig, + vdd => vdd, + vss => vss + ); + +on12_x1_2_ins : on12_x1 + port map ( + i0 => accu(1), + i1 => not_aux1, + q => on12_x1_2_sig, + vdd => vdd, + vss => vss + ); + +s_1_ins : na3_x1 + port map ( + i0 => on12_x1_2_sig, + i1 => na3_x1_3_sig, + i2 => na2_x1_sig, + nq => s(1), + vdd => vdd, + vss => vss + ); + +inv_x2_ins : inv_x2 + port map ( + i => accu(2), + nq => inv_x2_sig, + vdd => vdd, + vss => vss + ); + +o3_x2_ins : o3_x2 + port map ( + i0 => i(0), + i1 => not_aux0, + i2 => inv_x2_sig, + q => o3_x2_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_4_ins : na3_x1 + port map ( + i0 => rb(2), + i1 => i(0), + i2 => not_i(2), + nq => na3_x1_4_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_2_ins : na2_x1 + port map ( + i0 => ra(2), + i1 => not_aux0, + nq => na2_x1_2_sig, + vdd => vdd, + vss => vss + ); + +s_2_ins : na3_x1 + port map ( + i0 => na2_x1_2_sig, + i1 => na3_x1_4_sig, + i2 => o3_x2_sig, + nq => s(2), + vdd => vdd, + vss => vss + ); + +a2_x2_ins : a2_x2 + port map ( + i0 => rb(3), + i1 => accu(3), + q => a2_x2_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_ins : nao22_x1 + port map ( + i0 => i(2), + i1 => a2_x2_sig, + i2 => aux4, + nq => nao22_x1_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_2_ins : inv_x2 + port map ( + i => accu(3), + nq => inv_x2_2_sig, + vdd => vdd, + vss => vss + ); + +o3_x2_2_ins : o3_x2 + port map ( + i0 => i(0), + i1 => not_aux0, + i2 => inv_x2_2_sig, + q => o3_x2_2_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_5_ins : na3_x1 + port map ( + i0 => rb(3), + i1 => i(0), + i2 => not_i(2), + nq => na3_x1_5_sig, + vdd => vdd, + vss => vss + ); + +s_3_ins : na3_x1 + port map ( + i0 => na3_x1_5_sig, + i1 => o3_x2_2_sig, + i2 => nao22_x1_sig, + nq => s(3), + vdd => vdd, + vss => vss + ); + +no2_x1_ins : no2_x1 + port map ( + i0 => ra(0), + i1 => i(2), + nq => no2_x1_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_2_ins : no2_x1 + port map ( + i0 => i(2), + i1 => not_i(1), + nq => no2_x1_2_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_3_ins : no2_x1 + port map ( + i0 => d(0), + i1 => not_i(2), + nq => no2_x1_3_sig, + vdd => vdd, + vss => vss + ); + +r_0_ins : no4_x1 + port map ( + i0 => no2_x1_3_sig, + i1 => not_aux2, + i2 => no2_x1_2_sig, + i3 => no2_x1_sig, + nq => r(0), + vdd => vdd, + vss => vss + ); + +no2_x1_4_ins : no2_x1 + port map ( + i0 => d(1), + i1 => not_i(2), + nq => no2_x1_4_sig, + vdd => vdd, + vss => vss + ); + +an12_x1_ins : an12_x1 + port map ( + i0 => aux3, + i1 => not_i(2), + q => an12_x1_sig, + vdd => vdd, + vss => vss + ); + +r_1_ins : no3_x1 + port map ( + i0 => not_aux2, + i1 => an12_x1_sig, + i2 => no2_x1_4_sig, + nq => r(1), + vdd => vdd, + vss => vss + ); + +na3_x1_6_ins : na3_x1 + port map ( + i0 => ra(2), + i1 => not_i(1), + i2 => not_i(2), + nq => na3_x1_6_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_3_ins : na2_x1 + port map ( + i0 => d(2), + i1 => i(2), + nq => na2_x1_3_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_2_ins : a2_x2 + port map ( + i0 => not_i(1), + i1 => not_i(0), + q => a2_x2_2_sig, + vdd => vdd, + vss => vss + ); + +r_2_ins : nao22_x1 + port map ( + i0 => a2_x2_2_sig, + i1 => na2_x1_3_sig, + i2 => na3_x1_6_sig, + nq => r(2), + vdd => vdd, + vss => vss + ); + +no2_x1_5_ins : no2_x1 + port map ( + i0 => d(3), + i1 => not_i(2), + nq => no2_x1_5_sig, + vdd => vdd, + vss => vss + ); + +an12_x1_2_ins : an12_x1 + port map ( + i0 => aux4, + i1 => not_i(2), + q => an12_x1_2_sig, + vdd => vdd, + vss => vss + ); + +r_3_ins : no3_x1 + port map ( + i0 => not_aux2, + i1 => an12_x1_2_sig, + i2 => no2_x1_5_sig, + nq => r(3), + vdd => vdd, + vss => vss + ); + + +end structural; diff --git a/documentation/examples/AM2901/muxs.vst b/documentation/examples/AM2901/muxs.vst new file mode 100644 index 00000000..585c9273 --- /dev/null +++ b/documentation/examples/AM2901/muxs.vst @@ -0,0 +1,226 @@ +entity muxs is + port ( + alu_out : in bit_vector(3 downto 0); + i : in bit_vector(2 downto 0); + noe : in bit; + oe : out bit; + ra : in bit_vector(3 downto 0); + shift_l : out bit; + shift_r : out bit; + vdd : in bit; + vss : in bit; + y : out mux_vector(3 downto 0) bus + ); +end muxs; + +architecture structural of muxs is +Component o3_x2 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component inv_x2 + port ( + i : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component an12_x1 + port ( + i0 : in bit; + i1 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component a2_x2 + port ( + i0 : in bit; + i1 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component buf_x2 + port ( + i : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component nmx2_x1 + port ( + cmd : in bit; + i0 : in bit; + i1 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component nts_x1 + port ( + cmd : in bit; + i : in bit; + nq : out mux_bit bus; + vdd : in bit; + vss : in bit + ); +end component; + +signal not_noe : bit; +signal not_aux1 : bit; +signal nmx2_x1_sig : bit; +signal nmx2_x1_4_sig : bit; +signal nmx2_x1_3_sig : bit; +signal nmx2_x1_2_sig : bit; +signal inv_x2_sig : bit; + +begin + +inv_x2_ins : inv_x2 + port map ( + i => i(1), + nq => inv_x2_sig, + vdd => vdd, + vss => vss + ); + +not_aux1_ins : o3_x2 + port map ( + i0 => i(0), + i1 => i(2), + i2 => inv_x2_sig, + q => not_aux1, + vdd => vdd, + vss => vss + ); + +not_noe_ins : inv_x2 + port map ( + i => noe, + nq => not_noe, + vdd => vdd, + vss => vss + ); + +shift_r_ins : an12_x1 + port map ( + i0 => i(1), + i1 => i(2), + q => shift_r, + vdd => vdd, + vss => vss + ); + +shift_l_ins : a2_x2 + port map ( + i0 => i(2), + i1 => i(1), + q => shift_l, + vdd => vdd, + vss => vss + ); + +oe_ins : buf_x2 + port map ( + i => not_noe, + q => oe, + vdd => vdd, + vss => vss + ); + +nmx2_x1_ins : nmx2_x1 + port map ( + cmd => not_aux1, + i0 => ra(0), + i1 => alu_out(0), + nq => nmx2_x1_sig, + vdd => vdd, + vss => vss + ); + +y_0_ins : nts_x1 + port map ( + cmd => not_noe, + i => nmx2_x1_sig, + nq => y(0), + vdd => vdd, + vss => vss + ); + +nmx2_x1_2_ins : nmx2_x1 + port map ( + cmd => not_aux1, + i0 => ra(1), + i1 => alu_out(1), + nq => nmx2_x1_2_sig, + vdd => vdd, + vss => vss + ); + +y_1_ins : nts_x1 + port map ( + cmd => not_noe, + i => nmx2_x1_2_sig, + nq => y(1), + vdd => vdd, + vss => vss + ); + +nmx2_x1_3_ins : nmx2_x1 + port map ( + cmd => not_aux1, + i0 => ra(2), + i1 => alu_out(2), + nq => nmx2_x1_3_sig, + vdd => vdd, + vss => vss + ); + +y_2_ins : nts_x1 + port map ( + cmd => not_noe, + i => nmx2_x1_3_sig, + nq => y(2), + vdd => vdd, + vss => vss + ); + +nmx2_x1_4_ins : nmx2_x1 + port map ( + cmd => not_aux1, + i0 => ra(3), + i1 => alu_out(3), + nq => nmx2_x1_4_sig, + vdd => vdd, + vss => vss + ); + +y_3_ins : nts_x1 + port map ( + cmd => not_noe, + i => nmx2_x1_4_sig, + nq => y(3), + vdd => vdd, + vss => vss + ); + + +end structural; diff --git a/documentation/examples/AM2901/ram.vst b/documentation/examples/AM2901/ram.vst new file mode 100644 index 00000000..dfdd21e6 --- /dev/null +++ b/documentation/examples/AM2901/ram.vst @@ -0,0 +1,6541 @@ +entity ram is + port ( + i : in bit_vector(2 downto 0); + a : in bit_vector(3 downto 0); + b : in bit_vector(3 downto 0); + alu_out : in bit_vector(3 downto 0); + ra : out bit_vector(3 downto 0); + rb : out bit_vector(3 downto 0); + clk : in bit; + r0_from_pads : in bit; + r0_to_pads : out bit; + r3_from_pads : in bit; + r3_to_pads : out bit; + vdd : in bit; + vss : in bit + ); +end ram; + +architecture structural of ram is +Component on12_x1 + port ( + i0 : in bit; + i1 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component nao22_x1 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component ao2o22_x2 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + i3 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component ao22_x2 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component oa22_x2 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component nao2o22_x1 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + i3 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component an12_x1 + port ( + i0 : in bit; + i1 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component oa2ao222_x2 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + i3 : in bit; + i4 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component noa3ao322_x1 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + i3 : in bit; + i4 : in bit; + i5 : in bit; + i6 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component na2_x1 + port ( + i0 : in bit; + i1 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component oa2a22_x2 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + i3 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component sff1_x4 + port ( + ck : in bit; + i : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component buf_x2 + port ( + i : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component o2_x2 + port ( + i0 : in bit; + i1 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component no4_x1 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + i3 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component inv_x2 + port ( + i : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component no3_x1 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component o3_x2 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component na4_x1 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + i3 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component noa22_x1 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component noa2a2a23_x1 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + i3 : in bit; + i4 : in bit; + i5 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component a3_x2 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component no2_x1 + port ( + i0 : in bit; + i1 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component noa2a2a2a24_x1 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + i3 : in bit; + i4 : in bit; + i5 : in bit; + i6 : in bit; + i7 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component a2_x2 + port ( + i0 : in bit; + i1 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component a4_x2 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + i3 : in bit; + q : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +Component na3_x1 + port ( + i0 : in bit; + i1 : in bit; + i2 : in bit; + nq : out bit; + vdd : in bit; + vss : in bit + ); +end component; + +signal not_a : bit_vector( 2 downto 2); +signal not_alu_out : bit_vector( 3 downto 0); +signal not_b : bit_vector( 3 downto 1); +signal not_i : bit_vector( 2 downto 1); +signal not_ram_idx_11 : bit_vector( 2 downto 2); +signal not_ram_idx_12 : bit_vector( 1 downto 1); +signal not_ram_idx_13 : bit_vector( 3 downto 0); +signal not_ram_idx_15 : bit_vector( 3 downto 0); +signal not_ram_idx_2 : bit_vector( 2 downto 2); +signal not_ram_idx_3 : bit_vector( 0 downto 0); +signal not_ram_idx_7 : bit_vector( 2 downto 2); +signal not_ram_idx_9 : bit_vector( 3 downto 0); +signal ram_idx_0 : bit_vector( 3 downto 0); +signal ram_idx_1 : bit_vector( 3 downto 0); +signal ram_idx_10 : bit_vector( 3 downto 0); +signal ram_idx_11 : bit_vector( 3 downto 0); +signal ram_idx_12 : bit_vector( 3 downto 0); +signal ram_idx_13 : bit_vector( 3 downto 0); +signal ram_idx_14 : bit_vector( 3 downto 0); +signal ram_idx_15 : bit_vector( 3 downto 0); +signal ram_idx_2 : bit_vector( 3 downto 0); +signal ram_idx_3 : bit_vector( 3 downto 0); +signal ram_idx_4 : bit_vector( 3 downto 0); +signal ram_idx_5 : bit_vector( 3 downto 0); +signal ram_idx_6 : bit_vector( 3 downto 0); +signal ram_idx_7 : bit_vector( 3 downto 0); +signal ram_idx_8 : bit_vector( 3 downto 0); +signal ram_idx_9 : bit_vector( 3 downto 0); +signal on12_x1_sig : bit; +signal oa2ao222_x2_sig : bit; +signal oa2ao222_x2_9_sig : bit; +signal oa2ao222_x2_8_sig : bit; +signal oa2ao222_x2_7_sig : bit; +signal oa2ao222_x2_6_sig : bit; +signal oa2ao222_x2_5_sig : bit; +signal oa2ao222_x2_4_sig : bit; +signal oa2ao222_x2_3_sig : bit; +signal oa2ao222_x2_2_sig : bit; +signal oa2a22_x2_sig : bit; +signal oa2a22_x2_9_sig : bit; +signal oa2a22_x2_8_sig : bit; +signal oa2a22_x2_7_sig : bit; +signal oa2a22_x2_6_sig : bit; +signal oa2a22_x2_5_sig : bit; +signal oa2a22_x2_4_sig : bit; +signal oa2a22_x2_3_sig : bit; +signal oa2a22_x2_2_sig : bit; +signal oa2a22_x2_13_sig : bit; +signal oa2a22_x2_12_sig : bit; +signal oa2a22_x2_11_sig : bit; +signal oa2a22_x2_10_sig : bit; +signal oa22_x2_sig : bit; +signal oa22_x2_4_sig : bit; +signal oa22_x2_3_sig : bit; +signal oa22_x2_2_sig : bit; +signal o3_x2_sig : bit; +signal o3_x2_9_sig : bit; +signal o3_x2_8_sig : bit; +signal o3_x2_7_sig : bit; +signal o3_x2_6_sig : bit; +signal o3_x2_5_sig : bit; +signal o3_x2_4_sig : bit; +signal o3_x2_3_sig : bit; +signal o3_x2_2_sig : bit; +signal o3_x2_14_sig : bit; +signal o3_x2_13_sig : bit; +signal o3_x2_12_sig : bit; +signal o3_x2_11_sig : bit; +signal o3_x2_10_sig : bit; +signal o2_x2_sig : bit; +signal not_aux99 : bit; +signal not_aux98 : bit; +signal not_aux95 : bit; +signal not_aux90 : bit; +signal not_aux89 : bit; +signal not_aux83 : bit; +signal not_aux82 : bit; +signal not_aux81 : bit; +signal not_aux8 : bit; +signal not_aux78 : bit; +signal not_aux77 : bit; +signal not_aux76 : bit; +signal not_aux72 : bit; +signal not_aux70 : bit; +signal not_aux7 : bit; +signal not_aux68 : bit; +signal not_aux67 : bit; +signal not_aux65 : bit; +signal not_aux63 : bit; +signal not_aux60 : bit; +signal not_aux6 : bit; +signal not_aux58 : bit; +signal not_aux57 : bit; +signal not_aux55 : bit; +signal not_aux54 : bit; +signal not_aux52 : bit; +signal not_aux51 : bit; +signal not_aux50 : bit; +signal not_aux49 : bit; +signal not_aux48 : bit; +signal not_aux47 : bit; +signal not_aux46 : bit; +signal not_aux44 : bit; +signal not_aux41 : bit; +signal not_aux40 : bit; +signal not_aux4 : bit; +signal not_aux39 : bit; +signal not_aux32 : bit; +signal not_aux31 : bit; +signal not_aux30 : bit; +signal not_aux3 : bit; +signal not_aux23 : bit; +signal not_aux22 : bit; +signal not_aux21 : bit; +signal not_aux14 : bit; +signal not_aux120 : bit; +signal not_aux12 : bit; +signal not_aux119 : bit; +signal not_aux118 : bit; +signal not_aux117 : bit; +signal not_aux116 : bit; +signal not_aux115 : bit; +signal not_aux114 : bit; +signal not_aux113 : bit; +signal not_aux112 : bit; +signal not_aux111 : bit; +signal not_aux110 : bit; +signal not_aux11 : bit; +signal not_aux109 : bit; +signal not_aux108 : bit; +signal not_aux107 : bit; +signal not_aux106 : bit; +signal not_aux105 : bit; +signal not_aux104 : bit; +signal not_aux103 : bit; +signal not_aux102 : bit; +signal not_aux101 : bit; +signal not_aux100 : bit; +signal not_aux10 : bit; +signal noa3ao322_x1_sig : bit; +signal noa2a2a2a24_x1_sig : bit; +signal noa2a2a2a24_x1_4_sig : bit; +signal noa2a2a2a24_x1_3_sig : bit; +signal noa2a2a2a24_x1_2_sig : bit; +signal noa2a2a23_x1_sig : bit; +signal noa2a2a23_x1_4_sig : bit; +signal noa2a2a23_x1_3_sig : bit; +signal noa2a2a23_x1_2_sig : bit; +signal noa22_x1_sig : bit; +signal noa22_x1_9_sig : bit; +signal noa22_x1_8_sig : bit; +signal noa22_x1_7_sig : bit; +signal noa22_x1_6_sig : bit; +signal noa22_x1_5_sig : bit; +signal noa22_x1_4_sig : bit; +signal noa22_x1_3_sig : bit; +signal noa22_x1_2_sig : bit; +signal noa22_x1_10_sig : bit; +signal no4_x1_sig : bit; +signal no4_x1_2_sig : bit; +signal no3_x1_sig : bit; +signal no3_x1_9_sig : bit; +signal no3_x1_8_sig : bit; +signal no3_x1_7_sig : bit; +signal no3_x1_6_sig : bit; +signal no3_x1_5_sig : bit; +signal no3_x1_4_sig : bit; +signal no3_x1_3_sig : bit; +signal no3_x1_2_sig : bit; +signal no3_x1_28_sig : bit; +signal no3_x1_27_sig : bit; +signal no3_x1_26_sig : bit; +signal no3_x1_25_sig : bit; +signal no3_x1_24_sig : bit; +signal no3_x1_23_sig : bit; +signal no3_x1_22_sig : bit; +signal no3_x1_21_sig : bit; +signal no3_x1_20_sig : bit; +signal no3_x1_19_sig : bit; +signal no3_x1_18_sig : bit; +signal no3_x1_17_sig : bit; +signal no3_x1_16_sig : bit; +signal no3_x1_15_sig : bit; +signal no3_x1_14_sig : bit; +signal no3_x1_13_sig : bit; +signal no3_x1_12_sig : bit; +signal no3_x1_11_sig : bit; +signal no3_x1_10_sig : bit; +signal no2_x1_sig : bit; +signal no2_x1_9_sig : bit; +signal no2_x1_8_sig : bit; +signal no2_x1_7_sig : bit; +signal no2_x1_6_sig : bit; +signal no2_x1_5_sig : bit; +signal no2_x1_4_sig : bit; +signal no2_x1_42_sig : bit; +signal no2_x1_41_sig : bit; +signal no2_x1_40_sig : bit; +signal no2_x1_3_sig : bit; +signal no2_x1_39_sig : bit; +signal no2_x1_38_sig : bit; +signal no2_x1_37_sig : bit; +signal no2_x1_36_sig : bit; +signal no2_x1_35_sig : bit; +signal no2_x1_34_sig : bit; +signal no2_x1_33_sig : bit; +signal no2_x1_32_sig : bit; +signal no2_x1_31_sig : bit; +signal no2_x1_30_sig : bit; +signal no2_x1_2_sig : bit; +signal no2_x1_29_sig : bit; +signal no2_x1_28_sig : bit; +signal no2_x1_27_sig : bit; +signal no2_x1_26_sig : bit; +signal no2_x1_25_sig : bit; +signal no2_x1_24_sig : bit; +signal no2_x1_23_sig : bit; +signal no2_x1_22_sig : bit; +signal no2_x1_21_sig : bit; +signal no2_x1_20_sig : bit; +signal no2_x1_19_sig : bit; +signal no2_x1_18_sig : bit; +signal no2_x1_17_sig : bit; +signal no2_x1_16_sig : bit; +signal no2_x1_15_sig : bit; +signal no2_x1_14_sig : bit; +signal no2_x1_13_sig : bit; +signal no2_x1_12_sig : bit; +signal no2_x1_11_sig : bit; +signal no2_x1_10_sig : bit; +signal nao2o22_x1_sig : bit; +signal nao2o22_x1_2_sig : bit; +signal nao22_x1_sig : bit; +signal na4_x1_sig : bit; +signal na4_x1_4_sig : bit; +signal na4_x1_3_sig : bit; +signal na4_x1_2_sig : bit; +signal na3_x1_sig : bit; +signal na3_x1_9_sig : bit; +signal na3_x1_8_sig : bit; +signal na3_x1_7_sig : bit; +signal na3_x1_6_sig : bit; +signal na3_x1_5_sig : bit; +signal na3_x1_51_sig : bit; +signal na3_x1_50_sig : bit; +signal na3_x1_4_sig : bit; +signal na3_x1_49_sig : bit; +signal na3_x1_48_sig : bit; +signal na3_x1_47_sig : bit; +signal na3_x1_46_sig : bit; +signal na3_x1_45_sig : bit; +signal na3_x1_44_sig : bit; +signal na3_x1_43_sig : bit; +signal na3_x1_42_sig : bit; +signal na3_x1_41_sig : bit; +signal na3_x1_40_sig : bit; +signal na3_x1_3_sig : bit; +signal na3_x1_39_sig : bit; +signal na3_x1_38_sig : bit; +signal na3_x1_37_sig : bit; +signal na3_x1_36_sig : bit; +signal na3_x1_35_sig : bit; +signal na3_x1_34_sig : bit; +signal na3_x1_33_sig : bit; +signal na3_x1_32_sig : bit; +signal na3_x1_31_sig : bit; +signal na3_x1_30_sig : bit; +signal na3_x1_2_sig : bit; +signal na3_x1_29_sig : bit; +signal na3_x1_28_sig : bit; +signal na3_x1_27_sig : bit; +signal na3_x1_26_sig : bit; +signal na3_x1_25_sig : bit; +signal na3_x1_24_sig : bit; +signal na3_x1_23_sig : bit; +signal na3_x1_22_sig : bit; +signal na3_x1_21_sig : bit; +signal na3_x1_20_sig : bit; +signal na3_x1_19_sig : bit; +signal na3_x1_18_sig : bit; +signal na3_x1_17_sig : bit; +signal na3_x1_16_sig : bit; +signal na3_x1_15_sig : bit; +signal na3_x1_14_sig : bit; +signal na3_x1_13_sig : bit; +signal na3_x1_12_sig : bit; +signal na3_x1_11_sig : bit; +signal na3_x1_10_sig : bit; +signal na2_x1_sig : bit; +signal na2_x1_9_sig : bit; +signal na2_x1_8_sig : bit; +signal na2_x1_7_sig : bit; +signal na2_x1_6_sig : bit; +signal na2_x1_5_sig : bit; +signal na2_x1_4_sig : bit; +signal na2_x1_3_sig : bit; +signal na2_x1_2_sig : bit; +signal na2_x1_21_sig : bit; +signal na2_x1_20_sig : bit; +signal na2_x1_19_sig : bit; +signal na2_x1_18_sig : bit; +signal na2_x1_17_sig : bit; +signal na2_x1_16_sig : bit; +signal na2_x1_15_sig : bit; +signal na2_x1_14_sig : bit; +signal na2_x1_13_sig : bit; +signal na2_x1_12_sig : bit; +signal na2_x1_11_sig : bit; +signal na2_x1_10_sig : bit; +signal inv_x2_sig : bit; +signal inv_x2_9_sig : bit; +signal inv_x2_8_sig : bit; +signal inv_x2_7_sig : bit; +signal inv_x2_6_sig : bit; +signal inv_x2_62_sig : bit; +signal inv_x2_61_sig : bit; +signal inv_x2_60_sig : bit; +signal inv_x2_5_sig : bit; +signal inv_x2_59_sig : bit; +signal inv_x2_58_sig : bit; +signal inv_x2_57_sig : bit; +signal inv_x2_56_sig : bit; +signal inv_x2_55_sig : bit; +signal inv_x2_54_sig : bit; +signal inv_x2_53_sig : bit; +signal inv_x2_52_sig : bit; +signal inv_x2_51_sig : bit; +signal inv_x2_50_sig : bit; +signal inv_x2_4_sig : bit; +signal inv_x2_49_sig : bit; +signal inv_x2_48_sig : bit; +signal inv_x2_47_sig : bit; +signal inv_x2_46_sig : bit; +signal inv_x2_45_sig : bit; +signal inv_x2_44_sig : bit; +signal inv_x2_43_sig : bit; +signal inv_x2_42_sig : bit; +signal inv_x2_41_sig : bit; +signal inv_x2_40_sig : bit; +signal inv_x2_3_sig : bit; +signal inv_x2_39_sig : bit; +signal inv_x2_38_sig : bit; +signal inv_x2_37_sig : bit; +signal inv_x2_36_sig : bit; +signal inv_x2_35_sig : bit; +signal inv_x2_34_sig : bit; +signal inv_x2_33_sig : bit; +signal inv_x2_32_sig : bit; +signal inv_x2_31_sig : bit; +signal inv_x2_30_sig : bit; +signal inv_x2_2_sig : bit; +signal inv_x2_29_sig : bit; +signal inv_x2_28_sig : bit; +signal inv_x2_27_sig : bit; +signal inv_x2_26_sig : bit; +signal inv_x2_25_sig : bit; +signal inv_x2_24_sig : bit; +signal inv_x2_23_sig : bit; +signal inv_x2_22_sig : bit; +signal inv_x2_21_sig : bit; +signal inv_x2_20_sig : bit; +signal inv_x2_19_sig : bit; +signal inv_x2_18_sig : bit; +signal inv_x2_17_sig : bit; +signal inv_x2_16_sig : bit; +signal inv_x2_15_sig : bit; +signal inv_x2_14_sig : bit; +signal inv_x2_13_sig : bit; +signal inv_x2_12_sig : bit; +signal inv_x2_11_sig : bit; +signal inv_x2_10_sig : bit; +signal aux99 : bit; +signal aux97 : bit; +signal aux96 : bit; +signal aux94 : bit; +signal aux93 : bit; +signal aux92 : bit; +signal aux91 : bit; +signal aux90 : bit; +signal aux9 : bit; +signal aux87 : bit; +signal aux86 : bit; +signal aux84 : bit; +signal aux83 : bit; +signal aux82 : bit; +signal aux80 : bit; +signal aux8 : bit; +signal aux79 : bit; +signal aux78 : bit; +signal aux75 : bit; +signal aux74 : bit; +signal aux73 : bit; +signal aux72 : bit; +signal aux71 : bit; +signal aux70 : bit; +signal aux69 : bit; +signal aux66 : bit; +signal aux64 : bit; +signal aux63 : bit; +signal aux61 : bit; +signal aux60 : bit; +signal aux59 : bit; +signal aux58 : bit; +signal aux56 : bit; +signal aux55 : bit; +signal aux53 : bit; +signal aux49 : bit; +signal aux46 : bit; +signal aux43 : bit; +signal aux42 : bit; +signal aux41 : bit; +signal aux33 : bit; +signal aux32 : bit; +signal aux24 : bit; +signal aux23 : bit; +signal aux15 : bit; +signal aux13 : bit; +signal aux120 : bit; +signal aux12 : bit; +signal aux119 : bit; +signal aux118 : bit; +signal aux117 : bit; +signal aux116 : bit; +signal aux114 : bit; +signal aux112 : bit; +signal aux111 : bit; +signal aux110 : bit; +signal aux109 : bit; +signal aux108 : bit; +signal aux107 : bit; +signal aux105 : bit; +signal aux103 : bit; +signal aux101 : bit; +signal aux0 : bit; +signal ao2o22_x2_sig : bit; +signal ao2o22_x2_9_sig : bit; +signal ao2o22_x2_8_sig : bit; +signal ao2o22_x2_7_sig : bit; +signal ao2o22_x2_6_sig : bit; +signal ao2o22_x2_5_sig : bit; +signal ao2o22_x2_4_sig : bit; +signal ao2o22_x2_3_sig : bit; +signal ao2o22_x2_2_sig : bit; +signal ao2o22_x2_29_sig : bit; +signal ao2o22_x2_28_sig : bit; +signal ao2o22_x2_27_sig : bit; +signal ao2o22_x2_26_sig : bit; +signal ao2o22_x2_25_sig : bit; +signal ao2o22_x2_24_sig : bit; +signal ao2o22_x2_23_sig : bit; +signal ao2o22_x2_22_sig : bit; +signal ao2o22_x2_21_sig : bit; +signal ao2o22_x2_20_sig : bit; +signal ao2o22_x2_19_sig : bit; +signal ao2o22_x2_18_sig : bit; +signal ao2o22_x2_17_sig : bit; +signal ao2o22_x2_16_sig : bit; +signal ao2o22_x2_15_sig : bit; +signal ao2o22_x2_14_sig : bit; +signal ao2o22_x2_13_sig : bit; +signal ao2o22_x2_12_sig : bit; +signal ao2o22_x2_11_sig : bit; +signal ao2o22_x2_10_sig : bit; +signal ao22_x2_sig : bit; +signal ao22_x2_3_sig : bit; +signal ao22_x2_2_sig : bit; +signal an12_x1_sig : bit; +signal an12_x1_2_sig : bit; +signal a4_x2_sig : bit; +signal a4_x2_4_sig : bit; +signal a4_x2_3_sig : bit; +signal a4_x2_2_sig : bit; +signal a3_x2_sig : bit; +signal a3_x2_9_sig : bit; +signal a3_x2_8_sig : bit; +signal a3_x2_7_sig : bit; +signal a3_x2_6_sig : bit; +signal a3_x2_5_sig : bit; +signal a3_x2_4_sig : bit; +signal a3_x2_3_sig : bit; +signal a3_x2_38_sig : bit; +signal a3_x2_37_sig : bit; +signal a3_x2_36_sig : bit; +signal a3_x2_35_sig : bit; +signal a3_x2_34_sig : bit; +signal a3_x2_33_sig : bit; +signal a3_x2_32_sig : bit; +signal a3_x2_31_sig : bit; +signal a3_x2_30_sig : bit; +signal a3_x2_2_sig : bit; +signal a3_x2_29_sig : bit; +signal a3_x2_28_sig : bit; +signal a3_x2_27_sig : bit; +signal a3_x2_26_sig : bit; +signal a3_x2_25_sig : bit; +signal a3_x2_24_sig : bit; +signal a3_x2_23_sig : bit; +signal a3_x2_22_sig : bit; +signal a3_x2_21_sig : bit; +signal a3_x2_20_sig : bit; +signal a3_x2_19_sig : bit; +signal a3_x2_18_sig : bit; +signal a3_x2_17_sig : bit; +signal a3_x2_16_sig : bit; +signal a3_x2_15_sig : bit; +signal a3_x2_14_sig : bit; +signal a3_x2_13_sig : bit; +signal a3_x2_12_sig : bit; +signal a3_x2_11_sig : bit; +signal a3_x2_10_sig : bit; +signal a2_x2_sig : bit; +signal a2_x2_9_sig : bit; +signal a2_x2_8_sig : bit; +signal a2_x2_7_sig : bit; +signal a2_x2_6_sig : bit; +signal a2_x2_5_sig : bit; +signal a2_x2_4_sig : bit; +signal a2_x2_3_sig : bit; +signal a2_x2_2_sig : bit; +signal a2_x2_24_sig : bit; +signal a2_x2_23_sig : bit; +signal a2_x2_22_sig : bit; +signal a2_x2_21_sig : bit; +signal a2_x2_20_sig : bit; +signal a2_x2_19_sig : bit; +signal a2_x2_18_sig : bit; +signal a2_x2_17_sig : bit; +signal a2_x2_16_sig : bit; +signal a2_x2_15_sig : bit; +signal a2_x2_14_sig : bit; +signal a2_x2_13_sig : bit; +signal a2_x2_12_sig : bit; +signal a2_x2_11_sig : bit; +signal a2_x2_10_sig : bit; + +begin + +not_aux111_ins : inv_x2 + port map ( + i => aux111, + nq => not_aux111, + vdd => vdd, + vss => vss + ); + +not_aux110_ins : inv_x2 + port map ( + i => aux110, + nq => not_aux110, + vdd => vdd, + vss => vss + ); + +not_aux109_ins : inv_x2 + port map ( + i => aux109, + nq => not_aux109, + vdd => vdd, + vss => vss + ); + +not_aux108_ins : inv_x2 + port map ( + i => aux108, + nq => not_aux108, + vdd => vdd, + vss => vss + ); + +not_aux107_ins : inv_x2 + port map ( + i => aux107, + nq => not_aux107, + vdd => vdd, + vss => vss + ); + +not_aux106_ins : na2_x1 + port map ( + i0 => a(1), + i1 => a(0), + nq => not_aux106, + vdd => vdd, + vss => vss + ); + +not_aux105_ins : inv_x2 + port map ( + i => aux105, + nq => not_aux105, + vdd => vdd, + vss => vss + ); + +not_aux104_ins : on12_x1 + port map ( + i0 => a(1), + i1 => a(0), + q => not_aux104, + vdd => vdd, + vss => vss + ); + +not_aux103_ins : inv_x2 + port map ( + i => aux103, + nq => not_aux103, + vdd => vdd, + vss => vss + ); + +not_aux102_ins : on12_x1 + port map ( + i0 => a(0), + i1 => a(1), + q => not_aux102, + vdd => vdd, + vss => vss + ); + +not_aux101_ins : inv_x2 + port map ( + i => aux101, + nq => not_aux101, + vdd => vdd, + vss => vss + ); + +not_aux100_ins : o2_x2 + port map ( + i0 => a(1), + i1 => a(0), + q => not_aux100, + vdd => vdd, + vss => vss + ); + +not_aux120_ins : inv_x2 + port map ( + i => aux120, + nq => not_aux120, + vdd => vdd, + vss => vss + ); + +not_aux119_ins : inv_x2 + port map ( + i => aux119, + nq => not_aux119, + vdd => vdd, + vss => vss + ); + +not_aux118_ins : inv_x2 + port map ( + i => aux118, + nq => not_aux118, + vdd => vdd, + vss => vss + ); + +not_aux117_ins : inv_x2 + port map ( + i => aux117, + nq => not_aux117, + vdd => vdd, + vss => vss + ); + +not_aux116_ins : inv_x2 + port map ( + i => aux116, + nq => not_aux116, + vdd => vdd, + vss => vss + ); + +not_aux115_ins : na2_x1 + port map ( + i0 => b(1), + i1 => b(2), + nq => not_aux115, + vdd => vdd, + vss => vss + ); + +not_aux114_ins : inv_x2 + port map ( + i => aux114, + nq => not_aux114, + vdd => vdd, + vss => vss + ); + +not_aux113_ins : o2_x2 + port map ( + i0 => b(1), + i1 => not_b(2), + q => not_aux113, + vdd => vdd, + vss => vss + ); + +not_aux112_ins : inv_x2 + port map ( + i => aux112, + nq => not_aux112, + vdd => vdd, + vss => vss + ); + +not_ram_idx_15_3_ins : inv_x2 + port map ( + i => ram_idx_15(3), + nq => not_ram_idx_15(3), + vdd => vdd, + vss => vss + ); + +not_ram_idx_15_2_ins : inv_x2 + port map ( + i => ram_idx_15(2), + nq => not_ram_idx_15(2), + vdd => vdd, + vss => vss + ); + +not_ram_idx_15_0_ins : inv_x2 + port map ( + i => ram_idx_15(0), + nq => not_ram_idx_15(0), + vdd => vdd, + vss => vss + ); + +not_ram_idx_13_3_ins : inv_x2 + port map ( + i => ram_idx_13(3), + nq => not_ram_idx_13(3), + vdd => vdd, + vss => vss + ); + +not_ram_idx_13_2_ins : inv_x2 + port map ( + i => ram_idx_13(2), + nq => not_ram_idx_13(2), + vdd => vdd, + vss => vss + ); + +not_aux99_ins : inv_x2 + port map ( + i => aux99, + nq => not_aux99, + vdd => vdd, + vss => vss + ); + +not_aux98_ins : o2_x2 + port map ( + i0 => b(2), + i1 => not_b(1), + q => not_aux98, + vdd => vdd, + vss => vss + ); + +not_ram_idx_13_1_ins : inv_x2 + port map ( + i => ram_idx_13(1), + nq => not_ram_idx_13(1), + vdd => vdd, + vss => vss + ); + +not_ram_idx_13_0_ins : inv_x2 + port map ( + i => ram_idx_13(0), + nq => not_ram_idx_13(0), + vdd => vdd, + vss => vss + ); + +not_ram_idx_12_1_ins : inv_x2 + port map ( + i => ram_idx_12(1), + nq => not_ram_idx_12(1), + vdd => vdd, + vss => vss + ); + +not_ram_idx_11_2_ins : inv_x2 + port map ( + i => ram_idx_11(2), + nq => not_ram_idx_11(2), + vdd => vdd, + vss => vss + ); + +not_aux95_ins : na2_x1 + port map ( + i0 => b(0), + i1 => not_b(3), + nq => not_aux95, + vdd => vdd, + vss => vss + ); + +not_ram_idx_9_3_ins : inv_x2 + port map ( + i => ram_idx_9(3), + nq => not_ram_idx_9(3), + vdd => vdd, + vss => vss + ); + +not_ram_idx_9_2_ins : inv_x2 + port map ( + i => ram_idx_9(2), + nq => not_ram_idx_9(2), + vdd => vdd, + vss => vss + ); + +not_ram_idx_9_1_ins : inv_x2 + port map ( + i => ram_idx_9(1), + nq => not_ram_idx_9(1), + vdd => vdd, + vss => vss + ); + +not_aux90_ins : inv_x2 + port map ( + i => aux90, + nq => not_aux90, + vdd => vdd, + vss => vss + ); + +not_ram_idx_9_0_ins : inv_x2 + port map ( + i => ram_idx_9(0), + nq => not_ram_idx_9(0), + vdd => vdd, + vss => vss + ); + +not_aux89_ins : na3_x1 + port map ( + i0 => not_b(3), + i1 => b(0), + i2 => aux12, + nq => not_aux89, + vdd => vdd, + vss => vss + ); + +not_ram_idx_7_2_ins : inv_x2 + port map ( + i => ram_idx_7(2), + nq => not_ram_idx_7(2), + vdd => vdd, + vss => vss + ); + +not_aux83_ins : inv_x2 + port map ( + i => aux83, + nq => not_aux83, + vdd => vdd, + vss => vss + ); + +not_aux82_ins : inv_x2 + port map ( + i => aux82, + nq => not_aux82, + vdd => vdd, + vss => vss + ); + +not_aux78_ins : inv_x2 + port map ( + i => aux78, + nq => not_aux78, + vdd => vdd, + vss => vss + ); + +not_aux81_ins : na2_x1 + port map ( + i0 => b(0), + i1 => aux80, + nq => not_aux81, + vdd => vdd, + vss => vss + ); + +not_aux76_ins : o2_x2 + port map ( + i0 => b(2), + i1 => not_aux47, + q => not_aux76, + vdd => vdd, + vss => vss + ); + +not_aux77_ins : o2_x2 + port map ( + i0 => b(1), + i1 => b(2), + q => not_aux77, + vdd => vdd, + vss => vss + ); + +not_aux72_ins : inv_x2 + port map ( + i => aux72, + nq => not_aux72, + vdd => vdd, + vss => vss + ); + +not_aux70_ins : inv_x2 + port map ( + i => aux70, + nq => not_aux70, + vdd => vdd, + vss => vss + ); + +not_aux68_ins : a2_x2 + port map ( + i0 => not_aux22, + i1 => not_b(2), + q => not_aux68, + vdd => vdd, + vss => vss + ); + +not_aux63_ins : inv_x2 + port map ( + i => aux63, + nq => not_aux63, + vdd => vdd, + vss => vss + ); + +not_aux67_ins : na2_x1 + port map ( + i0 => b(0), + i1 => aux66, + nq => not_aux67, + vdd => vdd, + vss => vss + ); + +not_aux65_ins : o2_x2 + port map ( + i0 => b(2), + i1 => not_aux11, + q => not_aux65, + vdd => vdd, + vss => vss + ); + +not_aux60_ins : inv_x2 + port map ( + i => aux60, + nq => not_aux60, + vdd => vdd, + vss => vss + ); + +not_ram_idx_3_0_ins : inv_x2 + port map ( + i => ram_idx_3(0), + nq => not_ram_idx_3(0), + vdd => vdd, + vss => vss + ); + +not_aux58_ins : inv_x2 + port map ( + i => aux58, + nq => not_aux58, + vdd => vdd, + vss => vss + ); + +not_aux57_ins : a2_x2 + port map ( + i0 => not_b(1), + i1 => not_aux39, + q => not_aux57, + vdd => vdd, + vss => vss + ); + +not_aux55_ins : inv_x2 + port map ( + i => aux55, + nq => not_aux55, + vdd => vdd, + vss => vss + ); + +not_aux54_ins : a2_x2 + port map ( + i0 => not_b(1), + i1 => not_aux30, + q => not_aux54, + vdd => vdd, + vss => vss + ); + +not_ram_idx_2_2_ins : inv_x2 + port map ( + i => ram_idx_2(2), + nq => not_ram_idx_2(2), + vdd => vdd, + vss => vss + ); + +not_aux52_ins : a2_x2 + port map ( + i0 => b(2), + i1 => not_aux51, + q => not_aux52, + vdd => vdd, + vss => vss + ); + +not_aux51_ins : a2_x2 + port map ( + i0 => not_b(1), + i1 => not_aux21, + q => not_aux51, + vdd => vdd, + vss => vss + ); + +not_aux46_ins : inv_x2 + port map ( + i => aux46, + nq => not_aux46, + vdd => vdd, + vss => vss + ); + +not_aux44_ins : a2_x2 + port map ( + i0 => not_b(1), + i1 => not_aux3, + q => not_aux44, + vdd => vdd, + vss => vss + ); + +not_aux50_ins : na2_x1 + port map ( + i0 => b(0), + i1 => aux49, + nq => not_aux50, + vdd => vdd, + vss => vss + ); + +not_aux49_ins : inv_x2 + port map ( + i => aux49, + nq => not_aux49, + vdd => vdd, + vss => vss + ); + +not_aux48_ins : o2_x2 + port map ( + i0 => not_aux47, + i1 => not_b(2), + q => not_aux48, + vdd => vdd, + vss => vss + ); + +not_aux47_ins : o2_x2 + port map ( + i0 => b(1), + i1 => not_aux10, + q => not_aux47, + vdd => vdd, + vss => vss + ); + +not_aux41_ins : inv_x2 + port map ( + i => aux41, + nq => not_aux41, + vdd => vdd, + vss => vss + ); + +not_aux40_ins : a2_x2 + port map ( + i0 => b(1), + i1 => not_aux39, + q => not_aux40, + vdd => vdd, + vss => vss + ); + +na2_x1_ins : na2_x1 + port map ( + i0 => not_i(2), + i1 => not_alu_out(3), + nq => na2_x1_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_ins : a3_x2 + port map ( + i0 => i(1), + i1 => na2_x1_sig, + i2 => aux15, + q => a3_x2_sig, + vdd => vdd, + vss => vss + ); + +on12_x1_ins : on12_x1 + port map ( + i0 => i(2), + i1 => r3_from_pads, + q => on12_x1_sig, + vdd => vdd, + vss => vss + ); + +not_aux39_ins : noa22_x1 + port map ( + i0 => on12_x1_sig, + i1 => not_i(1), + i2 => a3_x2_sig, + nq => not_aux39, + vdd => vdd, + vss => vss + ); + +not_aux32_ins : inv_x2 + port map ( + i => aux32, + nq => not_aux32, + vdd => vdd, + vss => vss + ); + +not_aux31_ins : a2_x2 + port map ( + i0 => b(1), + i1 => not_aux30, + q => not_aux31, + vdd => vdd, + vss => vss + ); + +na2_x1_2_ins : na2_x1 + port map ( + i0 => not_alu_out(2), + i1 => not_i(2), + nq => na2_x1_2_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_2_ins : a3_x2 + port map ( + i0 => i(1), + i1 => na2_x1_2_sig, + i2 => aux0, + q => a3_x2_2_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_3_ins : na2_x1 + port map ( + i0 => i(2), + i1 => not_alu_out(3), + nq => na2_x1_3_sig, + vdd => vdd, + vss => vss + ); + +not_aux30_ins : noa22_x1 + port map ( + i0 => na2_x1_3_sig, + i1 => not_i(1), + i2 => a3_x2_2_sig, + nq => not_aux30, + vdd => vdd, + vss => vss + ); + +not_aux23_ins : inv_x2 + port map ( + i => aux23, + nq => not_aux23, + vdd => vdd, + vss => vss + ); + +not_aux22_ins : a2_x2 + port map ( + i0 => b(1), + i1 => not_aux21, + q => not_aux22, + vdd => vdd, + vss => vss + ); + +na2_x1_4_ins : na2_x1 + port map ( + i0 => not_alu_out(1), + i1 => not_i(2), + nq => na2_x1_4_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_5_ins : na2_x1 + port map ( + i0 => i(2), + i1 => not_alu_out(0), + nq => na2_x1_5_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_3_ins : a3_x2 + port map ( + i0 => i(1), + i1 => na2_x1_5_sig, + i2 => na2_x1_4_sig, + q => a3_x2_3_sig, + vdd => vdd, + vss => vss + ); + +not_aux21_ins : noa22_x1 + port map ( + i0 => aux15, + i1 => not_i(1), + i2 => a3_x2_3_sig, + nq => not_aux21, + vdd => vdd, + vss => vss + ); + +not_aux8_ins : inv_x2 + port map ( + i => aux8, + nq => not_aux8, + vdd => vdd, + vss => vss + ); + +not_aux7_ins : on12_x1 + port map ( + i0 => r0_from_pads, + i1 => not_aux6, + q => not_aux7, + vdd => vdd, + vss => vss + ); + +not_aux6_ins : na2_x1 + port map ( + i0 => i(2), + i1 => i(1), + nq => not_aux6, + vdd => vdd, + vss => vss + ); + +not_aux4_ins : a2_x2 + port map ( + i0 => b(1), + i1 => not_aux3, + q => not_aux4, + vdd => vdd, + vss => vss + ); + +no2_x1_ins : no2_x1 + port map ( + i0 => i(2), + i1 => not_alu_out(0), + nq => no2_x1_sig, + vdd => vdd, + vss => vss + ); + +not_aux3_ins : nao22_x1 + port map ( + i0 => no2_x1_sig, + i1 => not_i(1), + i2 => aux0, + nq => not_aux3, + vdd => vdd, + vss => vss + ); + +not_aux14_ins : na2_x1 + port map ( + i0 => b(0), + i1 => aux13, + nq => not_aux14, + vdd => vdd, + vss => vss + ); + +not_aux12_ins : inv_x2 + port map ( + i => aux12, + nq => not_aux12, + vdd => vdd, + vss => vss + ); + +not_aux11_ins : o2_x2 + port map ( + i0 => not_b(1), + i1 => not_aux10, + q => not_aux11, + vdd => vdd, + vss => vss + ); + +not_aux10_ins : a2_x2 + port map ( + i0 => not_i(2), + i1 => not_i(1), + q => not_aux10, + vdd => vdd, + vss => vss + ); + +not_i_2_ins : inv_x2 + port map ( + i => i(2), + nq => not_i(2), + vdd => vdd, + vss => vss + ); + +not_i_1_ins : inv_x2 + port map ( + i => i(1), + nq => not_i(1), + vdd => vdd, + vss => vss + ); + +not_a_2_ins : inv_x2 + port map ( + i => a(2), + nq => not_a(2), + vdd => vdd, + vss => vss + ); + +not_b_3_ins : inv_x2 + port map ( + i => b(3), + nq => not_b(3), + vdd => vdd, + vss => vss + ); + +not_b_2_ins : inv_x2 + port map ( + i => b(2), + nq => not_b(2), + vdd => vdd, + vss => vss + ); + +not_b_1_ins : inv_x2 + port map ( + i => b(1), + nq => not_b(1), + vdd => vdd, + vss => vss + ); + +not_alu_out_3_ins : inv_x2 + port map ( + i => alu_out(3), + nq => not_alu_out(3), + vdd => vdd, + vss => vss + ); + +not_alu_out_2_ins : inv_x2 + port map ( + i => alu_out(2), + nq => not_alu_out(2), + vdd => vdd, + vss => vss + ); + +not_alu_out_1_ins : inv_x2 + port map ( + i => alu_out(1), + nq => not_alu_out(1), + vdd => vdd, + vss => vss + ); + +not_alu_out_0_ins : inv_x2 + port map ( + i => alu_out(0), + nq => not_alu_out(0), + vdd => vdd, + vss => vss + ); + +aux120_ins : no2_x1 + port map ( + i0 => not_aux115, + i1 => not_b(3), + nq => aux120, + vdd => vdd, + vss => vss + ); + +aux119_ins : no2_x1 + port map ( + i0 => not_aux113, + i1 => not_b(3), + nq => aux119, + vdd => vdd, + vss => vss + ); + +aux118_ins : no2_x1 + port map ( + i0 => not_aux98, + i1 => not_b(3), + nq => aux118, + vdd => vdd, + vss => vss + ); + +aux117_ins : no2_x1 + port map ( + i0 => not_aux77, + i1 => not_b(3), + nq => aux117, + vdd => vdd, + vss => vss + ); + +aux116_ins : no2_x1 + port map ( + i0 => b(3), + i1 => not_aux115, + nq => aux116, + vdd => vdd, + vss => vss + ); + +aux114_ins : no2_x1 + port map ( + i0 => b(3), + i1 => not_aux113, + nq => aux114, + vdd => vdd, + vss => vss + ); + +aux112_ins : no2_x1 + port map ( + i0 => b(3), + i1 => not_aux77, + nq => aux112, + vdd => vdd, + vss => vss + ); + +aux111_ins : no2_x1 + port map ( + i0 => not_a(2), + i1 => not_aux106, + nq => aux111, + vdd => vdd, + vss => vss + ); + +aux110_ins : no2_x1 + port map ( + i0 => not_a(2), + i1 => not_aux104, + nq => aux110, + vdd => vdd, + vss => vss + ); + +aux109_ins : no2_x1 + port map ( + i0 => not_a(2), + i1 => not_aux102, + nq => aux109, + vdd => vdd, + vss => vss + ); + +aux108_ins : no2_x1 + port map ( + i0 => not_a(2), + i1 => not_aux100, + nq => aux108, + vdd => vdd, + vss => vss + ); + +aux107_ins : no2_x1 + port map ( + i0 => a(2), + i1 => not_aux106, + nq => aux107, + vdd => vdd, + vss => vss + ); + +aux105_ins : no2_x1 + port map ( + i0 => a(2), + i1 => not_aux104, + nq => aux105, + vdd => vdd, + vss => vss + ); + +aux103_ins : no2_x1 + port map ( + i0 => a(2), + i1 => not_aux102, + nq => aux103, + vdd => vdd, + vss => vss + ); + +aux101_ins : no2_x1 + port map ( + i0 => a(2), + i1 => not_aux100, + nq => aux101, + vdd => vdd, + vss => vss + ); + +aux99_ins : no2_x1 + port map ( + i0 => b(3), + i1 => not_aux98, + nq => aux99, + vdd => vdd, + vss => vss + ); + +aux97_ins : no2_x1 + port map ( + i0 => b(3), + i1 => not_aux65, + nq => aux97, + vdd => vdd, + vss => vss + ); + +aux96_ins : an12_x1 + port map ( + i0 => b(0), + i1 => aux92, + q => aux96, + vdd => vdd, + vss => vss + ); + +aux94_ins : na2_x1 + port map ( + i0 => not_aux52, + i1 => not_b(3), + nq => aux94, + vdd => vdd, + vss => vss + ); + +aux93_ins : a2_x2 + port map ( + i0 => b(0), + i1 => aux92, + q => aux93, + vdd => vdd, + vss => vss + ); + +aux92_ins : no2_x1 + port map ( + i0 => b(3), + i1 => not_aux48, + nq => aux92, + vdd => vdd, + vss => vss + ); + +aux91_ins : na2_x1 + port map ( + i0 => not_aux46, + i1 => not_b(3), + nq => aux91, + vdd => vdd, + vss => vss + ); + +aux90_ins : o2_x2 + port map ( + i0 => b(3), + i1 => b(0), + q => aux90, + vdd => vdd, + vss => vss + ); + +aux87_ins : an12_x1 + port map ( + i0 => b(0), + i1 => aux80, + q => aux87, + vdd => vdd, + vss => vss + ); + +aux86_ins : na3_x1 + port map ( + i0 => not_aux44, + i1 => not_aux7, + i2 => not_b(2), + nq => aux86, + vdd => vdd, + vss => vss + ); + +aux84_ins : na2_x1 + port map ( + i0 => b(3), + i1 => not_aux83, + nq => aux84, + vdd => vdd, + vss => vss + ); + +aux83_ins : na2_x1 + port map ( + i0 => not_aux57, + i1 => not_b(2), + nq => aux83, + vdd => vdd, + vss => vss + ); + +aux82_ins : na2_x1 + port map ( + i0 => not_aux54, + i1 => not_b(2), + nq => aux82, + vdd => vdd, + vss => vss + ); + +aux80_ins : no2_x1 + port map ( + i0 => not_aux76, + i1 => not_b(3), + nq => aux80, + vdd => vdd, + vss => vss + ); + +aux79_ins : na2_x1 + port map ( + i0 => b(3), + i1 => not_aux78, + nq => aux79, + vdd => vdd, + vss => vss + ); + +aux78_ins : na2_x1 + port map ( + i0 => not_aux51, + i1 => not_b(2), + nq => aux78, + vdd => vdd, + vss => vss + ); + +aux75_ins : a2_x2 + port map ( + i0 => b(3), + i1 => b(0), + q => aux75, + vdd => vdd, + vss => vss + ); + +aux74_ins : an12_x1 + port map ( + i0 => b(0), + i1 => aux66, + q => aux74, + vdd => vdd, + vss => vss + ); + +aux73_ins : na2_x1 + port map ( + i0 => b(3), + i1 => not_aux72, + nq => aux73, + vdd => vdd, + vss => vss + ); + +aux72_ins : na2_x1 + port map ( + i0 => not_aux40, + i1 => not_b(2), + nq => aux72, + vdd => vdd, + vss => vss + ); + +aux71_ins : na2_x1 + port map ( + i0 => b(3), + i1 => not_aux70, + nq => aux71, + vdd => vdd, + vss => vss + ); + +aux70_ins : na2_x1 + port map ( + i0 => not_aux31, + i1 => not_b(2), + nq => aux70, + vdd => vdd, + vss => vss + ); + +aux69_ins : na2_x1 + port map ( + i0 => b(3), + i1 => not_aux68, + nq => aux69, + vdd => vdd, + vss => vss + ); + +aux66_ins : no2_x1 + port map ( + i0 => not_aux65, + i1 => not_b(3), + nq => aux66, + vdd => vdd, + vss => vss + ); + +aux64_ins : na2_x1 + port map ( + i0 => b(3), + i1 => not_aux63, + nq => aux64, + vdd => vdd, + vss => vss + ); + +aux63_ins : na3_x1 + port map ( + i0 => not_aux4, + i1 => not_aux7, + i2 => not_b(2), + nq => aux63, + vdd => vdd, + vss => vss + ); + +aux61_ins : no2_x1 + port map ( + i0 => b(0), + i1 => not_aux49, + nq => aux61, + vdd => vdd, + vss => vss + ); + +aux60_ins : o2_x2 + port map ( + i0 => b(0), + i1 => not_b(3), + q => aux60, + vdd => vdd, + vss => vss + ); + +aux59_ins : na2_x1 + port map ( + i0 => b(3), + i1 => not_aux58, + nq => aux59, + vdd => vdd, + vss => vss + ); + +aux58_ins : na2_x1 + port map ( + i0 => b(2), + i1 => not_aux57, + nq => aux58, + vdd => vdd, + vss => vss + ); + +aux56_ins : na2_x1 + port map ( + i0 => b(3), + i1 => not_aux55, + nq => aux56, + vdd => vdd, + vss => vss + ); + +aux55_ins : na2_x1 + port map ( + i0 => b(2), + i1 => not_aux54, + nq => aux55, + vdd => vdd, + vss => vss + ); + +aux53_ins : na2_x1 + port map ( + i0 => b(3), + i1 => not_aux52, + nq => aux53, + vdd => vdd, + vss => vss + ); + +aux49_ins : no2_x1 + port map ( + i0 => not_aux48, + i1 => not_b(3), + nq => aux49, + vdd => vdd, + vss => vss + ); + +aux46_ins : na3_x1 + port map ( + i0 => not_aux44, + i1 => b(2), + i2 => not_aux7, + nq => aux46, + vdd => vdd, + vss => vss + ); + +aux43_ins : an12_x1 + port map ( + i0 => b(0), + i1 => aux13, + q => aux43, + vdd => vdd, + vss => vss + ); + +aux42_ins : na2_x1 + port map ( + i0 => b(3), + i1 => not_aux41, + nq => aux42, + vdd => vdd, + vss => vss + ); + +aux41_ins : na2_x1 + port map ( + i0 => b(2), + i1 => not_aux40, + nq => aux41, + vdd => vdd, + vss => vss + ); + +aux33_ins : na2_x1 + port map ( + i0 => b(3), + i1 => not_aux32, + nq => aux33, + vdd => vdd, + vss => vss + ); + +aux32_ins : na2_x1 + port map ( + i0 => b(2), + i1 => not_aux31, + nq => aux32, + vdd => vdd, + vss => vss + ); + +aux24_ins : na2_x1 + port map ( + i0 => b(3), + i1 => not_aux23, + nq => aux24, + vdd => vdd, + vss => vss + ); + +aux23_ins : na2_x1 + port map ( + i0 => b(2), + i1 => not_aux22, + nq => aux23, + vdd => vdd, + vss => vss + ); + +aux15_ins : na2_x1 + port map ( + i0 => i(2), + i1 => not_alu_out(2), + nq => aux15, + vdd => vdd, + vss => vss + ); + +aux13_ins : no2_x1 + port map ( + i0 => not_aux12, + i1 => not_b(3), + nq => aux13, + vdd => vdd, + vss => vss + ); + +aux12_ins : no2_x1 + port map ( + i0 => not_aux11, + i1 => not_b(2), + nq => aux12, + vdd => vdd, + vss => vss + ); + +aux9_ins : na2_x1 + port map ( + i0 => b(3), + i1 => not_aux8, + nq => aux9, + vdd => vdd, + vss => vss + ); + +aux8_ins : na3_x1 + port map ( + i0 => not_aux4, + i1 => b(2), + i2 => not_aux7, + nq => aux8, + vdd => vdd, + vss => vss + ); + +aux0_ins : na2_x1 + port map ( + i0 => i(2), + i1 => not_alu_out(1), + nq => aux0, + vdd => vdd, + vss => vss + ); + +inv_x2_ins : inv_x2 + port map ( + i => b(0), + nq => inv_x2_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_2_ins : inv_x2 + port map ( + i => not_aux14, + nq => inv_x2_2_sig, + vdd => vdd, + vss => vss + ); + +ao2o22_x2_ins : ao2o22_x2 + port map ( + i0 => inv_x2_2_sig, + i1 => ram_idx_0(0), + i2 => inv_x2_sig, + i3 => aux9, + q => ao2o22_x2_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_0_0_ins : sff1_x4 + port map ( + ck => clk, + i => ao2o22_x2_sig, + q => ram_idx_0(0), + vdd => vdd, + vss => vss + ); + +inv_x2_3_ins : inv_x2 + port map ( + i => b(0), + nq => inv_x2_3_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_4_ins : inv_x2 + port map ( + i => not_aux14, + nq => inv_x2_4_sig, + vdd => vdd, + vss => vss + ); + +ao2o22_x2_2_ins : ao2o22_x2 + port map ( + i0 => inv_x2_4_sig, + i1 => ram_idx_0(1), + i2 => inv_x2_3_sig, + i3 => aux24, + q => ao2o22_x2_2_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_0_1_ins : sff1_x4 + port map ( + ck => clk, + i => ao2o22_x2_2_sig, + q => ram_idx_0(1), + vdd => vdd, + vss => vss + ); + +inv_x2_5_ins : inv_x2 + port map ( + i => b(0), + nq => inv_x2_5_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_6_ins : inv_x2 + port map ( + i => not_aux14, + nq => inv_x2_6_sig, + vdd => vdd, + vss => vss + ); + +ao2o22_x2_3_ins : ao2o22_x2 + port map ( + i0 => inv_x2_6_sig, + i1 => ram_idx_0(2), + i2 => inv_x2_5_sig, + i3 => aux33, + q => ao2o22_x2_3_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_0_2_ins : sff1_x4 + port map ( + ck => clk, + i => ao2o22_x2_3_sig, + q => ram_idx_0(2), + vdd => vdd, + vss => vss + ); + +inv_x2_7_ins : inv_x2 + port map ( + i => b(0), + nq => inv_x2_7_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_8_ins : inv_x2 + port map ( + i => not_aux14, + nq => inv_x2_8_sig, + vdd => vdd, + vss => vss + ); + +ao2o22_x2_4_ins : ao2o22_x2 + port map ( + i0 => inv_x2_8_sig, + i1 => ram_idx_0(3), + i2 => inv_x2_7_sig, + i3 => aux42, + q => ao2o22_x2_4_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_0_3_ins : sff1_x4 + port map ( + ck => clk, + i => ao2o22_x2_4_sig, + q => ram_idx_0(3), + vdd => vdd, + vss => vss + ); + +ao2o22_x2_5_ins : ao2o22_x2 + port map ( + i0 => aux43, + i1 => ram_idx_1(0), + i2 => b(0), + i3 => aux9, + q => ao2o22_x2_5_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_1_0_ins : sff1_x4 + port map ( + ck => clk, + i => ao2o22_x2_5_sig, + q => ram_idx_1(0), + vdd => vdd, + vss => vss + ); + +ao2o22_x2_6_ins : ao2o22_x2 + port map ( + i0 => aux43, + i1 => ram_idx_1(1), + i2 => b(0), + i3 => aux24, + q => ao2o22_x2_6_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_1_1_ins : sff1_x4 + port map ( + ck => clk, + i => ao2o22_x2_6_sig, + q => ram_idx_1(1), + vdd => vdd, + vss => vss + ); + +ao2o22_x2_7_ins : ao2o22_x2 + port map ( + i0 => aux43, + i1 => ram_idx_1(2), + i2 => b(0), + i3 => aux33, + q => ao2o22_x2_7_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_1_2_ins : sff1_x4 + port map ( + ck => clk, + i => ao2o22_x2_7_sig, + q => ram_idx_1(2), + vdd => vdd, + vss => vss + ); + +ao2o22_x2_8_ins : ao2o22_x2 + port map ( + i0 => aux43, + i1 => ram_idx_1(3), + i2 => b(0), + i3 => aux42, + q => ao2o22_x2_8_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_1_3_ins : sff1_x4 + port map ( + ck => clk, + i => ao2o22_x2_8_sig, + q => ram_idx_1(3), + vdd => vdd, + vss => vss + ); + +a3_x2_4_ins : a3_x2 + port map ( + i0 => b(3), + i1 => b(0), + i2 => not_aux46, + q => a3_x2_4_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_9_ins : inv_x2 + port map ( + i => ram_idx_2(0), + nq => inv_x2_9_sig, + vdd => vdd, + vss => vss + ); + +noa22_x1_ins : noa22_x1 + port map ( + i0 => inv_x2_9_sig, + i1 => not_aux50, + i2 => a3_x2_4_sig, + nq => noa22_x1_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_2_0_ins : sff1_x4 + port map ( + ck => clk, + i => noa22_x1_sig, + q => ram_idx_2(0), + vdd => vdd, + vss => vss + ); + +inv_x2_10_ins : inv_x2 + port map ( + i => b(0), + nq => inv_x2_10_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_11_ins : inv_x2 + port map ( + i => not_aux50, + nq => inv_x2_11_sig, + vdd => vdd, + vss => vss + ); + +ao2o22_x2_9_ins : ao2o22_x2 + port map ( + i0 => inv_x2_11_sig, + i1 => ram_idx_2(1), + i2 => inv_x2_10_sig, + i3 => aux53, + q => ao2o22_x2_9_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_2_1_ins : sff1_x4 + port map ( + ck => clk, + i => ao2o22_x2_9_sig, + q => ram_idx_2(1), + vdd => vdd, + vss => vss + ); + +a2_x2_ins : a2_x2 + port map ( + i0 => not_aux49, + i1 => not_ram_idx_2(2), + q => a2_x2_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_6_ins : na2_x1 + port map ( + i0 => b(0), + i1 => aux56, + nq => na2_x1_6_sig, + vdd => vdd, + vss => vss + ); + +nao2o22_x1_ins : nao2o22_x1 + port map ( + i0 => na2_x1_6_sig, + i1 => a2_x2_sig, + i2 => b(0), + i3 => not_ram_idx_2(2), + nq => nao2o22_x1_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_2_2_ins : sff1_x4 + port map ( + ck => clk, + i => nao2o22_x1_sig, + q => ram_idx_2(2), + vdd => vdd, + vss => vss + ); + +inv_x2_12_ins : inv_x2 + port map ( + i => b(0), + nq => inv_x2_12_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_13_ins : inv_x2 + port map ( + i => not_aux50, + nq => inv_x2_13_sig, + vdd => vdd, + vss => vss + ); + +ao2o22_x2_10_ins : ao2o22_x2 + port map ( + i0 => inv_x2_13_sig, + i1 => ram_idx_2(3), + i2 => inv_x2_12_sig, + i3 => aux59, + q => ao2o22_x2_10_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_2_3_ins : sff1_x4 + port map ( + ck => clk, + i => ao2o22_x2_10_sig, + q => ram_idx_2(3), + vdd => vdd, + vss => vss + ); + +na2_x1_7_ins : na2_x1 + port map ( + i0 => not_aux48, + i1 => not_ram_idx_3(0), + nq => na2_x1_7_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_2_ins : a2_x2 + port map ( + i0 => not_aux60, + i1 => aux46, + q => a2_x2_2_sig, + vdd => vdd, + vss => vss + ); + +oa2a22_x2_ins : oa2a22_x2 + port map ( + i0 => a2_x2_2_sig, + i1 => na2_x1_7_sig, + i2 => ram_idx_3(0), + i3 => aux60, + q => oa2a22_x2_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_3_0_ins : sff1_x4 + port map ( + ck => clk, + i => oa2a22_x2_sig, + q => ram_idx_3(0), + vdd => vdd, + vss => vss + ); + +ao2o22_x2_11_ins : ao2o22_x2 + port map ( + i0 => aux61, + i1 => ram_idx_3(1), + i2 => b(0), + i3 => aux53, + q => ao2o22_x2_11_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_3_1_ins : sff1_x4 + port map ( + ck => clk, + i => ao2o22_x2_11_sig, + q => ram_idx_3(1), + vdd => vdd, + vss => vss + ); + +ao2o22_x2_12_ins : ao2o22_x2 + port map ( + i0 => aux61, + i1 => ram_idx_3(2), + i2 => b(0), + i3 => aux56, + q => ao2o22_x2_12_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_3_2_ins : sff1_x4 + port map ( + ck => clk, + i => ao2o22_x2_12_sig, + q => ram_idx_3(2), + vdd => vdd, + vss => vss + ); + +ao2o22_x2_13_ins : ao2o22_x2 + port map ( + i0 => aux61, + i1 => ram_idx_3(3), + i2 => b(0), + i3 => aux59, + q => ao2o22_x2_13_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_3_3_ins : sff1_x4 + port map ( + ck => clk, + i => ao2o22_x2_13_sig, + q => ram_idx_3(3), + vdd => vdd, + vss => vss + ); + +inv_x2_14_ins : inv_x2 + port map ( + i => b(0), + nq => inv_x2_14_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_15_ins : inv_x2 + port map ( + i => not_aux67, + nq => inv_x2_15_sig, + vdd => vdd, + vss => vss + ); + +ao2o22_x2_14_ins : ao2o22_x2 + port map ( + i0 => inv_x2_15_sig, + i1 => ram_idx_4(0), + i2 => inv_x2_14_sig, + i3 => aux64, + q => ao2o22_x2_14_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_4_0_ins : sff1_x4 + port map ( + ck => clk, + i => ao2o22_x2_14_sig, + q => ram_idx_4(0), + vdd => vdd, + vss => vss + ); + +inv_x2_16_ins : inv_x2 + port map ( + i => b(0), + nq => inv_x2_16_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_17_ins : inv_x2 + port map ( + i => not_aux67, + nq => inv_x2_17_sig, + vdd => vdd, + vss => vss + ); + +ao2o22_x2_15_ins : ao2o22_x2 + port map ( + i0 => inv_x2_17_sig, + i1 => ram_idx_4(1), + i2 => inv_x2_16_sig, + i3 => aux69, + q => ao2o22_x2_15_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_4_1_ins : sff1_x4 + port map ( + ck => clk, + i => ao2o22_x2_15_sig, + q => ram_idx_4(1), + vdd => vdd, + vss => vss + ); + +inv_x2_18_ins : inv_x2 + port map ( + i => b(0), + nq => inv_x2_18_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_19_ins : inv_x2 + port map ( + i => not_aux67, + nq => inv_x2_19_sig, + vdd => vdd, + vss => vss + ); + +ao2o22_x2_16_ins : ao2o22_x2 + port map ( + i0 => inv_x2_19_sig, + i1 => ram_idx_4(2), + i2 => inv_x2_18_sig, + i3 => aux71, + q => ao2o22_x2_16_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_4_2_ins : sff1_x4 + port map ( + ck => clk, + i => ao2o22_x2_16_sig, + q => ram_idx_4(2), + vdd => vdd, + vss => vss + ); + +inv_x2_20_ins : inv_x2 + port map ( + i => b(0), + nq => inv_x2_20_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_21_ins : inv_x2 + port map ( + i => not_aux67, + nq => inv_x2_21_sig, + vdd => vdd, + vss => vss + ); + +ao2o22_x2_17_ins : ao2o22_x2 + port map ( + i0 => inv_x2_21_sig, + i1 => ram_idx_4(3), + i2 => inv_x2_20_sig, + i3 => aux73, + q => ao2o22_x2_17_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_4_3_ins : sff1_x4 + port map ( + ck => clk, + i => ao2o22_x2_17_sig, + q => ram_idx_4(3), + vdd => vdd, + vss => vss + ); + +ao2o22_x2_18_ins : ao2o22_x2 + port map ( + i0 => aux74, + i1 => ram_idx_5(0), + i2 => b(0), + i3 => aux64, + q => ao2o22_x2_18_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_5_0_ins : sff1_x4 + port map ( + ck => clk, + i => ao2o22_x2_18_sig, + q => ram_idx_5(0), + vdd => vdd, + vss => vss + ); + +ao2o22_x2_19_ins : ao2o22_x2 + port map ( + i0 => aux74, + i1 => ram_idx_5(1), + i2 => b(0), + i3 => aux69, + q => ao2o22_x2_19_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_5_1_ins : sff1_x4 + port map ( + ck => clk, + i => ao2o22_x2_19_sig, + q => ram_idx_5(1), + vdd => vdd, + vss => vss + ); + +ao2o22_x2_20_ins : ao2o22_x2 + port map ( + i0 => aux74, + i1 => ram_idx_5(2), + i2 => b(0), + i3 => aux71, + q => ao2o22_x2_20_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_5_2_ins : sff1_x4 + port map ( + ck => clk, + i => ao2o22_x2_20_sig, + q => ram_idx_5(2), + vdd => vdd, + vss => vss + ); + +ao2o22_x2_21_ins : ao2o22_x2 + port map ( + i0 => aux74, + i1 => ram_idx_5(3), + i2 => b(0), + i3 => aux73, + q => ao2o22_x2_21_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_5_3_ins : sff1_x4 + port map ( + ck => clk, + i => ao2o22_x2_21_sig, + q => ram_idx_5(3), + vdd => vdd, + vss => vss + ); + +oa22_x2_2_ins : oa22_x2 + port map ( + i0 => i(2), + i1 => alu_out(1), + i2 => i(1), + q => oa22_x2_2_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_2_ins : no2_x1 + port map ( + i0 => b(1), + i1 => b(2), + nq => no2_x1_2_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_8_ins : na2_x1 + port map ( + i0 => not_i(2), + i1 => not_alu_out(0), + nq => na2_x1_8_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_5_ins : a3_x2 + port map ( + i0 => na2_x1_8_sig, + i1 => no2_x1_2_sig, + i2 => oa22_x2_2_sig, + q => a3_x2_5_sig, + vdd => vdd, + vss => vss + ); + +oa22_x2_ins : oa22_x2 + port map ( + i0 => ram_idx_6(0), + i1 => not_aux76, + i2 => a3_x2_5_sig, + q => oa22_x2_sig, + vdd => vdd, + vss => vss + ); + +o2_x2_ins : o2_x2 + port map ( + i0 => r0_from_pads, + i1 => not_aux6, + q => o2_x2_sig, + vdd => vdd, + vss => vss + ); + +oa22_x2_3_ins : oa22_x2 + port map ( + i0 => ram_idx_6(0), + i1 => not_aux77, + i2 => o2_x2_sig, + q => oa22_x2_3_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_ins : na3_x1 + port map ( + i0 => aux75, + i1 => oa22_x2_3_sig, + i2 => oa22_x2_sig, + nq => na3_x1_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_22_ins : inv_x2 + port map ( + i => ram_idx_6(0), + nq => inv_x2_22_sig, + vdd => vdd, + vss => vss + ); + +nao22_x1_ins : nao22_x1 + port map ( + i0 => inv_x2_22_sig, + i1 => aux75, + i2 => na3_x1_sig, + nq => nao22_x1_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_6_0_ins : sff1_x4 + port map ( + ck => clk, + i => nao22_x1_sig, + q => ram_idx_6(0), + vdd => vdd, + vss => vss + ); + +inv_x2_23_ins : inv_x2 + port map ( + i => b(0), + nq => inv_x2_23_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_24_ins : inv_x2 + port map ( + i => not_aux81, + nq => inv_x2_24_sig, + vdd => vdd, + vss => vss + ); + +ao2o22_x2_22_ins : ao2o22_x2 + port map ( + i0 => inv_x2_24_sig, + i1 => ram_idx_6(1), + i2 => inv_x2_23_sig, + i3 => aux79, + q => ao2o22_x2_22_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_6_1_ins : sff1_x4 + port map ( + ck => clk, + i => ao2o22_x2_22_sig, + q => ram_idx_6(1), + vdd => vdd, + vss => vss + ); + +a3_x2_6_ins : a3_x2 + port map ( + i0 => b(3), + i1 => b(0), + i2 => not_aux82, + q => a3_x2_6_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_25_ins : inv_x2 + port map ( + i => ram_idx_6(2), + nq => inv_x2_25_sig, + vdd => vdd, + vss => vss + ); + +noa22_x1_2_ins : noa22_x1 + port map ( + i0 => inv_x2_25_sig, + i1 => not_aux81, + i2 => a3_x2_6_sig, + nq => noa22_x1_2_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_6_2_ins : sff1_x4 + port map ( + ck => clk, + i => noa22_x1_2_sig, + q => ram_idx_6(2), + vdd => vdd, + vss => vss + ); + +inv_x2_26_ins : inv_x2 + port map ( + i => b(0), + nq => inv_x2_26_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_27_ins : inv_x2 + port map ( + i => not_aux81, + nq => inv_x2_27_sig, + vdd => vdd, + vss => vss + ); + +ao2o22_x2_23_ins : ao2o22_x2 + port map ( + i0 => inv_x2_27_sig, + i1 => ram_idx_6(3), + i2 => inv_x2_26_sig, + i3 => aux84, + q => ao2o22_x2_23_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_6_3_ins : sff1_x4 + port map ( + ck => clk, + i => ao2o22_x2_23_sig, + q => ram_idx_6(3), + vdd => vdd, + vss => vss + ); + +o3_x2_ins : o3_x2 + port map ( + i0 => not_b(3), + i1 => b(0), + i2 => aux86, + q => o3_x2_sig, + vdd => vdd, + vss => vss + ); + +ao22_x2_ins : ao22_x2 + port map ( + i0 => ram_idx_7(0), + i1 => aux87, + i2 => o3_x2_sig, + q => ao22_x2_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_7_0_ins : sff1_x4 + port map ( + ck => clk, + i => ao22_x2_sig, + q => ram_idx_7(0), + vdd => vdd, + vss => vss + ); + +ao2o22_x2_24_ins : ao2o22_x2 + port map ( + i0 => aux87, + i1 => ram_idx_7(1), + i2 => b(0), + i3 => aux79, + q => ao2o22_x2_24_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_7_1_ins : sff1_x4 + port map ( + ck => clk, + i => ao2o22_x2_24_sig, + q => ram_idx_7(1), + vdd => vdd, + vss => vss + ); + +na2_x1_9_ins : na2_x1 + port map ( + i0 => not_aux76, + i1 => not_ram_idx_7(2), + nq => na2_x1_9_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_3_ins : a2_x2 + port map ( + i0 => not_aux60, + i1 => aux82, + q => a2_x2_3_sig, + vdd => vdd, + vss => vss + ); + +oa2a22_x2_2_ins : oa2a22_x2 + port map ( + i0 => a2_x2_3_sig, + i1 => na2_x1_9_sig, + i2 => ram_idx_7(2), + i3 => aux60, + q => oa2a22_x2_2_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_7_2_ins : sff1_x4 + port map ( + ck => clk, + i => oa2a22_x2_2_sig, + q => ram_idx_7(2), + vdd => vdd, + vss => vss + ); + +ao2o22_x2_25_ins : ao2o22_x2 + port map ( + i0 => aux87, + i1 => ram_idx_7(3), + i2 => b(0), + i3 => aux84, + q => ao2o22_x2_25_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_7_3_ins : sff1_x4 + port map ( + ck => clk, + i => ao2o22_x2_25_sig, + q => ram_idx_7(3), + vdd => vdd, + vss => vss + ); + +a3_x2_7_ins : a3_x2 + port map ( + i0 => not_aux8, + i1 => b(0), + i2 => not_b(3), + q => a3_x2_7_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_28_ins : inv_x2 + port map ( + i => ram_idx_8(0), + nq => inv_x2_28_sig, + vdd => vdd, + vss => vss + ); + +noa22_x1_3_ins : noa22_x1 + port map ( + i0 => inv_x2_28_sig, + i1 => not_aux89, + i2 => a3_x2_7_sig, + nq => noa22_x1_3_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_8_0_ins : sff1_x4 + port map ( + ck => clk, + i => noa22_x1_3_sig, + q => ram_idx_8(0), + vdd => vdd, + vss => vss + ); + +a3_x2_8_ins : a3_x2 + port map ( + i0 => not_aux23, + i1 => b(0), + i2 => not_b(3), + q => a3_x2_8_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_29_ins : inv_x2 + port map ( + i => ram_idx_8(1), + nq => inv_x2_29_sig, + vdd => vdd, + vss => vss + ); + +noa22_x1_4_ins : noa22_x1 + port map ( + i0 => inv_x2_29_sig, + i1 => not_aux89, + i2 => a3_x2_8_sig, + nq => noa22_x1_4_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_8_1_ins : sff1_x4 + port map ( + ck => clk, + i => noa22_x1_4_sig, + q => ram_idx_8(1), + vdd => vdd, + vss => vss + ); + +a3_x2_9_ins : a3_x2 + port map ( + i0 => not_aux32, + i1 => b(0), + i2 => not_b(3), + q => a3_x2_9_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_30_ins : inv_x2 + port map ( + i => ram_idx_8(2), + nq => inv_x2_30_sig, + vdd => vdd, + vss => vss + ); + +noa22_x1_5_ins : noa22_x1 + port map ( + i0 => inv_x2_30_sig, + i1 => not_aux89, + i2 => a3_x2_9_sig, + nq => noa22_x1_5_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_8_2_ins : sff1_x4 + port map ( + ck => clk, + i => noa22_x1_5_sig, + q => ram_idx_8(2), + vdd => vdd, + vss => vss + ); + +a3_x2_10_ins : a3_x2 + port map ( + i0 => not_aux41, + i1 => b(0), + i2 => not_b(3), + q => a3_x2_10_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_31_ins : inv_x2 + port map ( + i => ram_idx_8(3), + nq => inv_x2_31_sig, + vdd => vdd, + vss => vss + ); + +noa22_x1_6_ins : noa22_x1 + port map ( + i0 => inv_x2_31_sig, + i1 => not_aux89, + i2 => a3_x2_10_sig, + nq => noa22_x1_6_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_8_3_ins : sff1_x4 + port map ( + ck => clk, + i => noa22_x1_6_sig, + q => ram_idx_8(3), + vdd => vdd, + vss => vss + ); + +na2_x1_10_ins : na2_x1 + port map ( + i0 => not_aux12, + i1 => not_ram_idx_9(0), + nq => na2_x1_10_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_4_ins : a2_x2 + port map ( + i0 => not_aux90, + i1 => aux8, + q => a2_x2_4_sig, + vdd => vdd, + vss => vss + ); + +oa2a22_x2_3_ins : oa2a22_x2 + port map ( + i0 => a2_x2_4_sig, + i1 => na2_x1_10_sig, + i2 => ram_idx_9(0), + i3 => aux90, + q => oa2a22_x2_3_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_9_0_ins : sff1_x4 + port map ( + ck => clk, + i => oa2a22_x2_3_sig, + q => ram_idx_9(0), + vdd => vdd, + vss => vss + ); + +na2_x1_11_ins : na2_x1 + port map ( + i0 => not_aux12, + i1 => not_ram_idx_9(1), + nq => na2_x1_11_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_5_ins : a2_x2 + port map ( + i0 => not_aux90, + i1 => aux23, + q => a2_x2_5_sig, + vdd => vdd, + vss => vss + ); + +oa2a22_x2_4_ins : oa2a22_x2 + port map ( + i0 => a2_x2_5_sig, + i1 => na2_x1_11_sig, + i2 => ram_idx_9(1), + i3 => aux90, + q => oa2a22_x2_4_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_9_1_ins : sff1_x4 + port map ( + ck => clk, + i => oa2a22_x2_4_sig, + q => ram_idx_9(1), + vdd => vdd, + vss => vss + ); + +na2_x1_12_ins : na2_x1 + port map ( + i0 => not_aux12, + i1 => not_ram_idx_9(2), + nq => na2_x1_12_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_6_ins : a2_x2 + port map ( + i0 => not_aux90, + i1 => aux32, + q => a2_x2_6_sig, + vdd => vdd, + vss => vss + ); + +oa2a22_x2_5_ins : oa2a22_x2 + port map ( + i0 => a2_x2_6_sig, + i1 => na2_x1_12_sig, + i2 => ram_idx_9(2), + i3 => aux90, + q => oa2a22_x2_5_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_9_2_ins : sff1_x4 + port map ( + ck => clk, + i => oa2a22_x2_5_sig, + q => ram_idx_9(2), + vdd => vdd, + vss => vss + ); + +na2_x1_13_ins : na2_x1 + port map ( + i0 => not_aux12, + i1 => not_ram_idx_9(3), + nq => na2_x1_13_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_7_ins : a2_x2 + port map ( + i0 => not_aux90, + i1 => aux41, + q => a2_x2_7_sig, + vdd => vdd, + vss => vss + ); + +oa2a22_x2_6_ins : oa2a22_x2 + port map ( + i0 => a2_x2_7_sig, + i1 => na2_x1_13_sig, + i2 => ram_idx_9(3), + i3 => aux90, + q => oa2a22_x2_6_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_9_3_ins : sff1_x4 + port map ( + ck => clk, + i => oa2a22_x2_6_sig, + q => ram_idx_9(3), + vdd => vdd, + vss => vss + ); + +inv_x2_32_ins : inv_x2 + port map ( + i => b(0), + nq => inv_x2_32_sig, + vdd => vdd, + vss => vss + ); + +ao2o22_x2_26_ins : ao2o22_x2 + port map ( + i0 => aux91, + i1 => inv_x2_32_sig, + i2 => ram_idx_10(0), + i3 => aux93, + q => ao2o22_x2_26_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_10_0_ins : sff1_x4 + port map ( + ck => clk, + i => ao2o22_x2_26_sig, + q => ram_idx_10(0), + vdd => vdd, + vss => vss + ); + +inv_x2_33_ins : inv_x2 + port map ( + i => b(0), + nq => inv_x2_33_sig, + vdd => vdd, + vss => vss + ); + +ao2o22_x2_27_ins : ao2o22_x2 + port map ( + i0 => aux94, + i1 => inv_x2_33_sig, + i2 => ram_idx_10(1), + i3 => aux93, + q => ao2o22_x2_27_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_10_1_ins : sff1_x4 + port map ( + ck => clk, + i => ao2o22_x2_27_sig, + q => ram_idx_10(1), + vdd => vdd, + vss => vss + ); + +no2_x1_3_ins : no2_x1 + port map ( + i0 => not_aux55, + i1 => not_aux95, + nq => no2_x1_3_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_34_ins : inv_x2 + port map ( + i => not_aux48, + nq => inv_x2_34_sig, + vdd => vdd, + vss => vss + ); + +oa2ao222_x2_ins : oa2ao222_x2 + port map ( + i0 => ram_idx_10(2), + i1 => not_aux95, + i2 => ram_idx_10(2), + i3 => inv_x2_34_sig, + i4 => no2_x1_3_sig, + q => oa2ao222_x2_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_10_2_ins : sff1_x4 + port map ( + ck => clk, + i => oa2ao222_x2_sig, + q => ram_idx_10(2), + vdd => vdd, + vss => vss + ); + +no2_x1_4_ins : no2_x1 + port map ( + i0 => not_aux58, + i1 => not_aux95, + nq => no2_x1_4_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_35_ins : inv_x2 + port map ( + i => not_aux48, + nq => inv_x2_35_sig, + vdd => vdd, + vss => vss + ); + +oa2ao222_x2_2_ins : oa2ao222_x2 + port map ( + i0 => ram_idx_10(3), + i1 => not_aux95, + i2 => ram_idx_10(3), + i3 => inv_x2_35_sig, + i4 => no2_x1_4_sig, + q => oa2ao222_x2_2_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_10_3_ins : sff1_x4 + port map ( + ck => clk, + i => oa2ao222_x2_2_sig, + q => ram_idx_10(3), + vdd => vdd, + vss => vss + ); + +ao2o22_x2_28_ins : ao2o22_x2 + port map ( + i0 => aux96, + i1 => ram_idx_11(0), + i2 => b(0), + i3 => aux91, + q => ao2o22_x2_28_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_11_0_ins : sff1_x4 + port map ( + ck => clk, + i => ao2o22_x2_28_sig, + q => ram_idx_11(0), + vdd => vdd, + vss => vss + ); + +ao2o22_x2_29_ins : ao2o22_x2 + port map ( + i0 => aux96, + i1 => ram_idx_11(1), + i2 => b(0), + i3 => aux94, + q => ao2o22_x2_29_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_11_1_ins : sff1_x4 + port map ( + ck => clk, + i => ao2o22_x2_29_sig, + q => ram_idx_11(1), + vdd => vdd, + vss => vss + ); + +na2_x1_14_ins : na2_x1 + port map ( + i0 => not_aux48, + i1 => not_ram_idx_11(2), + nq => na2_x1_14_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_8_ins : a2_x2 + port map ( + i0 => not_aux90, + i1 => aux55, + q => a2_x2_8_sig, + vdd => vdd, + vss => vss + ); + +oa2a22_x2_7_ins : oa2a22_x2 + port map ( + i0 => a2_x2_8_sig, + i1 => na2_x1_14_sig, + i2 => ram_idx_11(2), + i3 => aux90, + q => oa2a22_x2_7_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_11_2_ins : sff1_x4 + port map ( + ck => clk, + i => oa2a22_x2_7_sig, + q => ram_idx_11(2), + vdd => vdd, + vss => vss + ); + +o3_x2_2_ins : o3_x2 + port map ( + i0 => b(3), + i1 => b(0), + i2 => aux58, + q => o3_x2_2_sig, + vdd => vdd, + vss => vss + ); + +ao22_x2_2_ins : ao22_x2 + port map ( + i0 => ram_idx_11(3), + i1 => aux96, + i2 => o3_x2_2_sig, + q => ao22_x2_2_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_11_3_ins : sff1_x4 + port map ( + ck => clk, + i => ao22_x2_2_sig, + q => ram_idx_11(3), + vdd => vdd, + vss => vss + ); + +na3_x1_2_ins : na3_x1 + port map ( + i0 => not_aux63, + i1 => b(0), + i2 => not_b(3), + nq => na3_x1_2_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_9_ins : a2_x2 + port map ( + i0 => b(0), + i1 => aux97, + q => a2_x2_9_sig, + vdd => vdd, + vss => vss + ); + +ao22_x2_3_ins : ao22_x2 + port map ( + i0 => a2_x2_9_sig, + i1 => ram_idx_12(0), + i2 => na3_x1_2_sig, + q => ao22_x2_3_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_12_0_ins : sff1_x4 + port map ( + ck => clk, + i => ao22_x2_3_sig, + q => ram_idx_12(0), + vdd => vdd, + vss => vss + ); + +an12_x1_ins : an12_x1 + port map ( + i0 => aux97, + i1 => not_ram_idx_12(1), + q => an12_x1_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_36_ins : inv_x2 + port map ( + i => b(0), + nq => inv_x2_36_sig, + vdd => vdd, + vss => vss + ); + +oa22_x2_4_ins : oa22_x2 + port map ( + i0 => not_b(3), + i1 => not_aux68, + i2 => inv_x2_36_sig, + q => oa22_x2_4_sig, + vdd => vdd, + vss => vss + ); + +nao2o22_x1_2_ins : nao2o22_x1 + port map ( + i0 => oa22_x2_4_sig, + i1 => an12_x1_sig, + i2 => b(0), + i3 => not_ram_idx_12(1), + nq => nao2o22_x1_2_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_12_1_ins : sff1_x4 + port map ( + ck => clk, + i => nao2o22_x1_2_sig, + q => ram_idx_12(1), + vdd => vdd, + vss => vss + ); + +no2_x1_5_ins : no2_x1 + port map ( + i0 => not_aux70, + i1 => not_aux95, + nq => no2_x1_5_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_37_ins : inv_x2 + port map ( + i => not_aux65, + nq => inv_x2_37_sig, + vdd => vdd, + vss => vss + ); + +oa2ao222_x2_3_ins : oa2ao222_x2 + port map ( + i0 => ram_idx_12(2), + i1 => not_aux95, + i2 => ram_idx_12(2), + i3 => inv_x2_37_sig, + i4 => no2_x1_5_sig, + q => oa2ao222_x2_3_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_12_2_ins : sff1_x4 + port map ( + ck => clk, + i => oa2ao222_x2_3_sig, + q => ram_idx_12(2), + vdd => vdd, + vss => vss + ); + +no2_x1_6_ins : no2_x1 + port map ( + i0 => not_aux72, + i1 => not_aux95, + nq => no2_x1_6_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_38_ins : inv_x2 + port map ( + i => not_aux65, + nq => inv_x2_38_sig, + vdd => vdd, + vss => vss + ); + +oa2ao222_x2_4_ins : oa2ao222_x2 + port map ( + i0 => ram_idx_12(3), + i1 => not_aux95, + i2 => ram_idx_12(3), + i3 => inv_x2_38_sig, + i4 => no2_x1_6_sig, + q => oa2ao222_x2_4_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_12_3_ins : sff1_x4 + port map ( + ck => clk, + i => oa2ao222_x2_4_sig, + q => ram_idx_12(3), + vdd => vdd, + vss => vss + ); + +na2_x1_15_ins : na2_x1 + port map ( + i0 => not_aux65, + i1 => not_ram_idx_13(0), + nq => na2_x1_15_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_10_ins : a2_x2 + port map ( + i0 => not_aux90, + i1 => aux63, + q => a2_x2_10_sig, + vdd => vdd, + vss => vss + ); + +oa2a22_x2_8_ins : oa2a22_x2 + port map ( + i0 => a2_x2_10_sig, + i1 => na2_x1_15_sig, + i2 => ram_idx_13(0), + i3 => aux90, + q => oa2a22_x2_8_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_13_0_ins : sff1_x4 + port map ( + ck => clk, + i => oa2a22_x2_8_sig, + q => ram_idx_13(0), + vdd => vdd, + vss => vss + ); + +no3_x1_ins : no3_x1 + port map ( + i0 => not_aux99, + i1 => not_aux21, + i2 => b(0), + nq => no3_x1_sig, + vdd => vdd, + vss => vss + ); + +na2_x1_16_ins : na2_x1 + port map ( + i0 => not_aux10, + i1 => not_ram_idx_13(1), + nq => na2_x1_16_sig, + vdd => vdd, + vss => vss + ); + +oa2ao222_x2_5_ins : oa2ao222_x2 + port map ( + i0 => na2_x1_16_sig, + i1 => no3_x1_sig, + i2 => b(0), + i3 => not_aux99, + i4 => ram_idx_13(1), + q => oa2ao222_x2_5_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_13_1_ins : sff1_x4 + port map ( + ck => clk, + i => oa2ao222_x2_5_sig, + q => ram_idx_13(1), + vdd => vdd, + vss => vss + ); + +na2_x1_17_ins : na2_x1 + port map ( + i0 => not_aux65, + i1 => not_ram_idx_13(2), + nq => na2_x1_17_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_11_ins : a2_x2 + port map ( + i0 => not_aux90, + i1 => aux70, + q => a2_x2_11_sig, + vdd => vdd, + vss => vss + ); + +oa2a22_x2_9_ins : oa2a22_x2 + port map ( + i0 => a2_x2_11_sig, + i1 => na2_x1_17_sig, + i2 => ram_idx_13(2), + i3 => aux90, + q => oa2a22_x2_9_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_13_2_ins : sff1_x4 + port map ( + ck => clk, + i => oa2a22_x2_9_sig, + q => ram_idx_13(2), + vdd => vdd, + vss => vss + ); + +na2_x1_18_ins : na2_x1 + port map ( + i0 => not_aux65, + i1 => not_ram_idx_13(3), + nq => na2_x1_18_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_12_ins : a2_x2 + port map ( + i0 => not_aux90, + i1 => aux72, + q => a2_x2_12_sig, + vdd => vdd, + vss => vss + ); + +oa2a22_x2_10_ins : oa2a22_x2 + port map ( + i0 => a2_x2_12_sig, + i1 => na2_x1_18_sig, + i2 => ram_idx_13(3), + i3 => aux90, + q => oa2a22_x2_10_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_13_3_ins : sff1_x4 + port map ( + ck => clk, + i => oa2a22_x2_10_sig, + q => ram_idx_13(3), + vdd => vdd, + vss => vss + ); + +an12_x1_2_ins : an12_x1 + port map ( + i0 => not_aux95, + i1 => aux86, + q => an12_x1_2_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_39_ins : inv_x2 + port map ( + i => not_aux76, + nq => inv_x2_39_sig, + vdd => vdd, + vss => vss + ); + +oa2ao222_x2_6_ins : oa2ao222_x2 + port map ( + i0 => ram_idx_14(0), + i1 => not_aux95, + i2 => inv_x2_39_sig, + i3 => ram_idx_14(0), + i4 => an12_x1_2_sig, + q => oa2ao222_x2_6_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_14_0_ins : sff1_x4 + port map ( + ck => clk, + i => oa2ao222_x2_6_sig, + q => ram_idx_14(0), + vdd => vdd, + vss => vss + ); + +no2_x1_7_ins : no2_x1 + port map ( + i0 => not_aux78, + i1 => not_aux95, + nq => no2_x1_7_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_40_ins : inv_x2 + port map ( + i => not_aux76, + nq => inv_x2_40_sig, + vdd => vdd, + vss => vss + ); + +oa2ao222_x2_7_ins : oa2ao222_x2 + port map ( + i0 => ram_idx_14(1), + i1 => not_aux95, + i2 => ram_idx_14(1), + i3 => inv_x2_40_sig, + i4 => no2_x1_7_sig, + q => oa2ao222_x2_7_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_14_1_ins : sff1_x4 + port map ( + ck => clk, + i => oa2ao222_x2_7_sig, + q => ram_idx_14(1), + vdd => vdd, + vss => vss + ); + +no2_x1_8_ins : no2_x1 + port map ( + i0 => not_aux82, + i1 => not_aux95, + nq => no2_x1_8_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_41_ins : inv_x2 + port map ( + i => not_aux76, + nq => inv_x2_41_sig, + vdd => vdd, + vss => vss + ); + +oa2ao222_x2_8_ins : oa2ao222_x2 + port map ( + i0 => ram_idx_14(2), + i1 => not_aux95, + i2 => ram_idx_14(2), + i3 => inv_x2_41_sig, + i4 => no2_x1_8_sig, + q => oa2ao222_x2_8_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_14_2_ins : sff1_x4 + port map ( + ck => clk, + i => oa2ao222_x2_8_sig, + q => ram_idx_14(2), + vdd => vdd, + vss => vss + ); + +no2_x1_9_ins : no2_x1 + port map ( + i0 => not_aux83, + i1 => not_aux95, + nq => no2_x1_9_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_42_ins : inv_x2 + port map ( + i => not_aux76, + nq => inv_x2_42_sig, + vdd => vdd, + vss => vss + ); + +oa2ao222_x2_9_ins : oa2ao222_x2 + port map ( + i0 => ram_idx_14(3), + i1 => not_aux95, + i2 => ram_idx_14(3), + i3 => inv_x2_42_sig, + i4 => no2_x1_9_sig, + q => oa2ao222_x2_9_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_14_3_ins : sff1_x4 + port map ( + ck => clk, + i => oa2ao222_x2_9_sig, + q => ram_idx_14(3), + vdd => vdd, + vss => vss + ); + +na2_x1_19_ins : na2_x1 + port map ( + i0 => not_aux76, + i1 => not_ram_idx_15(0), + nq => na2_x1_19_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_13_ins : a2_x2 + port map ( + i0 => not_aux90, + i1 => aux86, + q => a2_x2_13_sig, + vdd => vdd, + vss => vss + ); + +oa2a22_x2_11_ins : oa2a22_x2 + port map ( + i0 => a2_x2_13_sig, + i1 => na2_x1_19_sig, + i2 => ram_idx_15(0), + i3 => aux90, + q => oa2a22_x2_11_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_15_0_ins : sff1_x4 + port map ( + ck => clk, + i => oa2a22_x2_11_sig, + q => ram_idx_15(0), + vdd => vdd, + vss => vss + ); + +inv_x2_43_ins : inv_x2 + port map ( + i => ram_idx_15(1), + nq => inv_x2_43_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_44_ins : inv_x2 + port map ( + i => b(0), + nq => inv_x2_44_sig, + vdd => vdd, + vss => vss + ); + +noa3ao322_x1_ins : noa3ao322_x1 + port map ( + i0 => inv_x2_44_sig, + i1 => not_aux78, + i2 => not_b(3), + i3 => not_aux76, + i4 => b(3), + i5 => b(0), + i6 => inv_x2_43_sig, + nq => noa3ao322_x1_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_15_1_ins : sff1_x4 + port map ( + ck => clk, + i => noa3ao322_x1_sig, + q => ram_idx_15(1), + vdd => vdd, + vss => vss + ); + +na2_x1_20_ins : na2_x1 + port map ( + i0 => not_aux76, + i1 => not_ram_idx_15(2), + nq => na2_x1_20_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_14_ins : a2_x2 + port map ( + i0 => not_aux90, + i1 => aux82, + q => a2_x2_14_sig, + vdd => vdd, + vss => vss + ); + +oa2a22_x2_12_ins : oa2a22_x2 + port map ( + i0 => a2_x2_14_sig, + i1 => na2_x1_20_sig, + i2 => ram_idx_15(2), + i3 => aux90, + q => oa2a22_x2_12_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_15_2_ins : sff1_x4 + port map ( + ck => clk, + i => oa2a22_x2_12_sig, + q => ram_idx_15(2), + vdd => vdd, + vss => vss + ); + +na2_x1_21_ins : na2_x1 + port map ( + i0 => not_aux76, + i1 => not_ram_idx_15(3), + nq => na2_x1_21_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_15_ins : a2_x2 + port map ( + i0 => not_aux90, + i1 => aux83, + q => a2_x2_15_sig, + vdd => vdd, + vss => vss + ); + +oa2a22_x2_13_ins : oa2a22_x2 + port map ( + i0 => a2_x2_15_sig, + i1 => na2_x1_21_sig, + i2 => ram_idx_15(3), + i3 => aux90, + q => oa2a22_x2_13_sig, + vdd => vdd, + vss => vss + ); + +ram_idx_15_3_ins : sff1_x4 + port map ( + ck => clk, + i => oa2a22_x2_13_sig, + q => ram_idx_15(3), + vdd => vdd, + vss => vss + ); + +r3_to_pads_ins : buf_x2 + port map ( + i => alu_out(3), + q => r3_to_pads, + vdd => vdd, + vss => vss + ); + +r0_to_pads_ins : buf_x2 + port map ( + i => alu_out(0), + q => r0_to_pads, + vdd => vdd, + vss => vss + ); + +o3_x2_3_ins : o3_x2 + port map ( + i0 => not_aux112, + i1 => b(0), + i2 => not_ram_idx_15(0), + q => o3_x2_3_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_3_ins : na3_x1 + port map ( + i0 => ram_idx_12(0), + i1 => b(0), + i2 => aux99, + nq => na3_x1_3_sig, + vdd => vdd, + vss => vss + ); + +o3_x2_4_ins : o3_x2 + port map ( + i0 => not_aux99, + i1 => b(0), + i2 => not_ram_idx_13(0), + q => o3_x2_4_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_11_ins : a3_x2 + port map ( + i0 => o3_x2_4_sig, + i1 => na3_x1_3_sig, + i2 => o3_x2_3_sig, + q => a3_x2_11_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_45_ins : inv_x2 + port map ( + i => ram_idx_11(0), + nq => inv_x2_45_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_3_ins : no3_x1 + port map ( + i0 => inv_x2_45_sig, + i1 => b(0), + i2 => not_aux114, + nq => no3_x1_3_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_46_ins : inv_x2 + port map ( + i => ram_idx_5(0), + nq => inv_x2_46_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_4_ins : no3_x1 + port map ( + i0 => inv_x2_46_sig, + i1 => b(0), + i2 => not_aux118, + nq => no3_x1_4_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_47_ins : inv_x2 + port map ( + i => ram_idx_7(0), + nq => inv_x2_47_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_5_ins : no3_x1 + port map ( + i0 => inv_x2_47_sig, + i1 => b(0), + i2 => not_aux117, + nq => no3_x1_5_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_2_ins : no3_x1 + port map ( + i0 => no3_x1_5_sig, + i1 => no3_x1_4_sig, + i2 => no3_x1_3_sig, + nq => no3_x1_2_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_4_ins : na3_x1 + port map ( + i0 => ram_idx_4(0), + i1 => b(0), + i2 => aux118, + nq => na3_x1_4_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_5_ins : na3_x1 + port map ( + i0 => ram_idx_0(0), + i1 => b(0), + i2 => aux120, + nq => na3_x1_5_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_6_ins : na3_x1 + port map ( + i0 => ram_idx_2(0), + i1 => b(0), + i2 => aux119, + nq => na3_x1_6_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_12_ins : a3_x2 + port map ( + i0 => na3_x1_6_sig, + i1 => na3_x1_5_sig, + i2 => na3_x1_4_sig, + q => a3_x2_12_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_7_ins : no3_x1 + port map ( + i0 => not_ram_idx_9(0), + i1 => b(0), + i2 => not_aux116, + nq => no3_x1_7_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_13_ins : a3_x2 + port map ( + i0 => ram_idx_6(0), + i1 => b(0), + i2 => aux117, + q => a3_x2_13_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_8_ins : no3_x1 + port map ( + i0 => not_ram_idx_3(0), + i1 => b(0), + i2 => not_aux119, + nq => no3_x1_8_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_6_ins : no3_x1 + port map ( + i0 => no3_x1_8_sig, + i1 => a3_x2_13_sig, + i2 => no3_x1_7_sig, + nq => no3_x1_6_sig, + vdd => vdd, + vss => vss + ); + +na4_x1_ins : na4_x1 + port map ( + i0 => no3_x1_6_sig, + i1 => a3_x2_12_sig, + i2 => no3_x1_2_sig, + i3 => a3_x2_11_sig, + nq => na4_x1_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_48_ins : inv_x2 + port map ( + i => ram_idx_1(0), + nq => inv_x2_48_sig, + vdd => vdd, + vss => vss + ); + +o3_x2_5_ins : o3_x2 + port map ( + i0 => not_aux120, + i1 => b(0), + i2 => inv_x2_48_sig, + q => o3_x2_5_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_7_ins : na3_x1 + port map ( + i0 => ram_idx_14(0), + i1 => b(0), + i2 => aux112, + nq => na3_x1_7_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_8_ins : na3_x1 + port map ( + i0 => ram_idx_8(0), + i1 => b(0), + i2 => aux116, + nq => na3_x1_8_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_9_ins : na3_x1 + port map ( + i0 => ram_idx_10(0), + i1 => b(0), + i2 => aux114, + nq => na3_x1_9_sig, + vdd => vdd, + vss => vss + ); + +na4_x1_2_ins : na4_x1 + port map ( + i0 => na3_x1_9_sig, + i1 => na3_x1_8_sig, + i2 => na3_x1_7_sig, + i3 => o3_x2_5_sig, + nq => na4_x1_2_sig, + vdd => vdd, + vss => vss + ); + +rb_0_ins : o2_x2 + port map ( + i0 => na4_x1_2_sig, + i1 => na4_x1_sig, + q => rb(0), + vdd => vdd, + vss => vss + ); + +o3_x2_6_ins : o3_x2 + port map ( + i0 => not_aux116, + i1 => b(0), + i2 => not_ram_idx_9(1), + q => o3_x2_6_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_10_ins : na3_x1 + port map ( + i0 => ram_idx_12(1), + i1 => b(0), + i2 => aux99, + nq => na3_x1_10_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_16_ins : a2_x2 + port map ( + i0 => na3_x1_10_sig, + i1 => o3_x2_6_sig, + q => a2_x2_16_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_49_ins : inv_x2 + port map ( + i => ram_idx_7(1), + nq => inv_x2_49_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_10_ins : no3_x1 + port map ( + i0 => inv_x2_49_sig, + i1 => b(0), + i2 => not_aux117, + nq => no3_x1_10_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_50_ins : inv_x2 + port map ( + i => ram_idx_3(1), + nq => inv_x2_50_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_11_ins : no3_x1 + port map ( + i0 => inv_x2_50_sig, + i1 => b(0), + i2 => not_aux119, + nq => no3_x1_11_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_51_ins : inv_x2 + port map ( + i => ram_idx_5(1), + nq => inv_x2_51_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_12_ins : no3_x1 + port map ( + i0 => inv_x2_51_sig, + i1 => b(0), + i2 => not_aux118, + nq => no3_x1_12_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_9_ins : no3_x1 + port map ( + i0 => no3_x1_12_sig, + i1 => no3_x1_11_sig, + i2 => no3_x1_10_sig, + nq => no3_x1_9_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_52_ins : inv_x2 + port map ( + i => ram_idx_15(1), + nq => inv_x2_52_sig, + vdd => vdd, + vss => vss + ); + +o3_x2_7_ins : o3_x2 + port map ( + i0 => not_aux112, + i1 => b(0), + i2 => inv_x2_52_sig, + q => o3_x2_7_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_14_ins : a3_x2 + port map ( + i0 => o3_x2_7_sig, + i1 => no3_x1_9_sig, + i2 => a2_x2_16_sig, + q => a3_x2_14_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_53_ins : inv_x2 + port map ( + i => ram_idx_1(1), + nq => inv_x2_53_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_13_ins : no3_x1 + port map ( + i0 => inv_x2_53_sig, + i1 => b(0), + i2 => not_aux120, + nq => no3_x1_13_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_15_ins : a3_x2 + port map ( + i0 => ram_idx_14(1), + i1 => b(0), + i2 => aux112, + q => a3_x2_15_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_16_ins : a3_x2 + port map ( + i0 => ram_idx_8(1), + i1 => b(0), + i2 => aux116, + q => a3_x2_16_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_17_ins : a3_x2 + port map ( + i0 => ram_idx_10(1), + i1 => b(0), + i2 => aux114, + q => a3_x2_17_sig, + vdd => vdd, + vss => vss + ); + +no4_x1_ins : no4_x1 + port map ( + i0 => a3_x2_17_sig, + i1 => a3_x2_16_sig, + i2 => a3_x2_15_sig, + i3 => no3_x1_13_sig, + nq => no4_x1_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_54_ins : inv_x2 + port map ( + i => ram_idx_11(1), + nq => inv_x2_54_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_15_ins : no3_x1 + port map ( + i0 => inv_x2_54_sig, + i1 => b(0), + i2 => not_aux114, + nq => no3_x1_15_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_18_ins : a3_x2 + port map ( + i0 => ram_idx_2(1), + i1 => b(0), + i2 => aux119, + q => a3_x2_18_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_19_ins : a3_x2 + port map ( + i0 => ram_idx_0(1), + i1 => b(0), + i2 => aux120, + q => a3_x2_19_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_14_ins : no3_x1 + port map ( + i0 => a3_x2_19_sig, + i1 => a3_x2_18_sig, + i2 => no3_x1_15_sig, + nq => no3_x1_14_sig, + vdd => vdd, + vss => vss + ); + +o3_x2_8_ins : o3_x2 + port map ( + i0 => not_aux99, + i1 => b(0), + i2 => not_ram_idx_13(1), + q => o3_x2_8_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_11_ins : na3_x1 + port map ( + i0 => ram_idx_6(1), + i1 => b(0), + i2 => aux117, + nq => na3_x1_11_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_12_ins : na3_x1 + port map ( + i0 => ram_idx_4(1), + i1 => b(0), + i2 => aux118, + nq => na3_x1_12_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_20_ins : a3_x2 + port map ( + i0 => na3_x1_12_sig, + i1 => na3_x1_11_sig, + i2 => o3_x2_8_sig, + q => a3_x2_20_sig, + vdd => vdd, + vss => vss + ); + +rb_1_ins : na4_x1 + port map ( + i0 => a3_x2_20_sig, + i1 => no3_x1_14_sig, + i2 => no4_x1_sig, + i3 => a3_x2_14_sig, + nq => rb(1), + vdd => vdd, + vss => vss + ); + +inv_x2_55_ins : inv_x2 + port map ( + i => ram_idx_5(2), + nq => inv_x2_55_sig, + vdd => vdd, + vss => vss + ); + +o3_x2_9_ins : o3_x2 + port map ( + i0 => not_aux118, + i1 => b(0), + i2 => inv_x2_55_sig, + q => o3_x2_9_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_13_ins : na3_x1 + port map ( + i0 => ram_idx_0(2), + i1 => b(0), + i2 => aux120, + nq => na3_x1_13_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_56_ins : inv_x2 + port map ( + i => ram_idx_3(2), + nq => inv_x2_56_sig, + vdd => vdd, + vss => vss + ); + +o3_x2_10_ins : o3_x2 + port map ( + i0 => not_aux119, + i1 => b(0), + i2 => inv_x2_56_sig, + q => o3_x2_10_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_21_ins : a3_x2 + port map ( + i0 => o3_x2_10_sig, + i1 => na3_x1_13_sig, + i2 => o3_x2_9_sig, + q => a3_x2_21_sig, + vdd => vdd, + vss => vss + ); + +o3_x2_11_ins : o3_x2 + port map ( + i0 => not_aux112, + i1 => b(0), + i2 => not_ram_idx_15(2), + q => o3_x2_11_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_14_ins : na3_x1 + port map ( + i0 => ram_idx_12(2), + i1 => b(0), + i2 => aux99, + nq => na3_x1_14_sig, + vdd => vdd, + vss => vss + ); + +o3_x2_12_ins : o3_x2 + port map ( + i0 => not_aux99, + i1 => b(0), + i2 => not_ram_idx_13(2), + q => o3_x2_12_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_22_ins : a3_x2 + port map ( + i0 => o3_x2_12_sig, + i1 => na3_x1_14_sig, + i2 => o3_x2_11_sig, + q => a3_x2_22_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_15_ins : na3_x1 + port map ( + i0 => ram_idx_6(2), + i1 => b(0), + i2 => aux117, + nq => na3_x1_15_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_16_ins : na3_x1 + port map ( + i0 => ram_idx_2(2), + i1 => b(0), + i2 => aux119, + nq => na3_x1_16_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_17_ins : na3_x1 + port map ( + i0 => ram_idx_4(2), + i1 => b(0), + i2 => aux118, + nq => na3_x1_17_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_23_ins : a3_x2 + port map ( + i0 => na3_x1_17_sig, + i1 => na3_x1_16_sig, + i2 => na3_x1_15_sig, + q => a3_x2_23_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_17_ins : no3_x1 + port map ( + i0 => not_ram_idx_11(2), + i1 => b(0), + i2 => not_aux114, + nq => no3_x1_17_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_18_ins : no3_x1 + port map ( + i0 => not_ram_idx_7(2), + i1 => b(0), + i2 => not_aux117, + nq => no3_x1_18_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_19_ins : no3_x1 + port map ( + i0 => not_ram_idx_9(2), + i1 => b(0), + i2 => not_aux116, + nq => no3_x1_19_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_16_ins : no3_x1 + port map ( + i0 => no3_x1_19_sig, + i1 => no3_x1_18_sig, + i2 => no3_x1_17_sig, + nq => no3_x1_16_sig, + vdd => vdd, + vss => vss + ); + +na4_x1_3_ins : na4_x1 + port map ( + i0 => no3_x1_16_sig, + i1 => a3_x2_23_sig, + i2 => a3_x2_22_sig, + i3 => a3_x2_21_sig, + nq => na4_x1_3_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_57_ins : inv_x2 + port map ( + i => ram_idx_1(2), + nq => inv_x2_57_sig, + vdd => vdd, + vss => vss + ); + +o3_x2_13_ins : o3_x2 + port map ( + i0 => not_aux120, + i1 => b(0), + i2 => inv_x2_57_sig, + q => o3_x2_13_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_18_ins : na3_x1 + port map ( + i0 => ram_idx_14(2), + i1 => b(0), + i2 => aux112, + nq => na3_x1_18_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_19_ins : na3_x1 + port map ( + i0 => ram_idx_8(2), + i1 => b(0), + i2 => aux116, + nq => na3_x1_19_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_20_ins : na3_x1 + port map ( + i0 => ram_idx_10(2), + i1 => b(0), + i2 => aux114, + nq => na3_x1_20_sig, + vdd => vdd, + vss => vss + ); + +na4_x1_4_ins : na4_x1 + port map ( + i0 => na3_x1_20_sig, + i1 => na3_x1_19_sig, + i2 => na3_x1_18_sig, + i3 => o3_x2_13_sig, + nq => na4_x1_4_sig, + vdd => vdd, + vss => vss + ); + +rb_2_ins : o2_x2 + port map ( + i0 => na4_x1_4_sig, + i1 => na4_x1_3_sig, + q => rb(2), + vdd => vdd, + vss => vss + ); + +inv_x2_58_ins : inv_x2 + port map ( + i => ram_idx_7(3), + nq => inv_x2_58_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_21_ins : no3_x1 + port map ( + i0 => inv_x2_58_sig, + i1 => b(0), + i2 => not_aux117, + nq => no3_x1_21_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_59_ins : inv_x2 + port map ( + i => ram_idx_3(3), + nq => inv_x2_59_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_22_ins : no3_x1 + port map ( + i0 => inv_x2_59_sig, + i1 => b(0), + i2 => not_aux119, + nq => no3_x1_22_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_60_ins : inv_x2 + port map ( + i => ram_idx_5(3), + nq => inv_x2_60_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_23_ins : no3_x1 + port map ( + i0 => inv_x2_60_sig, + i1 => b(0), + i2 => not_aux118, + nq => no3_x1_23_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_20_ins : no3_x1 + port map ( + i0 => no3_x1_23_sig, + i1 => no3_x1_22_sig, + i2 => no3_x1_21_sig, + nq => no3_x1_20_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_24_ins : no3_x1 + port map ( + i0 => not_ram_idx_15(3), + i1 => b(0), + i2 => not_aux112, + nq => no3_x1_24_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_25_ins : no3_x1 + port map ( + i0 => not_ram_idx_13(3), + i1 => b(0), + i2 => not_aux99, + nq => no3_x1_25_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_10_ins : no2_x1 + port map ( + i0 => no3_x1_25_sig, + i1 => no3_x1_24_sig, + nq => no2_x1_10_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_21_ins : na3_x1 + port map ( + i0 => ram_idx_12(3), + i1 => b(0), + i2 => aux99, + nq => na3_x1_21_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_24_ins : a3_x2 + port map ( + i0 => na3_x1_21_sig, + i1 => no2_x1_10_sig, + i2 => no3_x1_20_sig, + q => a3_x2_24_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_61_ins : inv_x2 + port map ( + i => ram_idx_1(3), + nq => inv_x2_61_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_26_ins : no3_x1 + port map ( + i0 => inv_x2_61_sig, + i1 => b(0), + i2 => not_aux120, + nq => no3_x1_26_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_25_ins : a3_x2 + port map ( + i0 => ram_idx_14(3), + i1 => b(0), + i2 => aux112, + q => a3_x2_25_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_26_ins : a3_x2 + port map ( + i0 => ram_idx_8(3), + i1 => b(0), + i2 => aux116, + q => a3_x2_26_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_27_ins : a3_x2 + port map ( + i0 => ram_idx_10(3), + i1 => b(0), + i2 => aux114, + q => a3_x2_27_sig, + vdd => vdd, + vss => vss + ); + +no4_x1_2_ins : no4_x1 + port map ( + i0 => a3_x2_27_sig, + i1 => a3_x2_26_sig, + i2 => a3_x2_25_sig, + i3 => no3_x1_26_sig, + nq => no4_x1_2_sig, + vdd => vdd, + vss => vss + ); + +inv_x2_62_ins : inv_x2 + port map ( + i => ram_idx_11(3), + nq => inv_x2_62_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_28_ins : no3_x1 + port map ( + i0 => inv_x2_62_sig, + i1 => b(0), + i2 => not_aux114, + nq => no3_x1_28_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_28_ins : a3_x2 + port map ( + i0 => ram_idx_2(3), + i1 => b(0), + i2 => aux119, + q => a3_x2_28_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_29_ins : a3_x2 + port map ( + i0 => ram_idx_0(3), + i1 => b(0), + i2 => aux120, + q => a3_x2_29_sig, + vdd => vdd, + vss => vss + ); + +no3_x1_27_ins : no3_x1 + port map ( + i0 => a3_x2_29_sig, + i1 => a3_x2_28_sig, + i2 => no3_x1_28_sig, + nq => no3_x1_27_sig, + vdd => vdd, + vss => vss + ); + +o3_x2_14_ins : o3_x2 + port map ( + i0 => not_aux116, + i1 => b(0), + i2 => not_ram_idx_9(3), + q => o3_x2_14_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_22_ins : na3_x1 + port map ( + i0 => ram_idx_6(3), + i1 => b(0), + i2 => aux117, + nq => na3_x1_22_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_23_ins : na3_x1 + port map ( + i0 => ram_idx_4(3), + i1 => b(0), + i2 => aux118, + nq => na3_x1_23_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_30_ins : a3_x2 + port map ( + i0 => na3_x1_23_sig, + i1 => na3_x1_22_sig, + i2 => o3_x2_14_sig, + q => a3_x2_30_sig, + vdd => vdd, + vss => vss + ); + +rb_3_ins : na4_x1 + port map ( + i0 => a3_x2_30_sig, + i1 => no3_x1_27_sig, + i2 => no4_x1_2_sig, + i3 => a3_x2_24_sig, + nq => rb(3), + vdd => vdd, + vss => vss + ); + +a3_x2_32_ins : a3_x2 + port map ( + i0 => a(3), + i1 => ram_idx_4(0), + i2 => aux107, + q => a3_x2_32_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_11_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux101, + nq => no2_x1_11_sig, + vdd => vdd, + vss => vss + ); + +noa22_x1_7_ins : noa22_x1 + port map ( + i0 => ram_idx_15(0), + i1 => no2_x1_11_sig, + i2 => a3_x2_32_sig, + nq => noa22_x1_7_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_12_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux105, + nq => no2_x1_12_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_13_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux110, + nq => no2_x1_13_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_14_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux103, + nq => no2_x1_14_sig, + vdd => vdd, + vss => vss + ); + +noa2a2a23_x1_ins : noa2a2a23_x1 + port map ( + i0 => ram_idx_14(0), + i1 => no2_x1_14_sig, + i2 => no2_x1_13_sig, + i3 => ram_idx_9(0), + i4 => ram_idx_13(0), + i5 => no2_x1_12_sig, + nq => noa2a2a23_x1_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_24_ins : na3_x1 + port map ( + i0 => a(3), + i1 => ram_idx_3(0), + i2 => aux108, + nq => na3_x1_24_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_31_ins : a3_x2 + port map ( + i0 => na3_x1_24_sig, + i1 => noa2a2a23_x1_sig, + i2 => noa22_x1_7_sig, + q => a3_x2_31_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_25_ins : na3_x1 + port map ( + i0 => a(3), + i1 => ram_idx_6(0), + i2 => aux103, + nq => na3_x1_25_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_26_ins : na3_x1 + port map ( + i0 => a(3), + i1 => ram_idx_5(0), + i2 => aux105, + nq => na3_x1_26_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_18_ins : a2_x2 + port map ( + i0 => na3_x1_26_sig, + i1 => na3_x1_25_sig, + q => a2_x2_18_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_15_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux107, + nq => no2_x1_15_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_16_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux111, + nq => no2_x1_16_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_17_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux108, + nq => no2_x1_17_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_18_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux109, + nq => no2_x1_18_sig, + vdd => vdd, + vss => vss + ); + +noa2a2a2a24_x1_ins : noa2a2a2a24_x1 + port map ( + i0 => ram_idx_10(0), + i1 => no2_x1_18_sig, + i2 => ram_idx_11(0), + i3 => no2_x1_17_sig, + i4 => no2_x1_16_sig, + i5 => ram_idx_8(0), + i6 => ram_idx_12(0), + i7 => no2_x1_15_sig, + nq => noa2a2a2a24_x1_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_17_ins : a2_x2 + port map ( + i0 => noa2a2a2a24_x1_sig, + i1 => a2_x2_18_sig, + q => a2_x2_17_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_27_ins : na3_x1 + port map ( + i0 => a(3), + i1 => ram_idx_2(0), + i2 => aux109, + nq => na3_x1_27_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_28_ins : na3_x1 + port map ( + i0 => a(3), + i1 => ram_idx_7(0), + i2 => aux101, + nq => na3_x1_28_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_29_ins : na3_x1 + port map ( + i0 => a(3), + i1 => ram_idx_0(0), + i2 => aux111, + nq => na3_x1_29_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_30_ins : na3_x1 + port map ( + i0 => a(3), + i1 => ram_idx_1(0), + i2 => aux110, + nq => na3_x1_30_sig, + vdd => vdd, + vss => vss + ); + +a4_x2_ins : a4_x2 + port map ( + i0 => na3_x1_30_sig, + i1 => na3_x1_29_sig, + i2 => na3_x1_28_sig, + i3 => na3_x1_27_sig, + q => a4_x2_sig, + vdd => vdd, + vss => vss + ); + +ra_0_ins : na3_x1 + port map ( + i0 => a4_x2_sig, + i1 => a2_x2_17_sig, + i2 => a3_x2_31_sig, + nq => ra(0), + vdd => vdd, + vss => vss + ); + +a3_x2_34_ins : a3_x2 + port map ( + i0 => a(3), + i1 => ram_idx_4(1), + i2 => aux107, + q => a3_x2_34_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_19_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux110, + nq => no2_x1_19_sig, + vdd => vdd, + vss => vss + ); + +noa22_x1_8_ins : noa22_x1 + port map ( + i0 => ram_idx_9(1), + i1 => no2_x1_19_sig, + i2 => a3_x2_34_sig, + nq => noa22_x1_8_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_20_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux103, + nq => no2_x1_20_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_21_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux107, + nq => no2_x1_21_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_22_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux105, + nq => no2_x1_22_sig, + vdd => vdd, + vss => vss + ); + +noa2a2a23_x1_2_ins : noa2a2a23_x1 + port map ( + i0 => ram_idx_13(1), + i1 => no2_x1_22_sig, + i2 => no2_x1_21_sig, + i3 => ram_idx_12(1), + i4 => ram_idx_14(1), + i5 => no2_x1_20_sig, + nq => noa2a2a23_x1_2_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_31_ins : na3_x1 + port map ( + i0 => a(3), + i1 => ram_idx_3(1), + i2 => aux108, + nq => na3_x1_31_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_33_ins : a3_x2 + port map ( + i0 => na3_x1_31_sig, + i1 => noa2a2a23_x1_2_sig, + i2 => noa22_x1_8_sig, + q => a3_x2_33_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_32_ins : na3_x1 + port map ( + i0 => a(3), + i1 => ram_idx_6(1), + i2 => aux103, + nq => na3_x1_32_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_33_ins : na3_x1 + port map ( + i0 => a(3), + i1 => ram_idx_5(1), + i2 => aux105, + nq => na3_x1_33_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_20_ins : a2_x2 + port map ( + i0 => na3_x1_33_sig, + i1 => na3_x1_32_sig, + q => a2_x2_20_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_23_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux108, + nq => no2_x1_23_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_24_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux109, + nq => no2_x1_24_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_25_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux111, + nq => no2_x1_25_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_26_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux101, + nq => no2_x1_26_sig, + vdd => vdd, + vss => vss + ); + +noa2a2a2a24_x1_2_ins : noa2a2a2a24_x1 + port map ( + i0 => no2_x1_26_sig, + i1 => ram_idx_15(1), + i2 => ram_idx_8(1), + i3 => no2_x1_25_sig, + i4 => no2_x1_24_sig, + i5 => ram_idx_10(1), + i6 => ram_idx_11(1), + i7 => no2_x1_23_sig, + nq => noa2a2a2a24_x1_2_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_19_ins : a2_x2 + port map ( + i0 => noa2a2a2a24_x1_2_sig, + i1 => a2_x2_20_sig, + q => a2_x2_19_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_34_ins : na3_x1 + port map ( + i0 => a(3), + i1 => ram_idx_2(1), + i2 => aux109, + nq => na3_x1_34_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_35_ins : na3_x1 + port map ( + i0 => a(3), + i1 => ram_idx_7(1), + i2 => aux101, + nq => na3_x1_35_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_36_ins : na3_x1 + port map ( + i0 => a(3), + i1 => ram_idx_0(1), + i2 => aux111, + nq => na3_x1_36_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_37_ins : na3_x1 + port map ( + i0 => a(3), + i1 => ram_idx_1(1), + i2 => aux110, + nq => na3_x1_37_sig, + vdd => vdd, + vss => vss + ); + +a4_x2_2_ins : a4_x2 + port map ( + i0 => na3_x1_37_sig, + i1 => na3_x1_36_sig, + i2 => na3_x1_35_sig, + i3 => na3_x1_34_sig, + q => a4_x2_2_sig, + vdd => vdd, + vss => vss + ); + +ra_1_ins : na3_x1 + port map ( + i0 => a4_x2_2_sig, + i1 => a2_x2_19_sig, + i2 => a3_x2_33_sig, + nq => ra(1), + vdd => vdd, + vss => vss + ); + +a3_x2_36_ins : a3_x2 + port map ( + i0 => a(3), + i1 => ram_idx_4(2), + i2 => aux107, + q => a3_x2_36_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_27_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux101, + nq => no2_x1_27_sig, + vdd => vdd, + vss => vss + ); + +noa22_x1_9_ins : noa22_x1 + port map ( + i0 => ram_idx_15(2), + i1 => no2_x1_27_sig, + i2 => a3_x2_36_sig, + nq => noa22_x1_9_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_28_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux105, + nq => no2_x1_28_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_29_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux110, + nq => no2_x1_29_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_30_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux108, + nq => no2_x1_30_sig, + vdd => vdd, + vss => vss + ); + +noa2a2a23_x1_3_ins : noa2a2a23_x1 + port map ( + i0 => ram_idx_11(2), + i1 => no2_x1_30_sig, + i2 => no2_x1_29_sig, + i3 => ram_idx_9(2), + i4 => ram_idx_13(2), + i5 => no2_x1_28_sig, + nq => noa2a2a23_x1_3_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_38_ins : na3_x1 + port map ( + i0 => a(3), + i1 => ram_idx_3(2), + i2 => aux108, + nq => na3_x1_38_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_35_ins : a3_x2 + port map ( + i0 => na3_x1_38_sig, + i1 => noa2a2a23_x1_3_sig, + i2 => noa22_x1_9_sig, + q => a3_x2_35_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_39_ins : na3_x1 + port map ( + i0 => a(3), + i1 => ram_idx_6(2), + i2 => aux103, + nq => na3_x1_39_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_40_ins : na3_x1 + port map ( + i0 => a(3), + i1 => ram_idx_5(2), + i2 => aux105, + nq => na3_x1_40_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_22_ins : a2_x2 + port map ( + i0 => na3_x1_40_sig, + i1 => na3_x1_39_sig, + q => a2_x2_22_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_31_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux103, + nq => no2_x1_31_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_32_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux107, + nq => no2_x1_32_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_33_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux109, + nq => no2_x1_33_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_34_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux111, + nq => no2_x1_34_sig, + vdd => vdd, + vss => vss + ); + +noa2a2a2a24_x1_3_ins : noa2a2a2a24_x1 + port map ( + i0 => no2_x1_34_sig, + i1 => ram_idx_8(2), + i2 => ram_idx_10(2), + i3 => no2_x1_33_sig, + i4 => no2_x1_32_sig, + i5 => ram_idx_12(2), + i6 => ram_idx_14(2), + i7 => no2_x1_31_sig, + nq => noa2a2a2a24_x1_3_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_21_ins : a2_x2 + port map ( + i0 => noa2a2a2a24_x1_3_sig, + i1 => a2_x2_22_sig, + q => a2_x2_21_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_41_ins : na3_x1 + port map ( + i0 => a(3), + i1 => ram_idx_2(2), + i2 => aux109, + nq => na3_x1_41_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_42_ins : na3_x1 + port map ( + i0 => a(3), + i1 => ram_idx_7(2), + i2 => aux101, + nq => na3_x1_42_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_43_ins : na3_x1 + port map ( + i0 => a(3), + i1 => ram_idx_0(2), + i2 => aux111, + nq => na3_x1_43_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_44_ins : na3_x1 + port map ( + i0 => a(3), + i1 => ram_idx_1(2), + i2 => aux110, + nq => na3_x1_44_sig, + vdd => vdd, + vss => vss + ); + +a4_x2_3_ins : a4_x2 + port map ( + i0 => na3_x1_44_sig, + i1 => na3_x1_43_sig, + i2 => na3_x1_42_sig, + i3 => na3_x1_41_sig, + q => a4_x2_3_sig, + vdd => vdd, + vss => vss + ); + +ra_2_ins : na3_x1 + port map ( + i0 => a4_x2_3_sig, + i1 => a2_x2_21_sig, + i2 => a3_x2_35_sig, + nq => ra(2), + vdd => vdd, + vss => vss + ); + +a3_x2_38_ins : a3_x2 + port map ( + i0 => a(3), + i1 => ram_idx_4(3), + i2 => aux107, + q => a3_x2_38_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_35_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux101, + nq => no2_x1_35_sig, + vdd => vdd, + vss => vss + ); + +noa22_x1_10_ins : noa22_x1 + port map ( + i0 => ram_idx_15(3), + i1 => no2_x1_35_sig, + i2 => a3_x2_38_sig, + nq => noa22_x1_10_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_36_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux105, + nq => no2_x1_36_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_37_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux110, + nq => no2_x1_37_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_38_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux103, + nq => no2_x1_38_sig, + vdd => vdd, + vss => vss + ); + +noa2a2a23_x1_4_ins : noa2a2a23_x1 + port map ( + i0 => ram_idx_14(3), + i1 => no2_x1_38_sig, + i2 => no2_x1_37_sig, + i3 => ram_idx_9(3), + i4 => ram_idx_13(3), + i5 => no2_x1_36_sig, + nq => noa2a2a23_x1_4_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_45_ins : na3_x1 + port map ( + i0 => a(3), + i1 => ram_idx_3(3), + i2 => aux108, + nq => na3_x1_45_sig, + vdd => vdd, + vss => vss + ); + +a3_x2_37_ins : a3_x2 + port map ( + i0 => na3_x1_45_sig, + i1 => noa2a2a23_x1_4_sig, + i2 => noa22_x1_10_sig, + q => a3_x2_37_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_46_ins : na3_x1 + port map ( + i0 => a(3), + i1 => ram_idx_6(3), + i2 => aux103, + nq => na3_x1_46_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_47_ins : na3_x1 + port map ( + i0 => a(3), + i1 => ram_idx_5(3), + i2 => aux105, + nq => na3_x1_47_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_24_ins : a2_x2 + port map ( + i0 => na3_x1_47_sig, + i1 => na3_x1_46_sig, + q => a2_x2_24_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_39_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux107, + nq => no2_x1_39_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_40_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux109, + nq => no2_x1_40_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_41_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux111, + nq => no2_x1_41_sig, + vdd => vdd, + vss => vss + ); + +no2_x1_42_ins : no2_x1 + port map ( + i0 => a(3), + i1 => not_aux108, + nq => no2_x1_42_sig, + vdd => vdd, + vss => vss + ); + +noa2a2a2a24_x1_4_ins : noa2a2a2a24_x1 + port map ( + i0 => no2_x1_42_sig, + i1 => ram_idx_11(3), + i2 => ram_idx_8(3), + i3 => no2_x1_41_sig, + i4 => no2_x1_40_sig, + i5 => ram_idx_10(3), + i6 => ram_idx_12(3), + i7 => no2_x1_39_sig, + nq => noa2a2a2a24_x1_4_sig, + vdd => vdd, + vss => vss + ); + +a2_x2_23_ins : a2_x2 + port map ( + i0 => noa2a2a2a24_x1_4_sig, + i1 => a2_x2_24_sig, + q => a2_x2_23_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_48_ins : na3_x1 + port map ( + i0 => a(3), + i1 => ram_idx_2(3), + i2 => aux109, + nq => na3_x1_48_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_49_ins : na3_x1 + port map ( + i0 => a(3), + i1 => ram_idx_7(3), + i2 => aux101, + nq => na3_x1_49_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_50_ins : na3_x1 + port map ( + i0 => a(3), + i1 => ram_idx_0(3), + i2 => aux111, + nq => na3_x1_50_sig, + vdd => vdd, + vss => vss + ); + +na3_x1_51_ins : na3_x1 + port map ( + i0 => a(3), + i1 => ram_idx_1(3), + i2 => aux110, + nq => na3_x1_51_sig, + vdd => vdd, + vss => vss + ); + +a4_x2_4_ins : a4_x2 + port map ( + i0 => na3_x1_51_sig, + i1 => na3_x1_50_sig, + i2 => na3_x1_49_sig, + i3 => na3_x1_48_sig, + q => a4_x2_4_sig, + vdd => vdd, + vss => vss + ); + +ra_3_ins : na3_x1 + port map ( + i0 => a4_x2_4_sig, + i1 => a2_x2_23_sig, + i2 => a3_x2_37_sig, + nq => ra(3), + vdd => vdd, + vss => vss + ); + + +end structural; diff --git a/documentation/examples/CMakeLists.txt b/documentation/examples/CMakeLists.txt new file mode 100644 index 00000000..660463e7 --- /dev/null +++ b/documentation/examples/CMakeLists.txt @@ -0,0 +1,3 @@ + + add_subdirectory(AM2901) + diff --git a/crlcore/doc/general-index.html b/documentation/general-index.html similarity index 100% rename from crlcore/doc/general-index.html rename to documentation/general-index.html diff --git a/hurricane/doc/hurricane/images/transf-R1.fig b/hurricane/doc/hurricane/images/transf-R1.fig index 9ebcff63..30d35119 100644 --- a/hurricane/doc/hurricane/images/transf-R1.fig +++ b/hurricane/doc/hurricane/images/transf-R1.fig @@ -18,21 +18,21 @@ Single 2 2 0 4 0 0 60 -1 7 0.000 0 0 -1 0 0 5 3375 7500 3975 7500 3975 8400 3375 8400 3375 7500 -6 -6 2400 8325 3450 9075 -6 2700 8475 3150 8850 +6 2400 7725 3450 8475 +6 2700 7875 3150 8250 2 1 0 4 18 18 45 -1 -1 0.000 0 0 -1 0 0 3 - 3075 8775 2775 8775 2775 8550 + 3075 8175 2775 8175 2775 7950 2 1 0 4 18 18 45 -1 -1 0.000 0 0 -1 0 0 2 - 2925 8775 2925 8625 + 2925 8175 2925 8025 -6 2 2 0 4 18 18 50 -1 30 0.000 0 0 -1 0 0 5 - 2475 9000 2475 8400 3375 8400 3375 9000 2475 9000 + 2475 8400 2475 7800 3375 7800 3375 8400 2475 8400 -6 2 1 0 1 0 5 70 -1 -1 0.000 0 0 -1 1 0 2 0 0 1.00 60.00 120.00 3375 9300 3375 7200 +2 2 0 0 32 32 100 -1 40 0.000 0 0 -1 0 0 5 + 2325 7125 4275 7125 4275 9375 2325 9375 2325 7125 2 1 0 1 0 5 70 -1 -1 0.000 0 0 -1 1 0 2 0 0 1.00 60.00 120.00 2475 8400 4275 8400 -2 2 0 0 32 32 100 -1 40 0.000 0 0 -1 0 0 5 - 2325 7125 4275 7125 4275 9375 2325 9375 2325 7125 diff --git a/hurricane/doc/hurricane/images/transf-R1.png b/hurricane/doc/hurricane/images/transf-R1.png index 8fa4cfc5..0d64501d 100644 Binary files a/hurricane/doc/hurricane/images/transf-R1.png and b/hurricane/doc/hurricane/images/transf-R1.png differ diff --git a/katabatic/src/GCell.cpp b/katabatic/src/GCell.cpp index bc9a3653..b9df4460 100644 --- a/katabatic/src/GCell.cpp +++ b/katabatic/src/GCell.cpp @@ -1,8 +1,7 @@ - // -*- C++ -*- // // This file is part of the Coriolis Software. -// Copyright (c) UPMC 2008-2013, All Rights Reserved +// Copyright (c) UPMC 2008-2014, All Rights Reserved // // +-----------------------------------------------------------------+ // | C O R I O L I S | diff --git a/katabatic/src/LayerAssign.cpp b/katabatic/src/LayerAssign.cpp index c4b88983..70d00d53 100644 --- a/katabatic/src/LayerAssign.cpp +++ b/katabatic/src/LayerAssign.cpp @@ -1,8 +1,7 @@ - // -*- C++ -*- // // This file is part of the Coriolis Software. -// Copyright (c) UPMC 2008-2013, All Rights Reserved +// Copyright (c) UPMC 2008-2014, All Rights Reserved // // +-----------------------------------------------------------------+ // | C O R I O L I S | diff --git a/kite/src/Configuration.cpp b/kite/src/Configuration.cpp index 8d8e8472..4ca4f1fa 100644 --- a/kite/src/Configuration.cpp +++ b/kite/src/Configuration.cpp @@ -1,7 +1,7 @@ // -*- mode: C++; explicit-buffer-name: "Configuration.cpp" -*- // // This file is part of the Coriolis Software. -// Copyright (c) UPMC/LIP6 2008-2013, All Rights Reserved +// Copyright (c) UPMC/LIP6 2008-2014, All Rights Reserved // // +-----------------------------------------------------------------+ // | C O R I O L I S | @@ -54,24 +54,24 @@ namespace Kite { _ripupLimits[GlobalRipupLimit] = Cfg::getParamInt("kite.globalRipupLimit" , 5)->asInt(); _ripupLimits[LongGlobalRipupLimit] = Cfg::getParamInt("kite.longGlobalRipupLimit" , 5)->asInt(); - for ( size_t i=0 ; isetDouble(threshold); - _globalMinBreaks[i] = DbU::lambda (Cfg::getParamDouble(paramName.str())->asDouble()); - } + // Cfg::getParamDouble(paramName.str())->setDouble(threshold); + // _globalMinBreaks[i] = DbU::lambda (Cfg::getParamDouble(paramName.str())->asDouble()); + // } } @@ -260,12 +260,12 @@ namespace Kite { record->add ( getSlot("_ripupLimits[GlobalRipupLimit]" ,_ripupLimits[GlobalRipupLimit] ) ); record->add ( getSlot("_ripupLimits[LongGlobalRipupLimit]",_ripupLimits[LongGlobalRipupLimit]) ); - for ( size_t i=0 ; iadd ( DbU::getValueSlot(paramName.str(),&_globalMinBreaks[i]) ); - } + // record->add ( DbU::getValueSlot(paramName.str(),&_globalMinBreaks[i]) ); + // } } return record; diff --git a/kite/src/Manipulator.cpp b/kite/src/Manipulator.cpp index 14adffc9..5a8f8eb9 100644 --- a/kite/src/Manipulator.cpp +++ b/kite/src/Manipulator.cpp @@ -1,7 +1,7 @@ // -*- C++ -*- // // This file is part of the Coriolis Software. -// Copyright (c) UPMC 2008-2013, All Rights Reserved +// Copyright (c) UPMC 2008-2014, All Rights Reserved // // +-----------------------------------------------------------------+ // | C O R I O L I S | @@ -639,7 +639,6 @@ namespace Kite { bool leftIntrication = false; bool rightIntrication = false; bool success = true; - unsigned long maxId = AutoSegment::getMaxId(); ltrace(200) << "Manipulator::insertInTrack() - " << toFree << endl; diff --git a/kite/src/kite/Configuration.h b/kite/src/kite/Configuration.h index dc5b33ee..f71f09e6 100644 --- a/kite/src/kite/Configuration.h +++ b/kite/src/kite/Configuration.h @@ -1,7 +1,7 @@ // -*- mode: C++; explicit-buffer-name: "Configuration.h" -*- // // This file is part of the Coriolis Software. -// Copyright (c) UPMC 2008-2013, All Rights Reserved +// Copyright (c) UPMC 2008-2014, All Rights Reserved // // +-----------------------------------------------------------------+ // | C O R I O L I S | @@ -81,13 +81,11 @@ namespace Kite { inline PostEventCb_t& getPostEventCb (); inline unsigned long getEventsLimit () const; inline float getExpandStep () const; - inline DbU::Unit getGlobalMinBreak ( unsigned int depth ) const; inline unsigned int getRipupCost () const; unsigned int getRipupLimit ( unsigned int type ) const; inline float getEdgeCapacityPercent () const; inline void setEventsLimit ( unsigned long ); inline void setExpandStep ( float ); - inline void setGlobalMinBreak ( unsigned int depth, DbU::Unit ); inline void setRipupCost ( unsigned int ); void setRipupLimit ( unsigned int limit, unsigned int type ); inline void setPostEventCb ( PostEventCb_t ); @@ -101,7 +99,6 @@ namespace Kite { PostEventCb_t _postEventCb; float _edgeCapacityPercent; float _expandStep; - DbU::Unit _globalMinBreaks[MaxMetalDepth]; unsigned int _ripupLimits [RipupLimitsTableSize]; unsigned int _ripupCost; unsigned long _eventsLimit; @@ -118,12 +115,10 @@ namespace Kite { inline unsigned int Configuration::getRipupCost () const { return _ripupCost; } inline float Configuration::getExpandStep () const { return _expandStep; } inline float Configuration::getEdgeCapacityPercent () const { return _edgeCapacityPercent; } - inline DbU::Unit Configuration::getGlobalMinBreak ( unsigned int depth ) const { return _globalMinBreaks[ (depth>=MaxMetalDepth) ? MaxMetalDepth-1 : depth ]; } inline void Configuration::setRipupCost ( unsigned int cost ) { _ripupCost = cost; } inline void Configuration::setExpandStep ( float step ) { _expandStep = step; } inline void Configuration::setPostEventCb ( PostEventCb_t cb ) { _postEventCb = cb; } inline void Configuration::setEventsLimit ( unsigned long limit ) { _eventsLimit = limit; } - inline void Configuration::setGlobalMinBreak ( unsigned int depth, DbU::Unit threshold ) { _globalMinBreaks[ (depth>=MaxMetalDepth) ? MaxMetalDepth-1 : depth ] = threshold; } diff --git a/kite/src/kite/KiteEngine.h b/kite/src/kite/KiteEngine.h index ac989057..e2814f83 100644 --- a/kite/src/kite/KiteEngine.h +++ b/kite/src/kite/KiteEngine.h @@ -1,8 +1,7 @@ - // -*- C++ -*- // // This file is part of the Coriolis Software. -// Copyright (c) UPMC 2008-2013, All Rights Reserved +// Copyright (c) UPMC 2008-2014, All Rights Reserved // // +-----------------------------------------------------------------+ // | C O R I O L I S | @@ -74,7 +73,6 @@ namespace Kite { inline unsigned int getRipupCost () const; inline float getExpandStep () const; inline float getEdgeCapacityPercent () const; - inline DbU::Unit getGlobalMinBreak ( unsigned int depth ) const; virtual const Name& getName () const; inline Configuration::PostEventCb_t& getPostEventCb (); @@ -94,7 +92,6 @@ namespace Kite { inline void setRipupCost ( unsigned int ); inline void setExpandStep ( float ); inline void setEdgeCapacityPercent ( float ); - inline void setGlobalMinBreak ( unsigned int depth, DbU::Unit ); void buildPowerRails (); void protectRoutingPads (); void preProcess (); @@ -152,7 +149,6 @@ namespace Kite { inline unsigned int KiteEngine::getRipupCost () const { return _configuration->getRipupCost(); } inline float KiteEngine::getExpandStep () const { return _configuration->getExpandStep(); } inline float KiteEngine::getEdgeCapacityPercent () const { return _configuration->getEdgeCapacityPercent(); } - inline DbU::Unit KiteEngine::getGlobalMinBreak ( unsigned int depth ) const { return _configuration->getGlobalMinBreak(depth); } inline unsigned int KiteEngine::getRipupLimit ( unsigned int type ) const { return _configuration->getRipupLimit(type); } inline NegociateWindow* KiteEngine::getNegociateWindow () { return _negociateWindow; } inline size_t KiteEngine::getRoutingPlanesSize () const { return _routingPlanes.size(); } @@ -161,7 +157,6 @@ namespace Kite { inline void KiteEngine::setRipupCost ( unsigned int cost ) { _configuration->setRipupCost(cost); } inline void KiteEngine::setExpandStep ( float step ) { _configuration->setExpandStep(step); } inline void KiteEngine::setEdgeCapacityPercent ( float percent ) { _configuration->setEdgeCapacityPercent(percent); } - inline void KiteEngine::setGlobalMinBreak ( unsigned int depth, DbU::Unit threshold ) { _configuration->setGlobalMinBreak(depth,threshold); } inline void KiteEngine::setMinimumWL ( double minimum ) { _minimumWL = minimum; } inline void KiteEngine::setPostEventCb ( Configuration::PostEventCb_t cb ) { _configuration->setPostEventCb(cb); } inline void KiteEngine::printConfiguration () const { _configuration->print(getCell()); }