riscv
/
coriolis
mirror of https://gitlab.lip6.fr/vlsi-eda/coriolis.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

createPartRing do not be there ??? 

use the python notation [-1] to access last bit of a net
This commit is contained in:
Roselyne Chotin-Avot 2017-04-25 16:18:18 +02:00
parent 2396ff7120
commit 0f8b767f1b
1 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
stratus1/src/stratus/st_net.py
View File

@ -111,6 +111,8 @@ class net :
##### For buses ##### ##### For buses #####
def __getitem__ ( self, indice ) : def __getitem__ ( self, indice ) :
if indice == -1:
return Sig ( self, self._ind + self._arity - 1 )
if ( indice < self._ind ) or ( indice >= ( self._ind + self._arity ) ) : if ( indice < self._ind ) or ( indice >= ( self._ind + self._arity ) ) :
err = "\n[Stratus ERROR] [] : bad index " + str(indice) + " for net : " \ err = "\n[Stratus ERROR] [] : bad index " + str(indice) + " for net : " \
+ self._name + " of arity " + str(self._arity) + self._name + " of arity " + str(self._arity)
@ -234,8 +236,8 @@ class net :
if self._st_cell._hur_cell : if self._st_cell._hur_cell :
net.hur_merge() net.hur_merge()
for i in range ( net._arity ) : #for i in range ( net._arity ) :
CRL.createPartRing ( self._st_cell._hur_cell, netInCell._hur_net[i+self._ind].getName() ) # FIXME plante avec le adder mixed dans un cas particulier indetermine .... # CRL.createPartRing ( self._st_cell._hur_cell, netInCell._hur_net[i+self._ind].getName() ) # FIXME plante avec le adder mixed dans un cas particulier indetermine ....
##### Instanciation of a buffer ##### ##### Instanciation of a buffer #####
def Buffer ( self ) : def Buffer ( self ) :