diff --git a/crlcore/doc/crlcore/html/AcmSigda_8h_source.html b/crlcore/doc/crlcore/html/AcmSigda_8h_source.html index c9e82b04..d8b0635a 100644 --- a/crlcore/doc/crlcore/html/AcmSigda_8h_source.html +++ b/crlcore/doc/crlcore/html/AcmSigda_8h_source.html @@ -54,7 +54,7 @@ $(function() {
- +
Generated by doxygen 1.8.14 on Thu Oct 18 2018Generated by doxygen 1.8.14 on Sun May 26 2019 Return to top of page
diff --git a/crlcore/doc/crlcore/html/AllianceFramework_8h_source.html b/crlcore/doc/crlcore/html/AllianceFramework_8h_source.html index 87ce4f41..bd55ab71 100644 --- a/crlcore/doc/crlcore/html/AllianceFramework_8h_source.html +++ b/crlcore/doc/crlcore/html/AllianceFramework_8h_source.html @@ -44,42 +44,44 @@ $(function() {
AllianceFramework.h
-
1 // -*- C++ -*-
2 //
3 // This file is part of the Coriolis Software.
4 // Copyright (c) UPMC 2008-2018, All Rights Reserved
5 //
6 // +-----------------------------------------------------------------+
7 // | C O R I O L I S |
8 // | Alliance / Hurricane Interface |
9 // | |
10 // | Author : Jean-Paul CHAPUT |
11 // | E-mail : Jean-Paul.Chaput@lip6.fr |
12 // | =============================================================== |
13 // | C++ Header : "./crlcore/AllianceFramework.h" |
14 // +-----------------------------------------------------------------+
15 
16 
17 #ifndef CRL_ALLIANCE_FRAMEWORK_H
18 #define CRL_ALLIANCE_FRAMEWORK_H
19 
20 #include <map>
21 #include <limits>
22 #include "hurricane/Cell.h"
23 #include "crlcore/Environment.h"
24 #include "crlcore/AllianceLibrary.h"
25 #include "crlcore/Catalog.h"
26 #include "crlcore/ParsersDrivers.h"
27 
28 
29 namespace CRL {
30 
31  using Hurricane::Observable;
32  using Hurricane::BaseObserver;
33  using Hurricane::JsonObject;
34  using Hurricane::JsonStack;
35  using Hurricane::Cell;
36  using Hurricane::Net;
37  class RoutingGauge;
38  class CellGauge;
39 
40 
41  class AllianceFramework {
42  public:
43  enum FunctionsFlags { NoFlags = 0
44  , NoPythonInit = (1<<0)
45  };
46  enum InstancesCountFlags { Recursive = (1<<0)
47  , IgnoreFeeds = (1<<1)
48  };
49  enum LibraryFlags { CreateLibrary = (1<<0)
50  , AppendLibrary = (1<<1)
51  , HasCatalog = (1<<2)
52  };
53  enum NotifyFlags { AddedLibrary = (1<<0)
54  , RemovedLibrary = (1<<1)
55  , ConfigChanged = (1<<2)
56  };
57  public:
58  // Constructors.
59  static AllianceFramework* create ( unsigned long flags=NoFlags );
60  // Destructors.
61  void destroy ();
62  // Accessors.
63  static AllianceFramework* get ();
64  string getPrint () const;
65  // Predicates.
66  Catalog::State* isInCatalog ( const Name& );
67  Catalog::State* isInCatalog ( string );
68  inline bool isPOWER ( const char* name );
69  inline bool isPOWER ( const string& name );
70  inline bool isPOWER ( const Name& name );
71  inline bool isGROUND ( const char* name );
72  inline bool isGROUND ( const string& name );
73  inline bool isGROUND ( const Name& name );
74  inline bool isCLOCK ( const char* name );
75  inline bool isCLOCK ( const string& name );
76  inline bool isCLOCK ( const Name& name );
77  inline bool isBLOCKAGE ( const char* name );
78  inline bool isBLOCKAGE ( const string& name );
79  inline bool isBLOCKAGE ( const Name& name );
80  inline bool isBLOCKAGE ( const Net* net );
81  inline bool isPad ( const char* name );
82  inline bool isPad ( const string& name );
83  inline bool isPad ( const Name& name );
84  inline bool isPad ( const Cell* );
85  // Accessors.
86  inline Environment* getEnvironment ();
87  inline Catalog* getCatalog ();
88  inline const Name& getParentLibraryName () const;
89  inline Library* getParentLibrary ();
90  Library* getLibrary ( unsigned int index );
91  Library* getLibrary ( const Name& libName );
92  AllianceLibrary* getAllianceLibrary ( unsigned int index );
93  AllianceLibrary* getAllianceLibrary ( const Name& libName, unsigned int flags );
94  AllianceLibrary* getAllianceLibrary ( Library* );
95  AllianceLibrary* createLibrary ( const string& path, unsigned int flags, string libName="" );
96  inline const AllianceLibraries& getAllianceLibraries () const;
97  void saveLibrary ( Library* );
98  void saveLibrary ( AllianceLibrary* );
99  RoutingGauge* getRoutingGauge ( const Name& name="" );
100  CellGauge* getCellGauge ( const Name& name="" );
101  inline const Name getDefaultCGPinLayerName () const;
102  // Modifiers.
103  RoutingGauge* setRoutingGauge ( const Name& name="" );
104  CellGauge* setCellGauge ( const Name& name="" );
105  void addRoutingGauge ( RoutingGauge* );
106  void addCellGauge ( CellGauge* );
107  void addObserver ( BaseObserver* );
108  void removeObserver ( BaseObserver* );
109  void notify ( unsigned int flags );
110  // Cell Management.
111  Cell* cellLoader ( const string& rpath );
112  Cell* getCell ( const string& name
113  , unsigned int mode
114  , unsigned int depth=(unsigned int)-1 );
115  Cell* createCell ( const string& name, AllianceLibrary* library=NULL );
116  void saveCell ( Cell* , unsigned int mode );
117  unsigned int loadLibraryCells ( Library* );
118  unsigned int loadLibraryCells ( const Name& );
119  static size_t getInstancesCount ( Cell*, unsigned int flags );
120  // Hurricane Managment.
121  void toJson ( JsonWriter* ) const;
122  inline string _getTypeName () const;
123  string _getString () const;
124  Record* _getRecord () const;
125 
126  // Internals - Attributes.
127  protected:
128  static const Name _parentLibraryName;
129  static AllianceFramework* _singleton;
130  Observable _observers;
131  Environment _environment;
132  ParsersMap _parsers;
133  DriversMap _drivers;
134  Catalog _catalog;
135  AllianceLibraries _libraries;
136  Library* _parentLibrary;
137  map<Name,RoutingGauge*> _routingGauges;
138  RoutingGauge* _defaultRoutingGauge;
139  map<Name,CellGauge*> _cellGauges;
140  CellGauge* _defaultCellGauge;
141 
142  // Internals - Constructors.
143  AllianceFramework ();
144  AllianceFramework ( const AllianceFramework& );
145  AllianceFramework& operator= ( const AllianceFramework& );
146  // Internals - Destructors.
147  ~AllianceFramework ();
148  // Internals - Methods.
149  bool _readLocate ( const string& file, unsigned int mode, bool isLib=false );
150  bool _writeLocate ( const string& file, unsigned int mode, bool isLib=false );
151  AllianceLibrary* _createLibrary ( const string& path, bool& hasCatalog );
152  void _bindLibraries ();
153  };
154 
155  inline bool AllianceFramework::isPOWER ( const char* name ) { return _environment.isPOWER(name); }
156  inline bool AllianceFramework::isPOWER ( const string& name ) { return isPOWER(name.c_str()); }
157  inline bool AllianceFramework::isPOWER ( const Name& name ) { return isPOWER(getString(name)); }
158  inline bool AllianceFramework::isGROUND ( const char* name ) { return _environment.isGROUND(name); }
159  inline bool AllianceFramework::isGROUND ( const string& name ) { return isGROUND(name.c_str()); }
160  inline bool AllianceFramework::isGROUND ( const Name& name ) { return isGROUND(getString(name)); }
161  inline bool AllianceFramework::isCLOCK ( const char* name ) { return _environment.isCLOCK(name); }
162  inline bool AllianceFramework::isCLOCK ( const string& name ) { return isCLOCK(name.c_str()); }
163  inline bool AllianceFramework::isCLOCK ( const Name& name ) { return isCLOCK(getString(name)); }
164  inline bool AllianceFramework::isBLOCKAGE ( const char* name ) { return _environment.isBLOCKAGE(name); }
165  inline bool AllianceFramework::isBLOCKAGE ( const string& name ) { return isBLOCKAGE(name.c_str()); }
166  inline bool AllianceFramework::isBLOCKAGE ( const Name& name ) { return isBLOCKAGE(getString(name)); }
167  inline bool AllianceFramework::isBLOCKAGE ( const Net* net ) { return isBLOCKAGE(net->getName()); }
168  inline bool AllianceFramework::isPad ( const char* name ) { return _environment.isPad(name); }
169  inline bool AllianceFramework::isPad ( const string& name ) { return isPad(name.c_str()); }
170  inline bool AllianceFramework::isPad ( const Name& name ) { return isPad(getString(name)); }
171  inline bool AllianceFramework::isPad ( const Cell* cell ) { return isPad(cell->getName()); }
172  inline Environment* AllianceFramework::getEnvironment () { return &_environment; }
173  inline Catalog* AllianceFramework::getCatalog () { return &_catalog; }
174  inline const Name& AllianceFramework::getParentLibraryName
175  () const { return _parentLibraryName; }
176  inline Library* AllianceFramework::getParentLibrary () { return _parentLibrary; }
177  inline const AllianceLibraries&
178  AllianceFramework::getAllianceLibraries () const { return _libraries; }
179 // TEMPORARY.
180  inline const Name AllianceFramework::getDefaultCGPinLayerName
181  () const { return "CALU1"; }
182  inline string AllianceFramework::_getTypeName () const { return "AllianceFramework"; }
183 
184 
185  class JsonAllianceFramework : public JsonObject {
186  public:
187  static void initialize ();
188  JsonAllianceFramework( unsigned long );
189  virtual ~JsonAllianceFramework();
190  virtual string getTypeName () const;
191  virtual JsonAllianceFramework* clone ( unsigned long ) const;
192  virtual void toData ( JsonStack& );
193  private:
194  std::string _defaultRoutingGauge;
195  std::string _defaultCellGauge;
196  };
197 
198 
199 } // CRL namespace.
200 
201 
202 INSPECTOR_P_SUPPORT(CRL::AllianceFramework);
203 
204 #endif // CRL_ALLIANCE_FRAMEWORK_H
CRL::Environment::isBLOCKAGE
bool isBLOCKAGE(const char *name) const
-
CRL::AllianceFramework::getParentLibrary
Library * getParentLibrary()
Definition: AllianceFramework.h:176
+
1 // -*- C++ -*-
2 //
3 // This file is part of the Coriolis Software.
4 // Copyright (c) UPMC 2008-2018, All Rights Reserved
5 //
6 // +-----------------------------------------------------------------+
7 // | C O R I O L I S |
8 // | Alliance / Hurricane Interface |
9 // | |
10 // | Author : Jean-Paul CHAPUT |
11 // | E-mail : Jean-Paul.Chaput@lip6.fr |
12 // | =============================================================== |
13 // | C++ Header : "./crlcore/AllianceFramework.h" |
14 // +-----------------------------------------------------------------+
15 
16 
17 #ifndef CRL_ALLIANCE_FRAMEWORK_H
18 #define CRL_ALLIANCE_FRAMEWORK_H
19 
20 #include <map>
21 #include <limits>
22 #include "hurricane/Cell.h"
23 #include "crlcore/Environment.h"
24 #include "crlcore/AllianceLibrary.h"
25 #include "crlcore/Catalog.h"
26 #include "crlcore/ParsersDrivers.h"
27 
28 
29 namespace CRL {
30 
31  using Hurricane::Observable;
32  using Hurricane::BaseObserver;
33  using Hurricane::JsonObject;
34  using Hurricane::JsonStack;
35  using Hurricane::DbU;
36  using Hurricane::Cell;
37  using Hurricane::Net;
38  class RoutingGauge;
39  class CellGauge;
40 
41 
42  class AllianceFramework {
43  public:
44  enum FunctionsFlags { NoFlags = 0
45  , NoPythonInit = (1<<0)
46  };
47  enum InstancesCountFlags { Recursive = (1<<0)
48  , IgnoreFeeds = (1<<1)
49  };
50  enum LibraryFlags { CreateLibrary = (1<<0)
51  , AppendLibrary = (1<<1)
52  , HasCatalog = (1<<2)
53  };
54  enum NotifyFlags { AddedLibrary = (1<<0)
55  , RemovedLibrary = (1<<1)
56  , ConfigChanged = (1<<2)
57  };
58  public:
59  // Constructors.
60  static AllianceFramework* create ( unsigned long flags=NoFlags );
61  // Destructors.
62  void destroy ();
63  // Accessors.
64  static AllianceFramework* get ();
65  string getPrint () const;
66  // Predicates.
67  Catalog::State* isInCatalog ( const Name& );
68  Catalog::State* isInCatalog ( string );
69  inline bool isPOWER ( const char* name );
70  inline bool isPOWER ( const string& name );
71  inline bool isPOWER ( const Name& name );
72  inline bool isGROUND ( const char* name );
73  inline bool isGROUND ( const string& name );
74  inline bool isGROUND ( const Name& name );
75  inline bool isCLOCK ( const char* name );
76  inline bool isCLOCK ( const string& name );
77  inline bool isCLOCK ( const Name& name );
78  inline bool isBLOCKAGE ( const char* name );
79  inline bool isBLOCKAGE ( const string& name );
80  inline bool isBLOCKAGE ( const Name& name );
81  inline bool isBLOCKAGE ( const Net* net );
82  inline bool isPad ( const char* name );
83  inline bool isPad ( const string& name );
84  inline bool isPad ( const Name& name );
85  inline bool isPad ( const Cell* );
86  // Accessors.
87  inline Environment* getEnvironment ();
88  inline Catalog* getCatalog ();
89  inline const Name& getParentLibraryName () const;
90  inline Library* getParentLibrary ();
91  Library* getLibrary ( unsigned int index );
92  Library* getLibrary ( const Name& libName );
93  AllianceLibrary* getAllianceLibrary ( unsigned int index );
94  AllianceLibrary* getAllianceLibrary ( const Name& libName, unsigned int flags );
95  AllianceLibrary* getAllianceLibrary ( Library* );
96  AllianceLibrary* createLibrary ( const string& path, unsigned int flags, string libName="" );
97  inline const AllianceLibraries& getAllianceLibraries () const;
98  void saveLibrary ( Library* );
99  void saveLibrary ( AllianceLibrary* );
100  RoutingGauge* getRoutingGauge ( const Name& name="" );
101  CellGauge* getCellGauge ( const Name& name="" );
102  CellGauge* matchCellGauge ( DbU::Unit width, DbU::Unit height ) const;
103  CellGauge* matchCellGaugeByHeight ( DbU::Unit height ) const;
104  inline const Name getDefaultCGPinLayerName () const;
105  // Modifiers.
106  RoutingGauge* setRoutingGauge ( const Name& name="" );
107  CellGauge* setCellGauge ( const Name& name="" );
108  void addRoutingGauge ( RoutingGauge* );
109  void addCellGauge ( CellGauge* );
110  void addObserver ( BaseObserver* );
111  void removeObserver ( BaseObserver* );
112  void notify ( unsigned int flags );
113  // Cell Management.
114  Cell* cellLoader ( const string& rpath );
115  Cell* getCell ( const string& name
116  , unsigned int mode
117  , unsigned int depth=(unsigned int)-1 );
118  Cell* createCell ( const string& name, AllianceLibrary* library=NULL );
119  void saveCell ( Cell* , unsigned int mode );
120  unsigned int loadLibraryCells ( Library* );
121  unsigned int loadLibraryCells ( const Name& );
122  static size_t getInstancesCount ( Cell*, unsigned int flags );
123  // Hurricane Managment.
124  void toJson ( JsonWriter* ) const;
125  inline string _getTypeName () const;
126  string _getString () const;
127  Record* _getRecord () const;
128 
129  // Internals - Attributes.
130  protected:
131  static const Name _parentLibraryName;
132  static AllianceFramework* _singleton;
133  Observable _observers;
134  Environment _environment;
135  ParsersMap _parsers;
136  DriversMap _drivers;
137  Catalog _catalog;
138  AllianceLibraries _libraries;
139  Library* _parentLibrary;
140  map<Name,RoutingGauge*> _routingGauges;
141  RoutingGauge* _defaultRoutingGauge;
142  map<Name,CellGauge*> _cellGauges;
143  CellGauge* _defaultCellGauge;
144 
145  // Internals - Constructors.
146  AllianceFramework ();
147  AllianceFramework ( const AllianceFramework& );
148  AllianceFramework& operator= ( const AllianceFramework& );
149  // Internals - Destructors.
150  ~AllianceFramework ();
151  // Internals - Methods.
152  bool _readLocate ( const string& file, unsigned int mode, bool isLib=false );
153  bool _writeLocate ( const string& file, unsigned int mode, bool isLib=false );
154  AllianceLibrary* _createLibrary ( const string& path, bool& hasCatalog );
155  void _bindLibraries ();
156  };
157 
158  inline bool AllianceFramework::isPOWER ( const char* name ) { return _environment.isPOWER(name); }
159  inline bool AllianceFramework::isPOWER ( const string& name ) { return isPOWER(name.c_str()); }
160  inline bool AllianceFramework::isPOWER ( const Name& name ) { return isPOWER(getString(name)); }
161  inline bool AllianceFramework::isGROUND ( const char* name ) { return _environment.isGROUND(name); }
162  inline bool AllianceFramework::isGROUND ( const string& name ) { return isGROUND(name.c_str()); }
163  inline bool AllianceFramework::isGROUND ( const Name& name ) { return isGROUND(getString(name)); }
164  inline bool AllianceFramework::isCLOCK ( const char* name ) { return _environment.isCLOCK(name); }
165  inline bool AllianceFramework::isCLOCK ( const string& name ) { return isCLOCK(name.c_str()); }
166  inline bool AllianceFramework::isCLOCK ( const Name& name ) { return isCLOCK(getString(name)); }
167  inline bool AllianceFramework::isBLOCKAGE ( const char* name ) { return _environment.isBLOCKAGE(name); }
168  inline bool AllianceFramework::isBLOCKAGE ( const string& name ) { return isBLOCKAGE(name.c_str()); }
169  inline bool AllianceFramework::isBLOCKAGE ( const Name& name ) { return isBLOCKAGE(getString(name)); }
170  inline bool AllianceFramework::isBLOCKAGE ( const Net* net ) { return isBLOCKAGE(net->getName()); }
171  inline bool AllianceFramework::isPad ( const char* name ) { return _environment.isPad(name); }
172  inline bool AllianceFramework::isPad ( const string& name ) { return isPad(name.c_str()); }
173  inline bool AllianceFramework::isPad ( const Name& name ) { return isPad(getString(name)); }
174  inline bool AllianceFramework::isPad ( const Cell* cell ) { return isPad(cell->getName()); }
175  inline Environment* AllianceFramework::getEnvironment () { return &_environment; }
176  inline Catalog* AllianceFramework::getCatalog () { return &_catalog; }
177  inline const Name& AllianceFramework::getParentLibraryName
178  () const { return _parentLibraryName; }
179  inline Library* AllianceFramework::getParentLibrary () { return _parentLibrary; }
180  inline const AllianceLibraries&
181  AllianceFramework::getAllianceLibraries () const { return _libraries; }
182 // TEMPORARY.
183  inline const Name AllianceFramework::getDefaultCGPinLayerName
184  () const { return "CALU1"; }
185  inline string AllianceFramework::_getTypeName () const { return "AllianceFramework"; }
186 
187 
188  class JsonAllianceFramework : public JsonObject {
189  public:
190  static void initialize ();
191  JsonAllianceFramework( unsigned long );
192  virtual ~JsonAllianceFramework();
193  virtual string getTypeName () const;
194  virtual JsonAllianceFramework* clone ( unsigned long ) const;
195  virtual void toData ( JsonStack& );
196  private:
197  std::string _defaultRoutingGauge;
198  std::string _defaultCellGauge;
199  };
200 
201 
202 } // CRL namespace.
203 
204 
205 INSPECTOR_P_SUPPORT(CRL::AllianceFramework);
206 
207 #endif // CRL_ALLIANCE_FRAMEWORK_H
CRL::Environment::isBLOCKAGE
bool isBLOCKAGE(const char *name) const
+
CRL::AllianceFramework::getParentLibrary
Library * getParentLibrary()
Definition: AllianceFramework.h:179
CRL::Environment::isCLOCK
bool isCLOCK(const char *name) const
-
CRL::AllianceFramework
A Framework to work with Alliance formats.
Definition: AllianceFramework.h:41
-
CRL::AllianceFramework::getDefaultCGPinLayerName
const Name getDefaultCGPinLayerName() const
Definition: AllianceFramework.h:181
+
CRL::AllianceFramework
A Framework to work with Alliance formats.
Definition: AllianceFramework.h:42
+
CRL::AllianceFramework::getDefaultCGPinLayerName
const Name getDefaultCGPinLayerName() const
Definition: AllianceFramework.h:184
CRL::Environment::isPOWER
bool isPOWER(const char *name) const
CRL::AllianceFramework::addCellGauge
void addCellGauge(CellGauge *)
-
CRL::AllianceFramework::InstancesCountFlags
InstancesCountFlags
Definition: AllianceFramework.h:46
+
CRL::AllianceFramework::InstancesCountFlags
InstancesCountFlags
Definition: AllianceFramework.h:47
CRL::AllianceFramework::getInstancesCount
static size_t getInstancesCount(Cell *, unsigned int flags)
+
Hurricane::DbU::Unit
std::int64_t Unit
CRL::AllianceFramework::saveCell
void saveCell(Cell *, unsigned int mode)
CRL::AllianceFramework::createLibrary
AllianceLibrary * createLibrary(const string &path, unsigned int flags, string libName="")
-
CRL::AllianceFramework::LibraryFlags
LibraryFlags
Definition: AllianceFramework.h:49
+
CRL::AllianceFramework::LibraryFlags
LibraryFlags
Definition: AllianceFramework.h:50
CRL::Environment::isPad
bool isPad(const char *name) const
CRL::Environment::isGROUND
bool isGROUND(const char *name) const
-
CRL::AllianceFramework::Recursive
Definition: AllianceFramework.h:46
+
CRL::AllianceFramework::Recursive
Definition: AllianceFramework.h:47
CRL::AllianceFramework::getLibrary
Library * getLibrary(unsigned int index)
-
CRL::AllianceFramework::getParentLibraryName
const Name & getParentLibraryName() const
Definition: AllianceFramework.h:175
+
CRL::AllianceFramework::getParentLibraryName
const Name & getParentLibraryName() const
Definition: AllianceFramework.h:178
+
CRL::AllianceFramework::addRoutingGauge
void addRoutingGauge(RoutingGauge *)
-
CRL::AllianceFramework::CreateLibrary
Definition: AllianceFramework.h:49
+
CRL::AllianceFramework::CreateLibrary
Definition: AllianceFramework.h:50
CRL::AllianceFramework::loadLibraryCells
unsigned int loadLibraryCells(Library *)
CRL::AllianceFramework::createCell
Cell * createCell(const string &name, AllianceLibrary *library=NULL)
-
CRL::AllianceFramework::getCatalog
Catalog * getCatalog()
Definition: AllianceFramework.h:173
-
CRL::AllianceFramework::IgnoreFeeds
Definition: AllianceFramework.h:47
+
CRL::AllianceFramework::getCatalog
Catalog * getCatalog()
Definition: AllianceFramework.h:176
+
CRL::AllianceFramework::IgnoreFeeds
Definition: AllianceFramework.h:48
CRL::AllianceFramework::getRoutingGauge
RoutingGauge * getRoutingGauge(const Name &name="")
CRL::Catalog
A Registry to store Alliance Cell metadatas.
Definition: Catalog.h:56
CRL::AllianceFramework::getAllianceLibrary
AllianceLibrary * getAllianceLibrary(unsigned int index)
-
CRL::AllianceFramework::HasCatalog
Definition: AllianceFramework.h:51
+
CRL::AllianceFramework::HasCatalog
Definition: AllianceFramework.h:52
CRL::Environment
Holds all the Alliance environment variables.
Definition: Environment.h:35
-
CRL::AllianceFramework::getEnvironment
Environment * getEnvironment()
Definition: AllianceFramework.h:172
+
CRL::AllianceFramework::getEnvironment
Environment * getEnvironment()
Definition: AllianceFramework.h:175
CRL::AllianceFramework::getPrint
string getPrint() const
CRL::AllianceFramework::saveLibrary
void saveLibrary(Library *)
CRL::AllianceFramework::getCell
Cell * getCell(const string &name, unsigned int mode, unsigned int depth=(unsigned int) -1)
@@ -90,7 +92,7 @@ $(function() {
- +
Generated by doxygen 1.8.14 on Thu Oct 18 2018Generated by doxygen 1.8.14 on Sun May 26 2019 Return to top of page
diff --git a/crlcore/doc/crlcore/html/AllianceLibrary_8h_source.html b/crlcore/doc/crlcore/html/AllianceLibrary_8h_source.html index bec4924a..35b6f5a1 100644 --- a/crlcore/doc/crlcore/html/AllianceLibrary_8h_source.html +++ b/crlcore/doc/crlcore/html/AllianceLibrary_8h_source.html @@ -59,7 +59,7 @@ $(function() {
- +
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diff --git a/crlcore/doc/crlcore/html/Banner_8h_source.html b/crlcore/doc/crlcore/html/Banner_8h_source.html index 68d6192d..887fc730 100644 --- a/crlcore/doc/crlcore/html/Banner_8h_source.html +++ b/crlcore/doc/crlcore/html/Banner_8h_source.html @@ -66,7 +66,7 @@ $(function() {
- +
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diff --git a/crlcore/doc/crlcore/html/Catalog_8h_source.html b/crlcore/doc/crlcore/html/Catalog_8h_source.html index 222c436a..3424e139 100644 --- a/crlcore/doc/crlcore/html/Catalog_8h_source.html +++ b/crlcore/doc/crlcore/html/Catalog_8h_source.html @@ -123,7 +123,7 @@ $(function() {
- +
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diff --git a/crlcore/doc/crlcore/html/Environment_8h_source.html b/crlcore/doc/crlcore/html/Environment_8h_source.html index aae11660..4d0bf20b 100644 --- a/crlcore/doc/crlcore/html/Environment_8h_source.html +++ b/crlcore/doc/crlcore/html/Environment_8h_source.html @@ -99,7 +99,7 @@ $(function() {
- +
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diff --git a/crlcore/doc/crlcore/html/GraphicToolEngine_8h_source.html b/crlcore/doc/crlcore/html/GraphicToolEngine_8h_source.html index e6a3b757..1f0ae5fc 100644 --- a/crlcore/doc/crlcore/html/GraphicToolEngine_8h_source.html +++ b/crlcore/doc/crlcore/html/GraphicToolEngine_8h_source.html @@ -60,7 +60,7 @@ $(function() {
- +
Generated by doxygen 1.8.14 on Thu Oct 18 2018Generated by doxygen 1.8.14 on Sun May 26 2019 Return to top of page
diff --git a/crlcore/doc/crlcore/html/RoutingGauge_8h_source.html b/crlcore/doc/crlcore/html/RoutingGauge_8h_source.html index d344ac0c..8bfb8ed5 100644 --- a/crlcore/doc/crlcore/html/RoutingGauge_8h_source.html +++ b/crlcore/doc/crlcore/html/RoutingGauge_8h_source.html @@ -80,7 +80,7 @@ $(function() {
- +
Generated by doxygen 1.8.14 on Thu Oct 18 2018Generated by doxygen 1.8.14 on Sun May 26 2019 Return to top of page
diff --git a/crlcore/doc/crlcore/html/RoutingLayerGauge_8h_source.html b/crlcore/doc/crlcore/html/RoutingLayerGauge_8h_source.html index 0964fb6a..f7cc7a1d 100644 --- a/crlcore/doc/crlcore/html/RoutingLayerGauge_8h_source.html +++ b/crlcore/doc/crlcore/html/RoutingLayerGauge_8h_source.html @@ -44,13 +44,13 @@ $(function() {
RoutingLayerGauge.h
-
1 // -*- C++ -*-
2 //
3 // This file is part of the Coriolis Software.
4 // Copyright (c) UPMC 2008-2018, All Rights Reserved
5 //
6 // +-----------------------------------------------------------------+
7 // | C O R I O L I S |
8 // | C o r e L i b r a r y |
9 // | |
10 // | Author : Jean-Paul CHAPUT |
11 // | E-mail : Jean-Paul.Chaput@asim.lip6.fr |
12 // | =============================================================== |
13 // | C++ Header : "./RoutingLayerGauge.h" |
14 // +-----------------------------------------------------------------+
15 
16 
17 #ifndef CRL_ROUTING_LAYER_GAUGE_H
18 #define CRL_ROUTING_LAYER_GAUGE_H
19 
20 
21 #include <map>
22 #include "hurricane/Commons.h"
23 #include "hurricane/Error.h"
24 #include "hurricane/DbU.h"
25 #include "hurricane/Collection.h"
26 #include "hurricane/Slot.h"
27 #include "crlcore/Utilities.h"
28 
29 namespace Hurricane {
30  class Layer;
31 }
32 
33 
34 namespace Constant {
35 
36  enum Direction { Horizontal = (1<<0)
37  , Vertical = (1<<1)
38  };
39 
40  enum LayerGaugeType { Default = (1<<0)
41  , PinOnly = (1<<1)
42  };
43 
44  enum Round { Superior = (1<<2)
45  , Inferior = (1<<3)
46  , Nearest = (1<<4)
47  , Exact = (1<<5)
48  };
49 
50  Direction perpandicular ( unsigned int );
51 
52 }
53 
54 
55 
56 namespace CRL {
57 
58  using std::map;
59  using Hurricane::JsonObject;
60  using Hurricane::JsonStack;
61  using Hurricane::Initializer;
62  using Hurricane::GenericCollection;
63  using Hurricane::GenericLocator;
64  using Hurricane::GenericFilter;
65  using Hurricane::Record;
66  using Hurricane::DbU;
67  using Hurricane::Layer;
68 
69 
70  class RoutingGauge;
71 
72 
73 // -------------------------------------------------------------------
74 // Class : "RoutingLayerGauge".
75 
76 
77  class RoutingLayerGauge {
78 
79  public:
80  // Constructors & Destructors.
81  static RoutingLayerGauge* create ( const Layer* layer
82  , Constant::Direction direction
83  , Constant::LayerGaugeType type
84  , unsigned int depth
85  , double density
86  , DbU::Unit offset
87  , DbU::Unit pitch
88  , DbU::Unit wireWidth
89  , DbU::Unit viaWidth
90  , DbU::Unit obsDw );
91  virtual void destroy ();
92  // Accessors.
93  inline bool isHorizontal () const;
94  inline bool isVertical () const;
95  inline const Layer* getLayer () const;
96  inline const Layer* getBlockageLayer () const;
97  inline unsigned int getDepth () const;
98  inline Constant::Direction getDirection () const;
99  inline Constant::LayerGaugeType getType () const;
100  inline double getDensity () const;
101  inline DbU::Unit getOffset () const;
102  inline DbU::Unit getPitch () const;
103  inline DbU::Unit getHalfPitch () const;
104  inline DbU::Unit getWireWidth () const;
105  inline DbU::Unit getHalfWireWidth () const;
106  inline DbU::Unit getViaWidth () const;
107  inline DbU::Unit getHalfViaWidth () const;
108  inline DbU::Unit getObstacleDw () const;
109  void divide ( DbU::Unit dividend, long& quotient, long& modulo ) const;
110  unsigned int getTrackNumber ( DbU::Unit start, DbU::Unit stop ) const;
111  unsigned int getTrackIndex ( DbU::Unit start, DbU::Unit stop, DbU::Unit position, unsigned mode ) const;
112  inline DbU::Unit getTrackPosition ( DbU::Unit start, DbU::Unit stop, DbU::Unit position, unsigned mode ) const;
113  DbU::Unit getTrackPosition ( DbU::Unit start, unsigned depth ) const;
114  // Hurricane Managment.
115  void toJson ( JsonWriter* ) const;
116  virtual string _getTypeName () const;
117  virtual string _getString () const;
118  virtual Record* _getRecord () const;
119 
120  protected:
121  // Internal - Attributes.
122  const Layer* _layer;
123  const Layer* _blockageLayer;
124  Constant::Direction _direction;
125  Constant::LayerGaugeType _type;
126  unsigned int _depth;
127  double _density;
128  DbU::Unit _offset;
129  DbU::Unit _pitch;
130  DbU::Unit _wireWidth;
131  DbU::Unit _viaWidth;
132  DbU::Unit _obstacleDw;
133 
134  // Internal - Constructors & Destructors.
135  RoutingLayerGauge ( const Layer* layer
136  , Constant::Direction direction
137  , Constant::LayerGaugeType type
138  , unsigned int depth
139  , double density
140  , DbU::Unit offset
141  , DbU::Unit pitch
142  , DbU::Unit wireWidth
143  , DbU::Unit viaWidth
144  , DbU::Unit obsDw );
145  virtual ~RoutingLayerGauge ();
146  virtual void _preDestroy();
147  RoutingLayerGauge& operator= ( const RoutingLayerGauge& );
148 
149  // Friends.
150  friend class RoutingGauge;
151  };
152 
153 
154  // New Types.
155  typedef map<Layer*,RoutingLayerGauge*> RoutingLayerGaugeMap;
156 
157 
158 // -------------------------------------------------------------------
159 // Collection : "RoutingLayerGauges".
160 
161  typedef GenericCollection<RoutingLayerGauge*> RoutingLayerGauges;
162  typedef GenericLocator<RoutingLayerGauge*> RoutingLayerGaugeLocator;
163  typedef GenericFilter<RoutingLayerGauge*> RoutingLayerGaugeFilter;
164 
165 
166 // -------------------------------------------------------------------
167 // Inline Functions.
168 
169  inline bool RoutingLayerGauge::isHorizontal () const { return (_direction == Constant::Direction::Horizontal); }
170  inline bool RoutingLayerGauge::isVertical () const { return (_direction == Constant::Direction::Vertical); }
171  inline const Layer* RoutingLayerGauge::getLayer () const { return _layer; }
172  inline const Layer* RoutingLayerGauge::getBlockageLayer () const { return _blockageLayer; }
173  inline Constant::Direction RoutingLayerGauge::getDirection () const { return _direction; }
174  inline Constant::LayerGaugeType RoutingLayerGauge::getType () const { return _type; }
175  inline unsigned int RoutingLayerGauge::getDepth () const { return _depth; }
176  inline double RoutingLayerGauge::getDensity () const { return _density; }
177  inline DbU::Unit RoutingLayerGauge::getOffset () const { return _offset; }
178  inline DbU::Unit RoutingLayerGauge::getPitch () const { return _pitch; }
179  inline DbU::Unit RoutingLayerGauge::getHalfPitch () const { return _pitch>>1; }
180  inline DbU::Unit RoutingLayerGauge::getWireWidth () const { return _wireWidth; }
181  inline DbU::Unit RoutingLayerGauge::getHalfWireWidth () const { return _wireWidth>>1; }
182  inline DbU::Unit RoutingLayerGauge::getViaWidth () const { return _viaWidth; }
183  inline DbU::Unit RoutingLayerGauge::getHalfViaWidth () const { return _viaWidth>>1; }
184  inline DbU::Unit RoutingLayerGauge::getObstacleDw () const { return _obstacleDw; }
185  inline DbU::Unit RoutingLayerGauge::getTrackPosition ( DbU::Unit start, DbU::Unit stop, DbU::Unit position, unsigned mode ) const
186  { return getTrackPosition( start, getTrackIndex(start,stop,position,mode) ); }
187 
188 
189 // -------------------------------------------------------------------
190 // Class : "JsonRoutingLayerGauge".
191 
192  class JsonRoutingLayerGauge : public JsonObject {
193  public:
194  static void initialize ();
195  JsonRoutingLayerGauge ( unsigned long flags );
196  virtual string getTypeName () const;
197  virtual JsonRoutingLayerGauge* clone ( unsigned long flags ) const;
198  virtual void toData ( JsonStack& );
199  };
200 
201 
202 } // CRL namespace.
203 
204 
205 INSPECTOR_P_SUPPORT(CRL::RoutingLayerGauge);
206 
207 
208 // -------------------------------------------------------------------
209 // Inspector Support for : "const ::Constant::Direction*".
210 
211 
212 inline void from ( Constant::Direction& direction, const std::string& s )
213 {
214  if (s == "Vertical") direction = Constant::Vertical;
215  else {
216  if (s != "Horizontal")
217  std::cerr << Hurricane::Error( "::from(Direction&,string&): Unknown value \"%s\"."
218  , s.c_str() ) << std::endl;
219  direction = Constant::Horizontal;
220  }
221 }
222 
223 
224 template<>
225 inline std::string getString<const Constant::Direction*>
226  ( const Constant::Direction* direction )
227 {
228  switch ( *direction ) {
229  case Constant::Horizontal: return "Horizontal";
230  case Constant::Vertical: return "Vertical";
231  }
232  return "Unknown Constant::Direction";
233 }
234 
235 
236 template<>
237 inline std::string getString<Constant::Direction>
238  ( Constant::Direction direction )
239 {
240  switch ( direction ) {
241  case Constant::Horizontal: return "Horizontal";
242  case Constant::Vertical: return "Vertical";
243  }
244  return "Unknown Constant::Direction";
245 }
246 
247 
248 IOSTREAM_POINTER_SUPPORT(Constant::Direction);
249 
250 
251 // -------------------------------------------------------------------
252 // Inspector Support for : "const Constant::LayerGaugeType*".
253 
254 
255 inline void from ( Constant::LayerGaugeType& type, const std::string& s )
256 {
257  if (s == "PinOnly") type = Constant::PinOnly;
258  else {
259  if (s != "Default")
260  std::cerr << Hurricane::Error( "::from(LayerGaugeType&,string&): Unknown value \"%s\"."
261  , s.c_str() ) << std::endl;
262  type = Constant::Default;
263  }
264 }
265 
266 
267 template<>
268 inline std::string getString<const Constant::LayerGaugeType*>
269  ( const Constant::LayerGaugeType* layerGaugeType )
270 {
271  switch ( *layerGaugeType ) {
272  case Constant::Default: return "Default";
273  case Constant::PinOnly: return "PinOnly";
274  }
275  return "Unknown Constant::LayerGaugeType";
276 }
277 
278 
279 template<>
280 inline std::string getString<Constant::LayerGaugeType*>
281  ( Constant::LayerGaugeType* layerGaugeType )
282 { return getString<const Constant::LayerGaugeType*>(layerGaugeType); }
283 
284 
285 template<>
286 inline std::string getString<const Constant::LayerGaugeType>
287  ( const Constant::LayerGaugeType layerGaugeType )
288 {
289  switch ( layerGaugeType ) {
290  case Constant::Default: return "Default";
291  case Constant::PinOnly: return "PinOnly";
292  }
293  return "Unknown Constant::LayerGaugeType";
294 }
295 
296 
297 template<>
298 inline std::string getString<Constant::LayerGaugeType>
299  ( Constant::LayerGaugeType layerGaugeType )
300 { return getString<const Constant::LayerGaugeType>(layerGaugeType); }
301 
302 
303 IOSTREAM_POINTER_SUPPORT(Constant::LayerGaugeType);
304 
305 
306 #endif // CRL_ROUTING_LAYER_GAUGE_H
Constant
Store various constants.
Definition: RoutingLayerGauge.h:34
+
1 // -*- C++ -*-
2 //
3 // This file is part of the Coriolis Software.
4 // Copyright (c) UPMC 2008-2018, All Rights Reserved
5 //
6 // +-----------------------------------------------------------------+
7 // | C O R I O L I S |
8 // | C o r e L i b r a r y |
9 // | |
10 // | Author : Jean-Paul CHAPUT |
11 // | E-mail : Jean-Paul.Chaput@asim.lip6.fr |
12 // | =============================================================== |
13 // | C++ Header : "./RoutingLayerGauge.h" |
14 // +-----------------------------------------------------------------+
15 
16 
17 #ifndef CRL_ROUTING_LAYER_GAUGE_H
18 #define CRL_ROUTING_LAYER_GAUGE_H
19 
20 
21 #include <map>
22 #include "hurricane/Commons.h"
23 #include "hurricane/Error.h"
24 #include "hurricane/DbU.h"
25 #include "hurricane/Collection.h"
26 #include "hurricane/Slot.h"
27 #include "crlcore/Utilities.h"
28 
29 namespace Hurricane {
30  class Layer;
31 }
32 
33 
34 namespace Constant {
35 
36  enum Direction { Horizontal = (1<<0)
37  , Vertical = (1<<1)
38  };
39 
40  enum LayerGaugeType { Default = (1<<0)
41  , PinOnly = (1<<1)
42  };
43 
44  enum Round { Superior = (1<<2)
45  , Inferior = (1<<3)
46  , Nearest = (1<<4)
47  , Exact = (1<<5)
48  };
49 
50  Direction perpandicular ( unsigned int );
51 
52 }
53 
54 
55 
56 namespace CRL {
57 
58  using std::map;
59  using Hurricane::JsonObject;
60  using Hurricane::JsonStack;
61  using Hurricane::Initializer;
62  using Hurricane::GenericCollection;
63  using Hurricane::GenericLocator;
64  using Hurricane::GenericFilter;
65  using Hurricane::Record;
66  using Hurricane::DbU;
67  using Hurricane::Layer;
68 
69 
70  class RoutingGauge;
71 
72 
73 // -------------------------------------------------------------------
74 // Class : "RoutingLayerGauge".
75 
76 
77  class RoutingLayerGauge {
78 
79  public:
80  // Constructors & Destructors.
81  static RoutingLayerGauge* create ( const Layer* layer
82  , Constant::Direction direction
83  , Constant::LayerGaugeType type
84  , unsigned int depth
85  , double density
86  , DbU::Unit offset
87  , DbU::Unit pitch
88  , DbU::Unit wireWidth
89  , DbU::Unit viaWidth
90  , DbU::Unit obsDw );
91  virtual void destroy ();
92  // Accessors.
93  inline bool isHorizontal () const;
94  inline bool isVertical () const;
95  inline const Layer* getLayer () const;
96  inline const Layer* getBlockageLayer () const;
97  inline unsigned int getDepth () const;
98  inline Constant::Direction getDirection () const;
99  inline Constant::LayerGaugeType getType () const;
100  inline double getDensity () const;
101  inline DbU::Unit getOffset () const;
102  inline DbU::Unit getPitch () const;
103  inline DbU::Unit getHalfPitch () const;
104  inline DbU::Unit getWireWidth () const;
105  inline DbU::Unit getHalfWireWidth () const;
106  inline DbU::Unit getViaWidth () const;
107  inline DbU::Unit getHalfViaWidth () const;
108  inline DbU::Unit getObstacleDw () const;
109  void divide ( DbU::Unit dividend, long& quotient, long& modulo ) const;
110  unsigned int getTrackNumber ( DbU::Unit start, DbU::Unit stop ) const;
111  long getTrackIndex ( DbU::Unit start, DbU::Unit stop, DbU::Unit position, unsigned mode ) const;
112  inline DbU::Unit getTrackPosition ( DbU::Unit start, DbU::Unit stop, DbU::Unit position, unsigned mode ) const;
113  DbU::Unit getTrackPosition ( DbU::Unit start, long index ) const;
114  // Hurricane Managment.
115  void toJson ( JsonWriter* ) const;
116  virtual string _getTypeName () const;
117  virtual string _getString () const;
118  virtual Record* _getRecord () const;
119 
120  protected:
121  // Internal - Attributes.
122  const Layer* _layer;
123  const Layer* _blockageLayer;
124  Constant::Direction _direction;
125  Constant::LayerGaugeType _type;
126  unsigned int _depth;
127  double _density;
128  DbU::Unit _offset;
129  DbU::Unit _pitch;
130  DbU::Unit _wireWidth;
131  DbU::Unit _viaWidth;
132  DbU::Unit _obstacleDw;
133 
134  // Internal - Constructors & Destructors.
135  RoutingLayerGauge ( const Layer* layer
136  , Constant::Direction direction
137  , Constant::LayerGaugeType type
138  , unsigned int depth
139  , double density
140  , DbU::Unit offset
141  , DbU::Unit pitch
142  , DbU::Unit wireWidth
143  , DbU::Unit viaWidth
144  , DbU::Unit obsDw );
145  virtual ~RoutingLayerGauge ();
146  virtual void _preDestroy();
147  RoutingLayerGauge& operator= ( const RoutingLayerGauge& );
148 
149  // Friends.
150  friend class RoutingGauge;
151  };
152 
153 
154  // New Types.
155  typedef map<Layer*,RoutingLayerGauge*> RoutingLayerGaugeMap;
156 
157 
158 // -------------------------------------------------------------------
159 // Collection : "RoutingLayerGauges".
160 
161  typedef GenericCollection<RoutingLayerGauge*> RoutingLayerGauges;
162  typedef GenericLocator<RoutingLayerGauge*> RoutingLayerGaugeLocator;
163  typedef GenericFilter<RoutingLayerGauge*> RoutingLayerGaugeFilter;
164 
165 
166 // -------------------------------------------------------------------
167 // Inline Functions.
168 
169  inline bool RoutingLayerGauge::isHorizontal () const { return (_direction == Constant::Direction::Horizontal); }
170  inline bool RoutingLayerGauge::isVertical () const { return (_direction == Constant::Direction::Vertical); }
171  inline const Layer* RoutingLayerGauge::getLayer () const { return _layer; }
172  inline const Layer* RoutingLayerGauge::getBlockageLayer () const { return _blockageLayer; }
173  inline Constant::Direction RoutingLayerGauge::getDirection () const { return _direction; }
174  inline Constant::LayerGaugeType RoutingLayerGauge::getType () const { return _type; }
175  inline unsigned int RoutingLayerGauge::getDepth () const { return _depth; }
176  inline double RoutingLayerGauge::getDensity () const { return _density; }
177  inline DbU::Unit RoutingLayerGauge::getOffset () const { return _offset; }
178  inline DbU::Unit RoutingLayerGauge::getPitch () const { return _pitch; }
179  inline DbU::Unit RoutingLayerGauge::getHalfPitch () const { return _pitch>>1; }
180  inline DbU::Unit RoutingLayerGauge::getWireWidth () const { return _wireWidth; }
181  inline DbU::Unit RoutingLayerGauge::getHalfWireWidth () const { return _wireWidth>>1; }
182  inline DbU::Unit RoutingLayerGauge::getViaWidth () const { return _viaWidth; }
183  inline DbU::Unit RoutingLayerGauge::getHalfViaWidth () const { return _viaWidth>>1; }
184  inline DbU::Unit RoutingLayerGauge::getObstacleDw () const { return _obstacleDw; }
185  inline DbU::Unit RoutingLayerGauge::getTrackPosition ( DbU::Unit start, DbU::Unit stop, DbU::Unit position, unsigned mode ) const
186  { return getTrackPosition( start, getTrackIndex(start,stop,position,mode) ); }
187 
188 
189 // -------------------------------------------------------------------
190 // Class : "JsonRoutingLayerGauge".
191 
192  class JsonRoutingLayerGauge : public JsonObject {
193  public:
194  static void initialize ();
195  JsonRoutingLayerGauge ( unsigned long flags );
196  virtual string getTypeName () const;
197  virtual JsonRoutingLayerGauge* clone ( unsigned long flags ) const;
198  virtual void toData ( JsonStack& );
199  };
200 
201 
202 } // CRL namespace.
203 
204 
205 INSPECTOR_P_SUPPORT(CRL::RoutingLayerGauge);
206 
207 
208 // -------------------------------------------------------------------
209 // Inspector Support for : "const ::Constant::Direction*".
210 
211 
212 inline void from ( Constant::Direction& direction, const std::string& s )
213 {
214  if (s == "Vertical") direction = Constant::Vertical;
215  else {
216  if (s != "Horizontal")
217  std::cerr << Hurricane::Error( "::from(Direction&,string&): Unknown value \"%s\"."
218  , s.c_str() ) << std::endl;
219  direction = Constant::Horizontal;
220  }
221 }
222 
223 
224 template<>
225 inline std::string getString<const Constant::Direction*>
226  ( const Constant::Direction* direction )
227 {
228  switch ( *direction ) {
229  case Constant::Horizontal: return "Horizontal";
230  case Constant::Vertical: return "Vertical";
231  }
232  return "Unknown Constant::Direction";
233 }
234 
235 
236 template<>
237 inline std::string getString<Constant::Direction>
238  ( Constant::Direction direction )
239 {
240  switch ( direction ) {
241  case Constant::Horizontal: return "Horizontal";
242  case Constant::Vertical: return "Vertical";
243  }
244  return "Unknown Constant::Direction";
245 }
246 
247 
248 IOSTREAM_POINTER_SUPPORT(Constant::Direction);
249 
250 
251 // -------------------------------------------------------------------
252 // Inspector Support for : "const Constant::LayerGaugeType*".
253 
254 
255 inline void from ( Constant::LayerGaugeType& type, const std::string& s )
256 {
257  if (s == "PinOnly") type = Constant::PinOnly;
258  else {
259  if (s != "Default")
260  std::cerr << Hurricane::Error( "::from(LayerGaugeType&,string&): Unknown value \"%s\"."
261  , s.c_str() ) << std::endl;
262  type = Constant::Default;
263  }
264 }
265 
266 
267 template<>
268 inline std::string getString<const Constant::LayerGaugeType*>
269  ( const Constant::LayerGaugeType* layerGaugeType )
270 {
271  switch ( *layerGaugeType ) {
272  case Constant::Default: return "Default";
273  case Constant::PinOnly: return "PinOnly";
274  }
275  return "Unknown Constant::LayerGaugeType";
276 }
277 
278 
279 template<>
280 inline std::string getString<Constant::LayerGaugeType*>
281  ( Constant::LayerGaugeType* layerGaugeType )
282 { return getString<const Constant::LayerGaugeType*>(layerGaugeType); }
283 
284 
285 template<>
286 inline std::string getString<const Constant::LayerGaugeType>
287  ( const Constant::LayerGaugeType layerGaugeType )
288 {
289  switch ( layerGaugeType ) {
290  case Constant::Default: return "Default";
291  case Constant::PinOnly: return "PinOnly";
292  }
293  return "Unknown Constant::LayerGaugeType";
294 }
295 
296 
297 template<>
298 inline std::string getString<Constant::LayerGaugeType>
299  ( Constant::LayerGaugeType layerGaugeType )
300 { return getString<const Constant::LayerGaugeType>(layerGaugeType); }
301 
302 
303 IOSTREAM_POINTER_SUPPORT(Constant::LayerGaugeType);
304 
305 
306 #endif // CRL_ROUTING_LAYER_GAUGE_H
Constant
Store various constants.
Definition: RoutingLayerGauge.h:34
CRL::RoutingLayerGauge::getViaWidth
DbU::Unit getViaWidth() const
Definition: RoutingLayerGauge.h:182
CRL::RoutingLayerGauge::destroy
virtual void destroy()
CRL::RoutingLayerGauge::getLayer
const Layer * getLayer() const
Definition: RoutingLayerGauge.h:171
Constant::Round
Round
Definition: RoutingLayerGauge.h:44
CRL::RoutingLayerGauge::getPitch
DbU::Unit getPitch() const
Definition: RoutingLayerGauge.h:178
-
CRL::RoutingLayerGauge::getTrackIndex
unsigned int getTrackIndex(DbU::Unit start, DbU::Unit stop, DbU::Unit position, unsigned mode) const
+
CRL::RoutingLayerGauge::getTrackIndex
long getTrackIndex(DbU::Unit start, DbU::Unit stop, DbU::Unit position, unsigned mode) const
@@ -93,7 +93,7 @@ $(function() {
- +
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diff --git a/crlcore/doc/crlcore/html/SearchPath_8h_source.html b/crlcore/doc/crlcore/html/SearchPath_8h_source.html index c6719954..57b9d045 100644 --- a/crlcore/doc/crlcore/html/SearchPath_8h_source.html +++ b/crlcore/doc/crlcore/html/SearchPath_8h_source.html @@ -68,7 +68,7 @@ $(function() {
- +
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diff --git a/crlcore/doc/crlcore/html/ToolEngine_8h_source.html b/crlcore/doc/crlcore/html/ToolEngine_8h_source.html index a5e8b2ac..3acb76d1 100644 --- a/crlcore/doc/crlcore/html/ToolEngine_8h_source.html +++ b/crlcore/doc/crlcore/html/ToolEngine_8h_source.html @@ -58,7 +58,7 @@ $(function() {
- +
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diff --git a/crlcore/doc/crlcore/html/ToolEngines_8h_source.html b/crlcore/doc/crlcore/html/ToolEngines_8h_source.html index 6e2d975c..d72d9ae0 100644 --- a/crlcore/doc/crlcore/html/ToolEngines_8h_source.html +++ b/crlcore/doc/crlcore/html/ToolEngines_8h_source.html @@ -57,7 +57,7 @@ $(function() {
- +
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diff --git a/crlcore/doc/crlcore/html/annotated.html b/crlcore/doc/crlcore/html/annotated.html index 50a90693..e8bd28c8 100644 --- a/crlcore/doc/crlcore/html/annotated.html +++ b/crlcore/doc/crlcore/html/annotated.html @@ -64,7 +64,7 @@ $(function() {
- +
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diff --git a/crlcore/doc/crlcore/html/classCRL_1_1AcmSigda-members.html b/crlcore/doc/crlcore/html/classCRL_1_1AcmSigda-members.html index b270d2c5..b1f95183 100644 --- a/crlcore/doc/crlcore/html/classCRL_1_1AcmSigda-members.html +++ b/crlcore/doc/crlcore/html/classCRL_1_1AcmSigda-members.html @@ -53,7 +53,7 @@ $(function() {
- +
Generated by doxygen 1.8.14 on Thu Oct 18 2018Generated by doxygen 1.8.14 on Sun May 26 2019 Return to top of page
diff --git a/crlcore/doc/crlcore/html/classCRL_1_1AcmSigda.html b/crlcore/doc/crlcore/html/classCRL_1_1AcmSigda.html index 463c49b8..8b60c414 100644 --- a/crlcore/doc/crlcore/html/classCRL_1_1AcmSigda.html +++ b/crlcore/doc/crlcore/html/classCRL_1_1AcmSigda.html @@ -118,7 +118,7 @@ Static Public Member Functions
- +
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diff --git a/crlcore/doc/crlcore/html/classCRL_1_1AllianceFramework-members.html b/crlcore/doc/crlcore/html/classCRL_1_1AllianceFramework-members.html index 0f8821cc..f607bfe0 100644 --- a/crlcore/doc/crlcore/html/classCRL_1_1AllianceFramework-members.html +++ b/crlcore/doc/crlcore/html/classCRL_1_1AllianceFramework-members.html @@ -87,7 +87,7 @@ $(function() {
- +
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diff --git a/crlcore/doc/crlcore/html/classCRL_1_1AllianceFramework.html b/crlcore/doc/crlcore/html/classCRL_1_1AllianceFramework.html index ba419e34..29b61911 100644 --- a/crlcore/doc/crlcore/html/classCRL_1_1AllianceFramework.html +++ b/crlcore/doc/crlcore/html/classCRL_1_1AllianceFramework.html @@ -923,7 +923,7 @@ Static Public Member Functions
- +
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diff --git a/crlcore/doc/crlcore/html/classCRL_1_1AllianceLibrary-members.html b/crlcore/doc/crlcore/html/classCRL_1_1AllianceLibrary-members.html index d7a7ca4b..3546c9a8 100644 --- a/crlcore/doc/crlcore/html/classCRL_1_1AllianceLibrary-members.html +++ b/crlcore/doc/crlcore/html/classCRL_1_1AllianceLibrary-members.html @@ -56,7 +56,7 @@ $(function() {
- +
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diff --git a/crlcore/doc/crlcore/html/classCRL_1_1AllianceLibrary.html b/crlcore/doc/crlcore/html/classCRL_1_1AllianceLibrary.html index abafaa29..59f87d75 100644 --- a/crlcore/doc/crlcore/html/classCRL_1_1AllianceLibrary.html +++ b/crlcore/doc/crlcore/html/classCRL_1_1AllianceLibrary.html @@ -175,7 +175,7 @@ Public Member Functions
- +
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diff --git a/crlcore/doc/crlcore/html/classCRL_1_1Banner-members.html b/crlcore/doc/crlcore/html/classCRL_1_1Banner-members.html index c3324927..5094698f 100644 --- a/crlcore/doc/crlcore/html/classCRL_1_1Banner-members.html +++ b/crlcore/doc/crlcore/html/classCRL_1_1Banner-members.html @@ -67,7 +67,7 @@ $(function() {
- +
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diff --git a/crlcore/doc/crlcore/html/classCRL_1_1Banner.html b/crlcore/doc/crlcore/html/classCRL_1_1Banner.html index a5065e46..7d03cf2d 100644 --- a/crlcore/doc/crlcore/html/classCRL_1_1Banner.html +++ b/crlcore/doc/crlcore/html/classCRL_1_1Banner.html @@ -495,7 +495,7 @@ Public Member Functions
- +
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diff --git a/crlcore/doc/crlcore/html/classCRL_1_1Catalog-members.html b/crlcore/doc/crlcore/html/classCRL_1_1Catalog-members.html index d71b0723..0ae4eabe 100644 --- a/crlcore/doc/crlcore/html/classCRL_1_1Catalog-members.html +++ b/crlcore/doc/crlcore/html/classCRL_1_1Catalog-members.html @@ -60,7 +60,7 @@ $(function() {
- +
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diff --git a/crlcore/doc/crlcore/html/classCRL_1_1Catalog.html b/crlcore/doc/crlcore/html/classCRL_1_1Catalog.html index dd4713ad..09b1a837 100644 --- a/crlcore/doc/crlcore/html/classCRL_1_1Catalog.html +++ b/crlcore/doc/crlcore/html/classCRL_1_1Catalog.html @@ -292,7 +292,7 @@ Public Member Functions
- +
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diff --git a/crlcore/doc/crlcore/html/classCRL_1_1CatalogExtension-members.html b/crlcore/doc/crlcore/html/classCRL_1_1CatalogExtension-members.html index 2255224e..8251818e 100644 --- a/crlcore/doc/crlcore/html/classCRL_1_1CatalogExtension-members.html +++ b/crlcore/doc/crlcore/html/classCRL_1_1CatalogExtension-members.html @@ -71,7 +71,7 @@ $(function() {
- +
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diff --git a/crlcore/doc/crlcore/html/classCRL_1_1CatalogExtension.html b/crlcore/doc/crlcore/html/classCRL_1_1CatalogExtension.html index 9ecc38fd..10aa49f5 100644 --- a/crlcore/doc/crlcore/html/classCRL_1_1CatalogExtension.html +++ b/crlcore/doc/crlcore/html/classCRL_1_1CatalogExtension.html @@ -763,7 +763,7 @@ Static Public Member Functions
- +
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diff --git a/crlcore/doc/crlcore/html/classCRL_1_1Catalog_1_1State-members.html b/crlcore/doc/crlcore/html/classCRL_1_1Catalog_1_1State-members.html index e58b7047..ee5b4bb6 100644 --- a/crlcore/doc/crlcore/html/classCRL_1_1Catalog_1_1State-members.html +++ b/crlcore/doc/crlcore/html/classCRL_1_1Catalog_1_1State-members.html @@ -86,7 +86,7 @@ $(function() {
- +
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diff --git a/crlcore/doc/crlcore/html/classCRL_1_1Catalog_1_1State.html b/crlcore/doc/crlcore/html/classCRL_1_1Catalog_1_1State.html index 1120f645..a3ae5d8b 100644 --- a/crlcore/doc/crlcore/html/classCRL_1_1Catalog_1_1State.html +++ b/crlcore/doc/crlcore/html/classCRL_1_1Catalog_1_1State.html @@ -846,7 +846,7 @@ Public Member Functions
- +
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diff --git a/crlcore/doc/crlcore/html/classCRL_1_1Environment-members.html b/crlcore/doc/crlcore/html/classCRL_1_1Environment-members.html index dca15fb5..f0de0a26 100644 --- a/crlcore/doc/crlcore/html/classCRL_1_1Environment-members.html +++ b/crlcore/doc/crlcore/html/classCRL_1_1Environment-members.html @@ -96,7 +96,7 @@ $(function() {
- +
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diff --git a/crlcore/doc/crlcore/html/classCRL_1_1Environment.html b/crlcore/doc/crlcore/html/classCRL_1_1Environment.html index 0b6e794c..82d4228a 100644 --- a/crlcore/doc/crlcore/html/classCRL_1_1Environment.html +++ b/crlcore/doc/crlcore/html/classCRL_1_1Environment.html @@ -1146,7 +1146,7 @@ Public Member Functions
- +
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diff --git a/crlcore/doc/crlcore/html/classCRL_1_1GraphicTool-members.html b/crlcore/doc/crlcore/html/classCRL_1_1GraphicTool-members.html index 2cbfefe9..7d25aae5 100644 --- a/crlcore/doc/crlcore/html/classCRL_1_1GraphicTool-members.html +++ b/crlcore/doc/crlcore/html/classCRL_1_1GraphicTool-members.html @@ -54,7 +54,7 @@ $(function() {
- +
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diff --git a/crlcore/doc/crlcore/html/classCRL_1_1GraphicTool.html b/crlcore/doc/crlcore/html/classCRL_1_1GraphicTool.html index c4306483..99b5c4ec 100644 --- a/crlcore/doc/crlcore/html/classCRL_1_1GraphicTool.html +++ b/crlcore/doc/crlcore/html/classCRL_1_1GraphicTool.html @@ -127,7 +127,7 @@ Public Member Functions
- +
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diff --git a/crlcore/doc/crlcore/html/classCRL_1_1RoutingGauge-members.html b/crlcore/doc/crlcore/html/classCRL_1_1RoutingGauge-members.html index 428e6c74..c34529aa 100644 --- a/crlcore/doc/crlcore/html/classCRL_1_1RoutingGauge-members.html +++ b/crlcore/doc/crlcore/html/classCRL_1_1RoutingGauge-members.html @@ -68,7 +68,7 @@ $(function() {
- +
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diff --git a/crlcore/doc/crlcore/html/classCRL_1_1RoutingGauge.html b/crlcore/doc/crlcore/html/classCRL_1_1RoutingGauge.html index 04d4e553..413272df 100644 --- a/crlcore/doc/crlcore/html/classCRL_1_1RoutingGauge.html +++ b/crlcore/doc/crlcore/html/classCRL_1_1RoutingGauge.html @@ -451,7 +451,7 @@ Static Public Member Functions
- +
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diff --git a/crlcore/doc/crlcore/html/classCRL_1_1RoutingLayerGauge-members.html b/crlcore/doc/crlcore/html/classCRL_1_1RoutingLayerGauge-members.html index b76ba7a3..394e8a53 100644 --- a/crlcore/doc/crlcore/html/classCRL_1_1RoutingLayerGauge-members.html +++ b/crlcore/doc/crlcore/html/classCRL_1_1RoutingLayerGauge-members.html @@ -62,16 +62,15 @@ $(function() { getPitch() constCRL::RoutingLayerGaugeinline getTrackIndex(DbU::Unit start, DbU::Unit stop, DbU::Unit position, unsigned mode) constCRL::RoutingLayerGauge getTrackNumber(DbU::Unit start, DbU::Unit stop) constCRL::RoutingLayerGauge - getTrackPosition(DbU::Unit start, unsigned depth) constCRL::RoutingLayerGauge - getType() constCRL::RoutingLayerGaugeinline - getViaWidth() constCRL::RoutingLayerGaugeinline - getWireWidth() constCRL::RoutingLayerGaugeinline + getType() constCRL::RoutingLayerGaugeinline + getViaWidth() constCRL::RoutingLayerGaugeinline + getWireWidth() constCRL::RoutingLayerGaugeinline

- +
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diff --git a/crlcore/doc/crlcore/html/classCRL_1_1RoutingLayerGauge.html b/crlcore/doc/crlcore/html/classCRL_1_1RoutingLayerGauge.html index 1a4eaba7..a1b499a6 100644 --- a/crlcore/doc/crlcore/html/classCRL_1_1RoutingLayerGauge.html +++ b/crlcore/doc/crlcore/html/classCRL_1_1RoutingLayerGauge.html @@ -86,10 +86,8 @@ Public Member Functions   unsigned int getTrackNumber (DbU::Unit start, DbU::Unit stop) const   -unsigned int getTrackIndex (DbU::Unit start, DbU::Unit stop, DbU::Unit position, unsigned mode) const +long getTrackIndex (DbU::Unit start, DbU::Unit stop, DbU::Unit position, unsigned mode) const   -DbU::Unit getTrackPosition (DbU::Unit start, unsigned depth) const -  @@ -673,35 +671,6 @@ Static Public Member Functions

Returns: the index of the track nearest position position in interval [start:stop], according the rounding mode.

-
- - -

◆ getTrackPosition()

- -
-
-

Static Public Member Functions

- - - - - - - - - - - - - - - - - -
DbU::Unit CRL::RoutingLayerGauge::getTrackPosition (DbU::Unit start,
unsigned depth 
) const
-
-

Returns: the position of the track number depth (with first track at start).

-
The documentation for this class was generated from the following files: +
  • Complete Design Flow & Examples
  • Installation
  • 2. Setting up the Environment
    • +
  • Complete Design Flow & Examples
  • Installation
  • 2. Setting up the Environment
    • +
  • Complete Design Flow & Examples
  • Installation
    • -
  • Knik – Global Router
    • -
  • Kite – Detailed Router
    • +
  • Complete Design Flow & Examples
  • Installation
  • 2. Setting up the Environment
    • +
  • Complete Design Flow & Examples
  • Installation
  • 2. Setting up the Environment
    • @@ -523,7 +533,7 @@ available here: Generated by Sphinx - using a RTD theme on Mar 04, 2019. + using a RTD theme on May 27, 2019. diff --git a/documentation/_build/html/Katabatic/Katabatic.html b/documentation/_build/html/Katabatic/Katabatic.html index 17d1bab3..cd84e8e1 100644 --- a/documentation/_build/html/Katabatic/Katabatic.html +++ b/documentation/_build/html/Katabatic/Katabatic.html @@ -83,13 +83,18 @@
  • Release 1.0.2049
  • Release v2.0.1
  • Release v2.1
    • -
  • Release v2.2
    • +
  • Release v2.2
    • +
  • Release v2.3
    • +
  • Complete Design Flow & Examples
  • Installation
  • 2. Setting up the Environment
    • +
  • Complete Design Flow & Examples
  • Installation
  • 2. Setting up the Environment
    • +
  • Complete Design Flow & Examples
  • Installation
  • 2. Setting up the Environment
    • +
  • Complete Design Flow & Examples
  • Installation
  • 2. Setting up the Environment
    • +
  • Complete Design Flow & Examples
  • Installation
  • 2. Setting up the Environment
    • +
  • Complete Design Flow & Examples
  • Installation
  • 2. Setting up the Environment
    • +
  • Complete Design Flow & Examples
  • Installation
  • 2. Setting up the Environment
    • +
  • Complete Design Flow & Examples
  • Installation
  • 2. Setting up the Environment
    • +
  • Complete Design Flow & Examples
  • Installation
  • 2. Setting up the Environment
    • +
  • Complete Design Flow & Examples
  • Installation
  • 2. Setting up the Environment
    • +
  • Complete Design Flow & Examples
  • Installation
  • 2. Setting up the Environment
    • +
  • Complete Design Flow & Examples
  • Installation
  • 2. Setting up the Environment
    • +
  • Complete Design Flow & Examples
  • Installation
  • 2. Setting up the Environment + + +

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    diff --git a/vlsisapd/doc/html/functions_func.html b/vlsisapd/doc/html/functions_func.html index d7859488..fff5bf8a 100644 --- a/vlsisapd/doc/html/functions_func.html +++ b/vlsisapd/doc/html/functions_func.html @@ -37,46 +37,27 @@
  • addConnector() : Instance
    • -
  • addDevice() -: Netlist -
  • addElement() : Structure
    • -
  • addEquation() -: Sizing -
  • addInclude() : Circuit
  • addInstance() -: Layout -, Netlist -, Schematic -, Circuit +: Circuit , Subckt
  • addInterface() : Subckt
    • -
  • addIntermediatePoint() -: Wire -
  • addLibrary() : Circuit
    • -
  • addNet() -: Netlist -
    • -
  • addOperator() -: Sizing -
  • addOption() : Circuit
  • addParameter() -: Parameters -, Circuit +: Circuit , Instance , Subckt
    • @@ -86,32 +67,235 @@
  • addPolygon() : Circuit
    • -
  • addPort() -: Net -
  • addRule() : Techno
    • -
  • addSimulModel() -: Circuit -
  • addSource() : Circuit
  • addStructure() : Library
    • -
  • addSubCircuitPath() -: Circuit -
  • addSubckt() : Circuit
    • -
  • addTransistor() -: Device + + + +

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    diff --git a/vlsisapd/doc/html/hierarchy.html b/vlsisapd/doc/html/hierarchy.html index 81d6967d..fd4ffc08 100644 --- a/vlsisapd/doc/html/hierarchy.html +++ b/vlsisapd/doc/html/hierarchy.html @@ -30,67 +30,55 @@
    This inheritance list is sorted roughly, but not completely, alphabetically:
    -
    [detail level 123]
    - - +
    [detail level 12]
     CCircuit
     CCircuit
    + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
     CBloc
     CCircuit
     CCircuit
     CNet::Connection
     COperator::Constraint
     CDTRException
     ▼CElement
     CRectangle
     ▼CEquation
     CDDP
     CDesignerCstrOC
     CHighLevelCstr
     CNRCCstr
     CSchematic::Infos
     ▼CInstance
     CDevice
     ▼CInstance
     CCapacitor
     CMosfet
     CResistor
     CLayout
     CLibrary
     Cmap_item< Key, Val >
     Cmap_item< Key, Val >
     CName
     CNet
     CNetlist
     ▼CNode
     CBloc
     CGroup
     COpenChamsException
     COperator
     CParameters
     CPolygon
     CPort
     ▼CRule
     CARule
     CSchematic
     CSimulModel
     CSizing
     ▼CSlicingNode
     CDSlicingNode
     ▼CHVSlicingNode
     CHSlicingNode
     CVSlicingNode
     CRSlicingNode
     ▼CSource
     CCurrent
     CVoltage
     CSpiceException
     CStructure
     CSubckt
     CTechno
     CTransistor
     CValue
     CWire
     ▼CWirePoint
     CInstancePoint
     CIntermediatePoint
     CPortPoint
     CCircuit
     CNet::Connection
     COperator::Constraint
     CDevice
     CDTRException
     ▼CElement
     CRectangle
     CGroup
     CSchematic::Infos
     ▼CInstance
     CCapacitor
     CMosfet
     CResistor
     CInstance
     CInstancePoint
     CIntermediatePoint
     CLayout
     CLibrary
     Cmap_item< Key, Val >
     CName
     CNet
     CNetlist
     CNode
     COpenChamsException
     COperator
     CParameters
     CPolygon
     CPort
     CPortPoint
     ▼CRule
     CARule
     CSchematic
     CSimulModel
     CSizing
     ▼CSource
     CCurrent
     CVoltage
     CSpiceException
     CStructure
     CSubckt
     CTechno
     CTransistor
     CValue
     CWire
     CWirePoint
    @@ -98,7 +86,7 @@
    - +
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    diff --git a/vlsisapd/doc/html/index.html b/vlsisapd/doc/html/index.html index f06fcc51..8eb456b1 100644 --- a/vlsisapd/doc/html/index.html +++ b/vlsisapd/doc/html/index.html @@ -56,7 +56,7 @@
    - +
    Generated by doxygen 1.8.14 on Thu Oct 18 2018Generated by doxygen 1.8.14 on Sun May 26 2019 Return to top of page
    diff --git a/vlsisapd/doc/html/openchams.html b/vlsisapd/doc/html/openchams.html index cd5edffe..a36eaf8a 100644 --- a/vlsisapd/doc/html/openchams.html +++ b/vlsisapd/doc/html/openchams.html @@ -40,73 +40,73 @@ Author Stand alone database structure

    The database has many objects that can be arranged in five categories:

    • General
      • -
    • Netlist
        -
      • OpenChams::Netlist
        • -
      • OpenChams::Instance
        • -
      • OpenChams::Device
        • -
      • OpenChams::Transistor
        • -
      • OpenChams::Parameters
        • -
      • OpenChams::Net
        • +
      • Netlist
          +
        • OpenChams::Netlist
          • +
        • OpenChams::Instance
          • +
        • OpenChams::Device
          • +
        • OpenChams::Transistor
          • +
        • OpenChams::Parameters
          • +
        • OpenChams::Net
        • -
      • Sizing
          -
        • OpenChams::Sizing
          • -
        • OpenChams::Operator
          • -
        • OpenChams::SimulModel
          • +
        • Sizing
            +
          • OpenChams::Sizing
            • +
          • OpenChams::Operator
            • +
          • OpenChams::SimulModel
          • -
        • Schematic
            -
          • OpenChams::Schematic
            • -
          • OpenChams::Port
            • -
          • OpenChams::Wire
            • -
          • OpenChams::WirePoint
            • -
          • OpenChams::InstancePoint
            • -
          • OpenChams::PortPoint
            • -
          • OpenChams::IntermediatePoint
            • +
          • Schematic
              +
            • OpenChams::Schematic
              • +
            • OpenChams::Port
              • +
            • OpenChams::Wire
              • +
            • OpenChams::WirePoint
              • +
            • OpenChams::InstancePoint
              • +
            • OpenChams::PortPoint
              • +
            • OpenChams::IntermediatePoint
            • -
          • Layout

            Using the parser

            -

            Simply load an OPENCHAMS file using the static function OpenChams::Circuit::readFromFile() and then get the netlist object (OpenChams::Circuit::getNetlist()) or the sizing procedure (OpenChams::Circuit::getSizing(), might be NULL) or any other useful information (see OpenChams::Circuit).

            +

            Simply load an OPENCHAMS file using the static function OpenChams::Circuit::readFromFile() and then get the netlist object (OpenChams::Circuit::getNetlist()) or the sizing procedure (OpenChams::Circuit::getSizing(), might be NULL) or any other useful information (see OpenChams::Circuit).

            Using the driver

            -

            Using the driver is very simple, user has to create an OpenChams::Circuit object and simply add OpenChams::Netlist (mandatory) and OpenChams::Sizing (optionnal) or OpenChams::Schematic (optionnal) or OpenChams::Layout (optinnal) to it. Finally use the OpenChams::Circuit::writeToFile() method to dump the database to file.

            +

            Using the driver is very simple, user has to create an OpenChams::Circuit object and simply add OpenChams::Netlist (mandatory) and OpenChams::Sizing (optionnal) or OpenChams::Schematic (optionnal) or OpenChams::Layout (optinnal) to it. Finally use the OpenChams::Circuit::writeToFile() method to dump the database to file.

            Examples

            -

            As said is the global presentation, VLSI SAPD project provides C++ libraries and Python modules for each supported format. In this section we present simple code examples to parse and drive a OPENCHAMS file using C++ or Python. The OPENCHAMS files considered are the same for all examples: inverter.xml and buffer.xml

            <?xml version="1.0" encoding="UTF-8"?>
            <circuit name="inverter" techno="myTech">
            <parameters>
            <parameter name="temp" value="27.0"/>
            <parameter name="Vdd" value="1.2"/>
            <parameter name="Vss" value="0.0"/>
            <parameter name="L" value="0.10e-6"/>
            <parameter name="Ids" value="30e-6"/>
            <parameter name="Veg" value="0.12"/>
            <parameterEq name="complex" equation="myEq"/>
            </parameters>
            <netlist>
            <instances>
            <instance name="nmos1" model="Transistor" order="1" mostype="NMOS" sourceBulkConnected="True">
            <connectors>
            <connector name="G"/>
            <connector name="D"/>
            <connector name="S"/>
            </connectors>
            <transistors>
            <transistor name="m1">
            <connection gate="G" source="S" drain="D" bulk="S"/>
            </transistor>
            </transistors>
            </instance>
            <instance name="pmos1" model="Transistor" order="2" mostype="PMOS" sourceBulkConnected="True">
            <connectors>
            <connector name="G"/>
            <connector name="D"/>
            <connector name="S"/>
            </connectors>
            <transistors>
            <transistor name="m1">
            <connection gate="G" source="S" drain="D" bulk="S"/>
            </transistor>
            </transistors>
            </instance>
            </instances>
            <nets>
            <net name="vdd" type="power" isExternal="True">
            <connector instance="pmos1" name="S"/>
            </net>
            <net name="vss" type="ground" isExternal="True">
            <connector instance="nmos1" name="S"/>
            </net>
            <net name="in" type="logical" isExternal="True">
            <connector instance="nmos1" name="G"/>
            <connector instance="pmos1" name="G"/>
            </net>
            <net name="out" type="logical" isExternal="True">
            <connector instance="nmos1" name="D"/>
            <connector instance="pmos1" name="D"/>
            </net>
            </nets>
            </netlist>
            <schematic>
            <instance name="nmos1" x="2490" y="2600" orient="ID"/>
            <instance name="pmos1" x="2490" y="2490" orient="ID"/>
            <net name="vdd">
            <port type="inV" idx="0" x="2525" y="2430" orient="ID"/>
            <wire>
            <connector name="pmos1" plug="S"/>
            <!--point x="" y=""/-->
            <connector idx="0"/>
            </wire>
            </net>
            <net name="vss">
            <port type="inV" idx="0" x="2525" y="2740" orient="MY"/>
            <wire>
            <connector name="nmos1" plug="S"/>
            <connector idx="0"/>
            </wire>
            </net>
            <net name="in">
            <port type="inH" idx="0" x="2415" y="2520" orient="ID"/>
            <wire>
            <connector name="pmos1" plug="G"/>
            <connector name="nmos1" plug="G"/>
            </wire>
            <wire>
            <connector idx="0"/>
            <connector name="pmos1" plug="G"/>
            </wire>
            </net>
            <net name="out">
            <port type="outH" idx="0" x="2570" y="2590" orient="ID"/>
            <wire>
            <connector name="pmos1" plug="D"/>
            <connector name="nmos1" plug="D"/>
            </wire>
            <wire>
            <connector name="nmos1" plug="D"/>
            <connector idx="0"/>
            </wire>
            </net>
            </schematic>
            <sizing>
            <instance name="pmos1" operator="OPVG(Veg)" simulModel="BSIM3V3">
            <constraint param="Temp" ref="design" refParam="temp"/>
            <constraint param="Ids" ref="design" refParam="Ids"/>
            <constraint param="L" ref="design" refParam="L"/>
            <constraint param="Veg" ref="design" refParam="Veg"/>
            <constraint param="Vd" ref="design" refParam="Vdd" factor="0.5"/>
            <constraint param="Vs" ref="design" refParam="Vdd"/>
            </instance>
            <instance name="nmos1" operator="OPW(Vg,Vs)" simulModel="BSIM3V3">
            <constraint param="Temp" ref="design" refParam="temp"/>
            <constraint param="Ids" ref="design" refParam="Ids"/>
            <constraint param="L" ref="design" refParam="L"/>
            <constraint param="Vs" ref="design" refParam="Vdd"/>
            <constraint param="Vg" ref="pmos1" refParam="Vg"/>
            <constraint param="Vd" ref="pmos1" refParam="Vd"/>
            <constraint param="another" refEquation="myEq" factor="-2.5"/>
            </instance>
            <equations>
            <eq name="myEq" equation="A/more+complex*equation"/>
            </equations>
            </sizing>
            <layout>
            <instance name="pmos1" style="Common transistor"/>
            <instance name="nmos1" style="Rotate transistor"/>
            <hbtree>
            <group name="g1" align="vertical">
            <bloc name="nmos1">
            <bloc name="pmos1" position="top"/>
            </bloc>
            </group>
            </hbtree>
            </layout>
            </circuit>
            <?xml version="1.0" encoding="UTF-8"?>
            <circuit name="buffer" techno="myTech">
            <subCircuitsPaths>
            <path path="."/>
            </subCircuitsPaths>
            <netlist>
            <instances>
            <instance name="inv1" model="inverter">
            <connectors>
            <connector name="vdd"/>
            <connector name="vss"/>
            <connector name="in" />
            <connector name="out"/>
            </connectors>
            </instance>
            <instance name="inv2" model="inverter">
            <connectors>
            <connector name="vdd"/>
            <connector name="vss"/>
            <connector name="in" />
            <connector name="out"/>
            </connectors>
            </instance>
            </instances>
            <nets>
            <net name="vdd" type="power" isExternal="True">
            <connector instance="inv1" name="vdd"/>
            <connector instance="inv2" name="vdd"/>
            </net>
            <net name="vss" type="ground" isExternal="True">
            <connector instance="inv1" name="vss"/>
            <connector instance="inv2" name="vss"/>
            </net>
            <net name="in" type="logical" isExternal="True">
            <connector instance="inv1" name="in"/>
            </net>
            <net name="out" type="logical" isExternal="True">
            <connector instance="inv2" name="out"/>
            </net>
            <net name="internal" type="logical" isExternal="False">
            <connector instance="inv1" name="out"/>
            <connector instance="inv2" name="in"/>
            </net>
            </nets>
            </netlist>
            <schematic>
            <instance name="inv1" x="2490" y="2600" orient="ID"/>
            <instance name="inv2" x="2490" y="2300" orient="ID"/>
            <net name="in">
            <port type="inV" idx="0" x="2415" y="2700" orient="MY"/>
            <wire>
            <connector name="inv1" plug="in"/>
            <connector idx="0"/>
            </wire>
            </net>
            <net name="internal">
            <wire>
            <connector name="inv1" plug="out"/>
            <connector name="inv2" plug="in"/>
            </wire>
            </net>
            <net name="out">
            <port type="outV" idx="0" x="2415" y="2200" orient="MY"/>
            <wire>
            <connector name="inv2" plug="out"/>
            <connector idx="0"/>
            </wire>
            </net>
            <net name="vdd">
            <port type="inH" idx="0" x="2200" y="2500" orient="ID"/>
            <wire>
            <connector idx="0"/>
            <connector name="inv2" plug="vdd"/>
            </wire>
            <wire>
            <connector name="inv1" plug="vdd"/>
            <connector name="inv2" plug="vdd"/>
            </wire>
            </net>
            <net name="vss">
            <port type="inH" idx="0" x="2700" y="2500" orient="MX"/>
            <wire>
            <connector idx="0"/>
            <connector name="inv2" plug="vss"/>
            </wire>
            <wire>
            <connector name="inv1" plug="vss"/>
            <connector name="inv2" plug="vss"/>
            </wire>
            </net>
            </schematic>
            </circuit>

            All source codes are available in the examples directory.

            +

            As said is the global presentation, VLSI SAPD project provides C++ libraries and Python modules for each supported format. In this section we present simple code examples to parse and drive a OPENCHAMS file using C++ or Python. The OPENCHAMS files considered are the same for all examples: inverter.xml and buffer.xml

            All source codes are available in the examples directory.

            C++

            Parser

            -

            The following code (parseOpenChams.cpp) is an example of how to parse a OPENCHAMS file using C++ library.

            #include <iostream>
            #include <string>
            #include <map>
            #include <vector>
            using namespace std;
            #include "vlsisapd/openChams/Circuit.h"
            #include "vlsisapd/openChams/Name.h"
            #include "vlsisapd/openChams/Parameters.h"
            #include "vlsisapd/openChams/Netlist.h"
            #include "vlsisapd/openChams/Instance.h"
            #include "vlsisapd/openChams/Device.h"
            #include "vlsisapd/openChams/Net.h"
            #include "vlsisapd/openChams/Transistor.h"
            #include "vlsisapd/openChams/Schematic.h"
            #include "vlsisapd/openChams/Sizing.h"
            #include "vlsisapd/openChams/Operator.h"
            #include "vlsisapd/openChams/Layout.h"
            #include "vlsisapd/openChams/Node.h"
            #include "vlsisapd/openChams/Port.h"
            #include "vlsisapd/openChams/Wire.h"
            #include "vlsisapd/openChams/OpenChamsException.h"
            void printHBTree(OpenChams::Node* node, unsigned indent) {
            if (!node) return; // since we pass nnode->getRight and node-getTop without checking for NULL
            for (unsigned i = 0 ; i < indent ; i++) {
            cerr << " |";
            }
            string pos = "";
            switch(node->getPosition()) {
            case OpenChams::Node::TOP:
            pos = "top";
            break;
            case OpenChams::Node::RIGHT:
            pos = "right";
            break;
            default:
            break;
            }
            OpenChams::Bloc* bloc = dynamic_cast<OpenChams::Bloc*>(node);
            if (bloc) {
            cerr << " bloc: " << bloc->getName().getString() << " - " << pos << endl;
            printHBTree(bloc->getTop() , indent+1);
            printHBTree(bloc->getRight(), indent+1);
            return;
            }
            OpenChams::Group* group = dynamic_cast<OpenChams::Group*>(node);
            if (group) {
            string align = "none";
            switch(group->getAlign()) {
            case OpenChams::Group::VERTICAL:
            align = "vertical";
            break;
            case OpenChams::Group::HORIZONTAL:
            align = "horizontal";
            break;
            default:
            break;
            }
            cerr << " group: " << group->getName().getString() << " - " << pos << " - align: " << align << " - isolated: " << group->isIsolated() << " - paired: " << group->isPaired() << endl;
            printHBTree(group->getRootNode(), indent+1);
            printHBTree(group->getTop() , indent+1);
            printHBTree(group->getRight() , indent+1);
            return;
            }
            cerr << "[ERROR] printHBTree: node is nor a bloc nor a group !" << endl;
            return;
            }
            int main(int argc, char * argv[]) {
            string file = "";
            if (argc == 1)
            file = "./inverter.xml";
            else if (argc == 2)
            file = argv[1];
            else {
            cerr << "Usage: openChamsParser [filename]" << endl;
            exit(1);
            }
            OpenChams::Circuit* circuit = NULL;
            try {
            circuit = OpenChams::Circuit::readFromFile(file);
            } catch (OpenChams::OpenChamsException& e) {
            cerr << e.what() << endl;
            exit(48);
            }
            cerr << circuit->getName().getString() << endl;
            cerr << " + parameters" << endl;
            OpenChams::Parameters params = circuit->getParameters();
            if (!params.isEmpty()) {
            for (map<OpenChams::Name, string>::const_iterator it = params.getValues().begin() ; it != params.getValues().end() ; ++it) {
            cerr << " | | " << ((*it).first).getString() << " : " << (*it).second << endl;
            }
            }
            cerr << " + netlist" << endl;
            cerr << " | + instances" << endl;
            OpenChams::Netlist* netlist = circuit->getNetlist();
            if (netlist && !netlist->hasNoInstances()) {
            for (size_t i = 0 ; i < netlist->getInstances().size() ; i++) {
            OpenChams::Instance* inst = netlist->getInstances()[i];
            OpenChams::Device* dev = NULL;
            if (dynamic_cast<OpenChams::Device*>(inst)) {
            dev = static_cast<OpenChams::Device*>(inst);
            cerr << " | | + " << dev->getName().getString() << " : " << dev->getModel().getString() << " - " << dev->getOrder() << " - " << dev->getMosType().getString() << " - " << (dev->isSourceBulkConnected()?"true":"false") << endl;
            } else {
            cerr << " | | + " << inst->getName().getString() << " : " << inst->getModel().getString() << " - " << inst->getOrder() << endl;
            }
            cerr << " | | | + connectors" << endl;
            for (map<OpenChams::Name, OpenChams::Net*>::const_iterator cit = inst->getConnectors().begin() ; cit != inst->getConnectors().end() ; ++cit) {
            if ((*cit).second)
            cerr << " | | | | " << ((*cit).first).getString() << " : " << ((*cit).second)->getName().getString() << endl;
            else
            cerr << " | | | | " << ((*cit).first).getString() << endl; // no net connected !
            }
            if (dev) {
            cerr << " | | | + transistors" << endl;
            for (size_t j = 0 ; j < dev->getTransistors().size() ; j++) {
            OpenChams::Transistor* tr = dev->getTransistors()[j];
            cerr << " | | | | name: " << tr->getName().getString() << " - gate: " << tr->getGate().getString() << " - source: " << tr->getSource().getString() << " - drain: " << tr->getDrain().getString() << " - bulk: " << tr->getBulk().getString() << endl;
            }
            }
            }
            }
            cerr << " | + nets" << endl;
            bool schematicNet = false; // define wether net sections are needed in schematic section
            if (!netlist->hasNoNets()) {
            for (size_t i = 0 ; i < netlist->getNets().size() ; i++) {
            OpenChams::Net* net = netlist->getNets()[i];
            cerr << " | | + " << net->getName().getString() << " : " << net->getType().getString() << " - " << (net->isExternal()?"true":"false") << endl;
            cerr << " | | | + connections" << endl;
            for (size_t j = 0 ; j < net->getConnections().size() ; j++) {
            OpenChams::Net::Connection* connect = net->getConnections()[j];
            cerr << " | | | | " << connect->getInstanceName().getString() << "." << connect->getConnectorName().getString() << endl;
            }
            if (!net->hasNoPorts() || !net->hasNoWires())
            schematicNet = true;
            }
            }
            OpenChams::Schematic* schematic = circuit->getSchematic();
            if (schematic && !schematic->hasNoInstances()) {
            cerr << " + schematic" << endl;
            for (map<OpenChams::Name, OpenChams::Schematic::Infos*>::const_iterator sit = schematic->getInstances().begin() ; sit != schematic->getInstances().end() ; ++sit) {
            OpenChams::Schematic::Infos* inf = (*sit).second;
            cerr << " | + instance: name: " << ((*sit).first).getString() << " - x: " << inf->getX() << " - y: " << inf->getY() << " - orientation: " << inf->getOrientation().getString() << endl;
            }
            if (schematicNet) {
            for (size_t i = 0 ; i < netlist->getNets().size() ; i++) {
            OpenChams::Net* net = netlist->getNets()[i];
            cerr << " | + net name: " << net->getName().getString() << endl;
            if (!net->hasNoPorts()) {
            for (size_t j = 0 ; j < net->getPorts().size() ; j++) {
            OpenChams::Port* port = net->getPorts()[j];
            cerr << " | | + port type: " << port->getType().getString() << " - idx: " << port->getIndex() << " - x: " << port->getX() << " - y: " << port->getY() << " - orientation: " << port->getOrientation().getString() << endl;
            }
            }
            if (!net->hasNoWires()) {
            for (size_t j = 0 ; j < net->getWires().size() ; j++) {
            OpenChams::Wire* wire = net->getWires()[j];
            cerr << " | | + wire ";
            OpenChams::WirePoint* start = wire->getStartPoint();
            if (dynamic_cast<OpenChams::InstancePoint*>(start)) {
            OpenChams::InstancePoint* iP = static_cast<OpenChams::InstancePoint*>(start);
            cerr << "<" << iP->getName().getString() << "," << iP->getPlug().getString() << "> ";
            } else if (dynamic_cast<OpenChams::PortPoint*>(start)) {
            OpenChams::PortPoint* pP = static_cast<OpenChams::PortPoint*>(start);
            cerr << "<" << pP->getIndex() << "> ";
            }
            for (size_t k = 0 ; k < wire->getIntermediatePoints().size() ; k++) {
            OpenChams::IntermediatePoint* iP = wire->getIntermediatePoints()[k];
            cerr << "<" << iP->getX() << "," << iP->getY() << "> ";
            }
            OpenChams::WirePoint* end = wire->getEndPoint();
            if (dynamic_cast<OpenChams::InstancePoint*>(end)) {
            OpenChams::InstancePoint* iP = static_cast<OpenChams::InstancePoint*>(end);
            cerr << "<" << iP->getName().getString() << "," << iP->getPlug().getString() << "> ";
            } else if (dynamic_cast<OpenChams::PortPoint*>(end)) {
            OpenChams::PortPoint* pP = static_cast<OpenChams::PortPoint*>(end);
            cerr << "<" << pP->getIndex() << "> ";
            }
            cerr << endl;
            }
            }
            }
            }
            }
            OpenChams::Sizing* sizing = circuit->getSizing();
            if (sizing) {
            cerr << " + sizing" << endl;
            if (!sizing->hasNoOperators()) {
            for (map<OpenChams::Name, OpenChams::Operator*>::const_iterator oit = sizing->getOperators().begin() ; oit != sizing->getOperators().end() ; ++oit) {
            OpenChams::Operator* op = (*oit).second;
            cerr << " | + instance name: " << ((*oit).first).getString() << " - operator: " << op->getName().getString() << " - simulModel: " << op->getSimulModel().getString() << endl;
            if (!op->hasNoConstraints()) {
            for (map<OpenChams::Name, OpenChams::Operator::Constraint*>::const_iterator cit = op->getConstraints().begin() ; cit != op->getConstraints().end() ; ++cit) {
            OpenChams::Operator::Constraint* cstr = (*cit).second;
            cerr << " | | + param: " << ((*cit).first).getString() << " - ref: " << cstr->getRef().getString() << " - refParam: " << cstr->getRefParam().getString() << " - factor: " << cstr->getFactor() << endl;
            }
            }
            }
            }
            // To update to the new equations.
            // if (!sizing->hasNoEquations()) {
            // cerr << " | + equations" << endl;
            // for (map<OpenChams::Name, string>::const_iterator eit = sizing->getEquations().begin() ; eit != sizing->getEquations().end() ; ++eit) {
            // cerr << " | | " << ((*eit).first).getString() << " : " << (*eit).second << endl;
            // }
            // }
            }
            OpenChams::Layout* layout = circuit->getLayout();
            if (layout) {
            if (!layout->hasNoInstance()) {
            cerr << " + layout" << endl;
            for (map<OpenChams::Name, OpenChams::Name>::const_iterator lit = layout->getInstances().begin() ; lit != layout->getInstances().end() ; ++lit) {
            cerr << " | | instance name: " << ((*lit).first).getString() << " - style: " << ((*lit).second).getString() << endl;
            }
            }
            OpenChams::Node* root = layout->getHBTreeRoot();
            if (root) {
            cerr << " | + hbtree" << endl;
            printHBTree(root, 2);
            }
            }
            return 0;
            }

            +

            The following code (parseOpenChams.cpp) is an example of how to parse a OPENCHAMS file using C++ library.

            Driver

            -

            This C++ code (driveOpenChams.cpp) generates an inverter.xml file equivalent to the included one.

            #include <string>
            using namespace std;
            #include "vlsisapd/openChams/Circuit.h"
            #include "vlsisapd/openChams/Netlist.h"
            #include "vlsisapd/openChams/Instance.h"
            #include "vlsisapd/openChams/Device.h"
            #include "vlsisapd/openChams/Transistor.h"
            #include "vlsisapd/openChams/Net.h"
            #include "vlsisapd/openChams/Schematic.h"
            #include "vlsisapd/openChams/Sizing.h"
            #include "vlsisapd/openChams/Operator.h"
            #include "vlsisapd/openChams/Layout.h"
            #include "vlsisapd/openChams/Node.h"
            #include "vlsisapd/openChams/Port.h"
            #include "vlsisapd/openChams/Wire.h"
            int main(int argc, char * argv[]) {
            OpenChams::Circuit* circuit = new OpenChams::Circuit(OpenChams::Name("design"), OpenChams::Name("myTech"));
            // value parameters
            circuit->addParameter(OpenChams::Name("temp"), "27.0" );
            circuit->addParameter(OpenChams::Name("Vdd") , "1.2" );
            circuit->addParameter(OpenChams::Name("Vss") , "0.0" );
            circuit->addParameter(OpenChams::Name("L") , "0.1e-6");
            circuit->addParameter(OpenChams::Name("Ids") , "30e-6" );
            circuit->addParameter(OpenChams::Name("Veg") , "0.12" );
            // equation parameters
            circuit->addParameter(OpenChams::Name("complex"), "myEq");
            // netlist
            OpenChams::Netlist* netlist = circuit->createNetlist();
            // instances
            // nmos1
            OpenChams::Device* inst_nmos1 = netlist->addDevice(OpenChams::Name("nmos1"), OpenChams::Name("Transistor"), 1, OpenChams::Name("NMOS"), true);
            inst_nmos1->addConnector(OpenChams::Name("G"));
            inst_nmos1->addConnector(OpenChams::Name("S"));
            inst_nmos1->addConnector(OpenChams::Name("D"));
            OpenChams::Transistor* tr_nmos1 = inst_nmos1->addTransistor(OpenChams::Name("m1"));
            tr_nmos1->setGate (OpenChams::Name("G")); // the name of the connector of inst_nmos1
            tr_nmos1->setSource(OpenChams::Name("S"));
            tr_nmos1->setDrain (OpenChams::Name("D"));
            tr_nmos1->setBulk (OpenChams::Name("S"));
            // pmos1
            OpenChams::Device* inst_pmos1 = netlist->addDevice(OpenChams::Name("pmos1"), OpenChams::Name("Transistor"), 2, OpenChams::Name("PMOS"), true);
            inst_pmos1->addConnector(OpenChams::Name("G"));
            inst_pmos1->addConnector(OpenChams::Name("S"));
            inst_pmos1->addConnector(OpenChams::Name("D"));
            OpenChams::Transistor* tr_pmos1 = inst_pmos1->addTransistor(OpenChams::Name("m1"));
            tr_pmos1->setGate (OpenChams::Name("G")); // the name of the connector of inst_pmos1
            tr_pmos1->setSource(OpenChams::Name("S"));
            tr_pmos1->setDrain (OpenChams::Name("D"));
            tr_pmos1->setBulk (OpenChams::Name("S"));
            // nets
            OpenChams::Net* _vdd = netlist->addNet(OpenChams::Name("vdd"), OpenChams::Name("power") , true);
            OpenChams::Net* _vss = netlist->addNet(OpenChams::Name("vss"), OpenChams::Name("ground") , true);
            OpenChams::Net* _in = netlist->addNet(OpenChams::Name("in" ), OpenChams::Name("logical"), true);
            OpenChams::Net* _out = netlist->addNet(OpenChams::Name("out"), OpenChams::Name("logical"), true);
            _vdd->connectTo(OpenChams::Name("pmos1"), OpenChams::Name("S"));
            _vss->connectTo(OpenChams::Name("nmos1"), OpenChams::Name("S"));
            _in->connectTo (OpenChams::Name("nmos1"), OpenChams::Name("G"));
            _in->connectTo (OpenChams::Name("pmos1"), OpenChams::Name("G"));
            _out->connectTo(OpenChams::Name("nmos1"), OpenChams::Name("D"));
            _out->connectTo(OpenChams::Name("pmos1"), OpenChams::Name("D"));
            // schematic
            OpenChams::Schematic* schematic = circuit->createSchematic();
            schematic->addInstance(OpenChams::Name("nmos1"), 2490, 2600, OpenChams::Name("ID"));
            schematic->addInstance(OpenChams::Name("pmos1"), 2490, 2300, OpenChams::Name("ID"));
            _vdd->addPort(OpenChams::Name("inV"), 0, 2490, 2100, OpenChams::Name("ID"));
            OpenChams::Wire* wVdd = _vdd->addWire();
            wVdd->setStartPoint(OpenChams::Name("pmos1"), OpenChams::Name("S"));
            wVdd->setEndPoint (0);
            _vss->addPort(OpenChams::Name("inV"), 0, 2490, 2800, OpenChams::Name("MY"));
            OpenChams::Wire* wVss = _vss->addWire();
            wVss->setStartPoint(OpenChams::Name("nmos1"), OpenChams::Name("S"));
            wVss->setEndPoint (0);
            _in->addPort(OpenChams::Name("inH"), 0, 2190, 2500, OpenChams::Name("ID"));
            OpenChams::Wire* wIn = _in->addWire();
            wIn->setStartPoint(OpenChams::Name("pmos1"), OpenChams::Name("G"));
            wIn->setEndPoint (OpenChams::Name("nmos1"), OpenChams::Name("G"));
            OpenChams::Wire* wIn1 = _in->addWire();
            wIn1->setStartPoint(0);
            wIn1->setEndPoint (OpenChams::Name("pmos1"), OpenChams::Name("G"));
            _out->addPort(OpenChams::Name("outH"), 0, 2600, 2500, OpenChams::Name("ID"));
            OpenChams::Wire* wOut = _out->addWire();
            wOut->setStartPoint(OpenChams::Name("pmos1"), OpenChams::Name("D"));
            wOut->setEndPoint (OpenChams::Name("nmos1"), OpenChams::Name("D"));
            OpenChams::Wire* wOut1 = _out->addWire();
            wOut1->setStartPoint(OpenChams::Name("nmos1"), OpenChams::Name("D"));
            wOut1->setEndPoint (0);
            // sizing
            OpenChams::Sizing* sizing = circuit->createSizing();
            OpenChams::Operator* op_pmos1 = sizing->addOperator(OpenChams::Name("pmos1"), OpenChams::Name("OPVG(Veg)"), OpenChams::Name("BSIM3V3"));
            op_pmos1->addConstraint(OpenChams::Name("Temp"), OpenChams::Name("design"), OpenChams::Name("temp"));
            op_pmos1->addConstraint(OpenChams::Name("Ids") , OpenChams::Name("design"), OpenChams::Name("Ids") );
            op_pmos1->addConstraint(OpenChams::Name("L") , OpenChams::Name("design"), OpenChams::Name("L") );
            op_pmos1->addConstraint(OpenChams::Name("Veg") , OpenChams::Name("design"), OpenChams::Name("Veg") );
            op_pmos1->addConstraint(OpenChams::Name("Vd") , OpenChams::Name("design"), OpenChams::Name("Vdd") , 0.5);
            op_pmos1->addConstraint(OpenChams::Name("Vs") , OpenChams::Name("design"), OpenChams::Name("Vdd") );
            OpenChams::Operator* op_nmos1 = sizing->addOperator(OpenChams::Name("nmos1"), OpenChams::Name("OPW(Vg,Vs)"), OpenChams::Name("BSIM3V3"));
            op_nmos1->addConstraint(OpenChams::Name("Temp"), OpenChams::Name("design"), OpenChams::Name("temp"));
            op_nmos1->addConstraint(OpenChams::Name("Ids") , OpenChams::Name("design"), OpenChams::Name("Ids" ));
            op_nmos1->addConstraint(OpenChams::Name("L") , OpenChams::Name("design"), OpenChams::Name("L" ));
            op_nmos1->addConstraint(OpenChams::Name("Vs") , OpenChams::Name("design"), OpenChams::Name("Vdd" ));
            op_nmos1->addConstraint(OpenChams::Name("Vg") , OpenChams::Name("pmos1") , OpenChams::Name("Vg" ));
            op_nmos1->addConstraint(OpenChams::Name("Vd") , OpenChams::Name("pmos1") , OpenChams::Name("Vd" ));
            op_nmos1->addConstraint(OpenChams::Name("another"), OpenChams::Name("myEq"), -2.5 );
            // layout
            OpenChams::Layout* layout = circuit->createLayout();
            layout->addInstance(OpenChams::Name("pmos1"), OpenChams::Name("Common transistor"));
            layout->addInstance(OpenChams::Name("nmos1"), OpenChams::Name("Rotate transistor"));
            // create hbtree
            OpenChams::Group* g1 = new OpenChams::Group("g1"); // default position is NONE and default parent is NULL
            g1->setAlign(OpenChams::Group::VERTICAL);
            OpenChams::Bloc* b1 = new OpenChams::Bloc("nmos1", OpenChams::Node::NONE, g1);
            g1->setRootNode(b1); // b1 is root node of group g1
            OpenChams::Bloc* b2 = new OpenChams::Bloc("pmos1", OpenChams::Node::TOP, b1);
            b1->setTop(b2); // b2 is on top of b1
            layout->setHBTreeRoot(g1); // g1 is the root of the tree
            circuit->writeToFile("./myInverter.xml");
            return 0;
            }
            Note
            In order to compile these codes, a CMakeLists.txt file is provided. User must set the $VLSISAPD_TOP variable before running these commands in the directory containing the CMakeLists.txt file:
            %> mkdir build; cd build
            %> cmake ..
            %> make
            +

            This C++ code (driveOpenChams.cpp) generates an inverter.xml file equivalent to the included one.

            Note
            In order to compile these codes, a CMakeLists.txt file is provided. User must set the $VLSISAPD_TOP variable before running these commands in the directory containing the CMakeLists.txt file:
            %> mkdir build; cd build
            %> cmake ..
            %> make

            Python

            Parser

            -

            The following python script (parseOpenChams.py) is an example of how to parse a OPENCHAMS file using python module.

            import sys
            from OPENCHAMS import *
            def printHBTree(node, indent):
            if node == None:
            return
            for i in range(indent):
            print " |",
            if isinstance(node, Bloc):
            print " bloc:", node.getName(), "-", node.getPosition()
            printHBTree(node.top , indent+1)
            printHBTree(node.right, indent+1)
            return
            if isinstance(node, Group):
            print " group:", node.getName(), "-", node.getPosition(), "-", node.align, "-", node.isolated, "-", node.paired
            printHBTree(node.rootNode, indent+1)
            printHBTree(node.top , indent+1)
            printHBTree(node.right , indent+1)
            return
            def printContents(circuit):
            print circuit.name
            # circuit parameters
            print " + parameters"
            for param in circuit.parameters.getValues():
            print " | |", param.key, ":", param.value
            for param in circuit.parameters.getEqValues():
            print " | |", param.key, ":", param.value
            # netlist
            print " + netlist"
            # instances
            print " | + instances"
            for instance in circuit.netlist.getInstances():
            if isinstance(instance, Device):
            print " | | +", instance.name, ":", instance.model, instance.order, instance.mosType, instance.sourceBulkConnected
            else:
            print " | | +", instance.name, ":", instance.model, instance.order
            print " | | | + connectors"
            for conn in instance.getConnectors():
            print " | | | |", conn.key, ":", conn.value.name
            if isinstance(instance, Device):
            print " | | | + transistors"
            for tr in instance.getTransistors():
            print " | | | | name:", tr.name, "- gate:", tr.gate, "- source:", tr.source, "- drain:", tr.drain, "- bulk:", tr.bulk
            # nets
            print " | + nets"
            schematicNet = False
            for net in circuit.netlist.getNets():
            print " | | +", net.name, ":", net.type, net.external
            print " | | | + connections"
            for conn in net.getConnections():
            print " | | | | %s.%s"%(conn.instanceName, conn.connectorName)
            if not net.hasNoPorts() or not net.hasNoWires():
            schematicNet = True
            # schematic
            if (circuit.schematic):
            print " + schematic"
            for instance in circuit.schematic.getInstances():
            print " | + instance name:", instance.key, "- x:", instance.value.x, "- y:", instance.value.y, "- orientation:", instance.value.orientation
            if schematicNet:
            for net in circuit.netlist.getNets():
            if net.hasNoPorts() and net.hasNoWires():
            continue
            print " | + net name:", net.name
            for port in net.getPorts():
            print " | | + port type:", port.type, "- idx:", port.index, "- x:", port.x, "- y:", port.y, "- orientation:", port.orientation
            for wire in net.getWires():
            if isinstance(wire.startPoint, InstancePoint):
            print " | | + wire <" + wire.startPoint.name.getString() + "," + wire.startPoint.plug.getString() +">"
            elif isinstance(wire.startPoint, PortPoint):
            print " | | + wire <" + str(wire.startPoint.index) + ">"
            else:
            print " - - UNKNOWN START POINT"
            for point in wire.getIntermediatePoints():
            print " | | <" + str(point.x) + "," + str(point.y) + ">"
            if isinstance(wire.endPoint, InstancePoint):
            print " | | <" + wire.endPoint.name.getString() + "," + wire.endPoint.plug.getString() +">"
            elif isinstance(wire.endPoint, PortPoint):
            print " | | <" + str(wire.endPoint.index) + ">"
            else:
            print " - - UNKNOWN END POINT"
            # sizing
            if (circuit.sizing):
            print " + sizing"
            for op in circuit.sizing.getOperators():
            print " | + instance name:", op.key, "- operator:", op.value.name, "- simulModel:", op.value.simulModel
            for constraint in op.value.getConstraints():
            print " | | + param:", constraint.key, "- ref:", constraint.value.ref, "- refParam:", constraint.value.refParam, "- factor:", constraint.value.factor
            print " | + equations"
            for eq in circuit.sizing.getEquations():
            print " | |", eq.key, ":", eq.value
            # layout
            if (circuit.layout):
            print " + layout"
            for inst in circuit.layout.getInstances():
            print " | | instance name:", inst.key, "- style:", inst.value
            if circuit.layout.hbTreeRoot != None:
            print " | + hbtree"
            printHBTree(circuit.layout.hbTreeRoot, 2)
            def usage():
            print "usage:", sys.argv[0], "[filename]"
            sys.exit(48)
            def main():
            if len(sys.argv) == 1:
            filename = "./inverter.xml"
            elif len(sys.argv) == 2:
            filename = sys.argv[1]
            else:
            usage()
            circuit = Circuit.readFromFile(filename)
            printContents(circuit)
            if __name__ == "__main__":
            main()

            +

            The following python script (parseOpenChams.py) is an example of how to parse a OPENCHAMS file using python module.

            Driver

            -

            This python script (driveOpenChams.py) generates an inverter.xml file equivalent to the included one.

            from OPENCHAMS import *
            circuit = Circuit(Name("design"), Name("myTech"))
            # value parameters
            circuit.addParameter(Name("temp"), 27.0 )
            circuit.addParameter(Name("Vdd") , 1.2 )
            circuit.addParameter(Name("Vss") , 0.0 )
            circuit.addParameter(Name("L") , 0.1e-6)
            circuit.addParameter(Name("Ids") , 30e-6 )
            circuit.addParameter(Name("Veg") , 0.12 )
            # equation parameters
            circuit.addParameter(Name("complex"), "myEq")
            # netlist :
            netlist = circuit.createNetlist()
            # instances
            # nmos1
            inst_nmos1 = netlist.addDevice("nmos1", "Transistor", 1, "NMOS", True)
            inst_nmos1.addConnector("G")
            inst_nmos1.addConnector("S")
            inst_nmos1.addConnector("D")
            tr_nmos1 = inst_nmos1.addTransistor("m1")
            tr_nmos1.gate = "G" # the name of the connector of inst_nmos1
            tr_nmos1.source = "S"
            tr_nmos1.drain = "D"
            tr_nmos1.bulk = "S"
            # pmos1
            inst_pmos1 = netlist.addDevice("pmos1", "Transistor", 2, "PMOS", True)
            inst_pmos1.addConnector("G")
            inst_pmos1.addConnector("S")
            inst_pmos1.addConnector("D")
            tr_pmos1 = inst_pmos1.addTransistor("m1")
            tr_pmos1.gate = "G" # the name of the connector of inst_pmos1
            tr_pmos1.source = "S"
            tr_pmos1.drain = "D"
            tr_pmos1.bulk = "S"
            # nets
            _vdd = netlist.addNet("vdd", "power" , True)
            _vss = netlist.addNet("vss", "ground" , True)
            _in = netlist.addNet("in" , "logical", True)
            _out = netlist.addNet("out", "logical", True)
            _vdd.connectTo("pmos1", "S")
            _vss.connectTo("nmos1", "S")
            _in.connectTo ("nmos1", "G")
            _in.connectTo ("pmos1", "G")
            _out.connectTo("nmos1", "D")
            _out.connectTo("pmos1", "D")
            # schematic
            schematic = circuit.createSchematic()
            schematic.addInstance("nmos1", 2490, 2600, "ID")
            schematic.addInstance("pmos1", 2490, 2300, "ID")
            _vdd.addPort("inV" , 0, 2490, 2100, "ID")
            _vss.addPort("inV" , 0, 2490, 2800, "MY")
            _in.addPort ("inH" , 0, 2190, 2500, "ID")
            _out.addPort("outH", 0, 2600, 2500, "ID")
            wireVdd = _vdd.addWire()
            wireVdd.setStartPoint("pmos1", "S")
            wireVdd.setEndPoint(0)
            wireVss = _vss.addWire()
            wireVss.setStartPoint("nmos1", "S")
            wireVss.setEndPoint(0)
            wireIn0 = _in.addWire()
            wireIn1 = _in.addWire()
            wireIn0.setStartPoint("pmos1", "G")
            wireIn0.setEndPoint ("nmos1", "G")
            wireIn1.setStartPoint(0)
            wireIn1.setEndPoint ("pmos1", "G")
            wireOut0 = _out.addWire()
            wireOut1 = _out.addWire()
            wireOut0.setStartPoint("pmos1", "D")
            wireOut0.setEndPoint ("nmos1", "D")
            wireOut1.setStartPoint("nmos1", "D")
            wireOut1.setEndPoint (0)
            # sizing
            sizing = circuit.createSizing()
            op_pmos1 = sizing.addOperator("pmos1", "OPVG(Veg)" , "BSIM3V3")
            op_pmos1.addConstraint("Temp", "design", "temp")
            op_pmos1.addConstraint("Ids" , "design", "Ids" )
            op_pmos1.addConstraint("L" , "design", "L" )
            op_pmos1.addConstraint("Veg" , "design", "Veg" )
            op_pmos1.addConstraint("Vd" , "design", "Vdd", 0.5)
            op_pmos1.addConstraint("Vs" , "design", "Vdd" )
            op_nmos1 = sizing.addOperator("nmos1", "OPW(Vg,Vs)", "BSIM3V3")
            op_nmos1.addConstraint("Temp", "design", "temp")
            op_nmos1.addConstraint("Ids" , "design", "Ids" )
            op_nmos1.addConstraint("L" , "design", "L" )
            op_nmos1.addConstraint("Vs" , "design", "Vdd" )
            op_nmos1.addConstraint("Vg" , "pmos1" , "Vg" )
            op_nmos1.addConstraint("Vd" , "pmos1" , "Vd" )
            op_nmos1.addConstraint("another", "myEq", -2.5 )
            # layout
            layout = circuit.createLayout()
            layout.addInstance("pmos1", "Common transistor")
            layout.addInstance("nmos1", "Rotate transistor")
            # create hbtree
            g1 = Group("g1")
            g1.align = Group.Align.VERTICAL
            b1 = Bloc("nmos1", Node.Position.NONE, g1)
            g1.rootNode = b1
            b2 = Bloc("pmos1", Node.Position.TOP, b1)
            b1.top = b2
            layout.hbTreeRoot = g1
            circuit.writeToFile("./myInverter.xml")
            Note
            In order to run these two scripts (parseOpenChams.py & driveOpenChams.py), user must ensure that $PYTHONPATH variable points to the directory containing OPENCHAMS.so module.
            +

            This python script (driveOpenChams.py) generates an inverter.xml file equivalent to the included one.

            Note
            In order to run these two scripts (parseOpenChams.py & driveOpenChams.py), user must ensure that $PYTHONPATH variable points to the directory containing OPENCHAMS.so module.

            - +
            Generated by doxygen 1.8.14 on Thu Oct 18 2018Generated by doxygen 1.8.14 on Sun May 26 2019 Return to top of page
            diff --git a/vlsisapd/doc/html/pages.html b/vlsisapd/doc/html/pages.html index 771a1654..2600405e 100644 --- a/vlsisapd/doc/html/pages.html +++ b/vlsisapd/doc/html/pages.html @@ -39,7 +39,7 @@
            - +
            Generated by doxygen 1.8.14 on Thu Oct 18 2018Generated by doxygen 1.8.14 on Sun May 26 2019 Return to top of page
            diff --git a/vlsisapd/doc/html/spice.html b/vlsisapd/doc/html/spice.html index dfbbfb6d..cd26977c 100644 --- a/vlsisapd/doc/html/spice.html +++ b/vlsisapd/doc/html/spice.html @@ -52,7 +52,7 @@ Stand alone database structure

          Using the parser

          -

          Simply load an Spice netlist file using the static function SPICE::Circuit::readFromFile().

          +

          Simply load an Spice netlist file using the static function SPICE::Circuit::readFromFile().

          Using the driver

          Using the driver is very simple, user has to create a SPICE::Circuit object and simply add others Spice objects like SPICE::Subckt or SPICE::Instance to it. Includes, libraries and parameters can also be added to SPICE::Circuit. Finally use the SPICE::Circuit::writeToFile() method to dump the database to file.

          @@ -63,7 +63,7 @@ Examples C++

          Parser

          -

          The following code (parseSpice.cpp) is an example of how to parse a SPICE file using C++ library.

          #include <cstdlib>
          #include <iostream>
          #include <string>
          #include <map>
          #include <vector>
          using namespace std;
          #include "vlsisapd/spice/Circuit.h"
          #include "vlsisapd/spice/SpiceException.h"
          #include "vlsisapd/spice/Sources.h"
          #include "vlsisapd/spice/Subckt.h"
          #include "vlsisapd/spice/Instances.h"
          int main(int argc, char * argv[]) {
          string file = "";
          if (argc == 1)
          file = "./OTA.cir";
          else if (argc == 2)
          file = argv[1];
          else {
          cerr << "Usage: parseSpice [filename]" << endl;
          exit(1);
          }
          SPICE::Circuit* circuit = NULL;
          try {
          circuit = SPICE::Circuit::readFromFile(file);
          } catch (SPICE::SpiceException& e) {
          cerr << e.what() << endl;
          exit(48);
          }
          // if (!circuit) cerr << "circuit is NULL !!" << endl;
          // TITLE
          cerr << "+ " << circuit->getTitle() << endl;
          // INCLUDES
          vector<string> includes = circuit->getIncludes();
          if (includes.size()) {
          cerr << "| + includes" << endl;
          for (size_t i = 0 ; i < includes.size() ; i++)
          cerr << "| | " << includes[i] << endl;
          }
          // LIBRARIES
          vector<pair<string, string> > libs = circuit->getLibraries();
          if (libs.size()) {
          cerr << "| + libraries" << endl;
          for (size_t i = 0 ; i < libs.size() ; i++)
          cerr << "| | " << libs[i].first << " " << libs[i].second << endl;
          }
          // PARAMETERS
          map<string, string> params = circuit->getParameters();
          if (params.size()) {
          cerr << "| + parameters" << endl;
          for (map<string, string>::const_iterator it = params.begin() ; it != params.end() ; ++it)
          cerr << "| | " << (*it).first << " = " << (*it).second << endl;
          }
          // OPTIONS
          map<string, string> opts = circuit->getOptions();
          if (opts.size()) {
          cerr << "| + options" << endl;
          for (map<string, string>::const_iterator it = opts.begin() ; it != opts.end() ; ++it)
          cerr << "| | " << (*it).first << " = " << (*it).second << endl;
          }
          // SOURCES
          vector<SPICE::Source*> sources = circuit->getSources();
          if (sources.size()) {
          cerr << "| + sources" << endl;
          for (size_t i = 0 ; i < sources.size() ; i++) {
          SPICE::Source* s = sources[i];
          cerr << "| | " << s->getName() << " " << s->getPositive() << " " << s->getNegative() << " " << s->getValue() << endl;
          }
          }
          // SUBCKTS
          vector<SPICE::Subckt*> subs = circuit->getSubckts();
          if (subs.size()) {
          cerr << "| + subckts" << endl;
          for (size_t i = 0 ; i < subs.size() ; i++) {
          SPICE::Subckt* sub = subs[i];
          cerr << "| | + " << sub->getName();
          for (size_t j = 0 ; j < sub->getInterfaces().size() ; j++)
          cerr << " " << sub->getInterfaces()[j];
          if (sub->getParameters().size()) {
          cerr << " param:";
          for (map<string, string>::const_iterator it = sub->getParameters().begin() ; it != sub->getParameters().end() ; ++it)
          cerr << " " << (*it).first << "=" << (*it).second;
          }
          cerr << endl;
          for (size_t j = 0 ; j < sub->getInstances().size() ; j++) {
          SPICE::Instance* inst = sub->getInstances()[j];
          cerr << "| | | + " << inst->getName();
          if (dynamic_cast<SPICE::Mosfet*>(inst)) {
          SPICE::Mosfet* mos = static_cast<SPICE::Mosfet*>(inst);
          cerr << " " << mos->getDrain() << " " << mos->getGrid() << " " << mos->getSource() << " " << mos->getBulk() << " " << mos->getModel();
          int k = 0;
          for (map<string, string>::const_iterator it =mos->getParameters().begin() ; it != mos->getParameters().end(); ++it, k++) {
          if (k%6 == 0)
          cerr << endl << "| | | | +";
          cerr << " " << (*it).first << "=" << (*it).second;
          }
          } else if (dynamic_cast<SPICE::Resistor*>(inst)) {
          SPICE::Resistor* res = static_cast<SPICE::Resistor*>(inst);
          cerr << " " << res->getFirst() << " " << res->getSecond() << " " << res->getValue();
          } else if (dynamic_cast<SPICE::Capacitor*>(inst)) {
          SPICE::Capacitor* capa = static_cast<SPICE::Capacitor*>(inst);
          cerr << " " << capa->getPositive() << " " << capa->getNegative() << " " << capa->getValue();
          } else {
          for (size_t k = 0 ; k < inst->getConnectors().size() ; k++)
          cerr << " " << inst->getConnectors()[k];
          cerr << " " << inst->getModel();
          int l = 0;
          for (map<string, string>::const_iterator it = inst->getParameters().begin() ; it != inst->getParameters().end() ; ++it, l++) {
          if (l%6 == 0)
          cerr << endl << "| | | | +";
          cerr << " " << (*it).first << "=" << (*it).second;
          }
          }
          cerr << endl;
          }
          }
          }
          // INSTANCES
          vector<SPICE::Instance*> insts = circuit->getInstances();
          if (insts.size()) {
          cerr << "| + instances" << endl;
          for (size_t i = 0 ; i < insts.size() ; i++) {
          SPICE::Instance* inst = insts[i];
          cerr << "| | + " << inst->getName();
          if (dynamic_cast<SPICE::Mosfet*>(inst)) {
          SPICE::Mosfet* mos = static_cast<SPICE::Mosfet*>(inst);
          cerr << " " << mos->getDrain() << " " << mos->getGrid() << " " << mos->getSource() << " " << mos->getBulk() << " " << mos->getModel();
          int j = 0;
          for (map<string, string>::const_iterator it =mos->getParameters().begin() ; it != mos->getParameters().end(); ++it, j++) {
          if (j%6 == 0)
          cerr << endl << "| | | | +";
          cerr << " " << (*it).first << "=" << (*it).second;
          }
          } else if (dynamic_cast<SPICE::Resistor*>(inst)) {
          SPICE::Resistor* res = static_cast<SPICE::Resistor*>(inst);
          cerr << " " << res->getFirst() << " " << res->getSecond() << " " << res->getValue();
          } else if (dynamic_cast<SPICE::Capacitor*>(inst)) {
          SPICE::Capacitor* capa = static_cast<SPICE::Capacitor*>(inst);
          cerr << " " << capa->getPositive() << " " << capa->getNegative() << " " << capa->getValue();
          } else {
          for (size_t k = 0 ; k < inst->getConnectors().size() ; k++)
          cerr << " " << inst->getConnectors()[k];
          cerr << " " << inst->getModel();
          int l = 0;
          for (map<string, string>::const_iterator it = inst->getParameters().begin() ; it != inst->getParameters().end() ; ++it, l++) {
          if (l%6 == 0)
          cerr << endl << "| | | +";
          cerr << " " << (*it).first << "=" << (*it).second;
          }
          }
          cerr << endl;
          }
          }
          return 0;
          }

          +

          The following code (parseSpice.cpp) is an example of how to parse a SPICE file using C++ library.

          #include <cstdlib>
          #include <iostream>
          #include <string>
          #include <map>
          #include <vector>
          using namespace std;
          #include "vlsisapd/spice/Circuit.h"
          #include "vlsisapd/spice/SpiceException.h"
          #include "vlsisapd/spice/Sources.h"
          #include "vlsisapd/spice/Subckt.h"
          #include "vlsisapd/spice/Instances.h"
          int main(int argc, char * argv[]) {
          string file = "";
          if (argc == 1)
          file = "./OTA.cir";
          else if (argc == 2)
          file = argv[1];
          else {
          cerr << "Usage: parseSpice [filename]" << endl;
          exit(1);
          }
          SPICE::Circuit* circuit = NULL;
          try {
          circuit = SPICE::Circuit::readFromFile(file);
          } catch (SPICE::SpiceException& e) {
          cerr << e.what() << endl;
          exit(48);
          }
          // if (!circuit) cerr << "circuit is NULL !!" << endl;
          // TITLE
          cerr << "+ " << circuit->getTitle() << endl;
          // INCLUDES
          vector<string> includes = circuit->getIncludes();
          if (includes.size()) {
          cerr << "| + includes" << endl;
          for (size_t i = 0 ; i < includes.size() ; i++)
          cerr << "| | " << includes[i] << endl;
          }
          // LIBRARIES
          vector<pair<string, string> > libs = circuit->getLibraries();
          if (libs.size()) {
          cerr << "| + libraries" << endl;
          for (size_t i = 0 ; i < libs.size() ; i++)
          cerr << "| | " << libs[i].first << " " << libs[i].second << endl;
          }
          // PARAMETERS
          map<string, string> params = circuit->getParameters();
          if (params.size()) {
          cerr << "| + parameters" << endl;
          for (map<string, string>::const_iterator it = params.begin() ; it != params.end() ; ++it)
          cerr << "| | " << (*it).first << " = " << (*it).second << endl;
          }
          // OPTIONS
          map<string, string> opts = circuit->getOptions();
          if (opts.size()) {
          cerr << "| + options" << endl;
          for (map<string, string>::const_iterator it = opts.begin() ; it != opts.end() ; ++it)
          cerr << "| | " << (*it).first << " = " << (*it).second << endl;
          }
          // SOURCES
          vector<SPICE::Source*> sources = circuit->getSources();
          if (sources.size()) {
          cerr << "| + sources" << endl;
          for (size_t i = 0 ; i < sources.size() ; i++) {
          SPICE::Source* s = sources[i];
          cerr << "| | " << s->getName() << " " << s->getPositive() << " " << s->getNegative() << " " << s->getValue() << endl;
          }
          }
          // SUBCKTS
          vector<SPICE::Subckt*> subs = circuit->getSubckts();
          if (subs.size()) {
          cerr << "| + subckts" << endl;
          for (size_t i = 0 ; i < subs.size() ; i++) {
          SPICE::Subckt* sub = subs[i];
          cerr << "| | + " << sub->getName();
          for (size_t j = 0 ; j < sub->getInterfaces().size() ; j++)
          cerr << " " << sub->getInterfaces()[j];
          if (sub->getParameters().size()) {
          cerr << " param:";
          for (map<string, string>::const_iterator it = sub->getParameters().begin() ; it != sub->getParameters().end() ; ++it)
          cerr << " " << (*it).first << "=" << (*it).second;
          }
          cerr << endl;
          for (size_t j = 0 ; j < sub->getInstances().size() ; j++) {
          SPICE::Instance* inst = sub->getInstances()[j];
          cerr << "| | | + " << inst->getName();
          if (dynamic_cast<SPICE::Mosfet*>(inst)) {
          SPICE::Mosfet* mos = static_cast<SPICE::Mosfet*>(inst);
          cerr << " " << mos->getDrain() << " " << mos->getGrid() << " " << mos->getSource() << " " << mos->getBulk() << " " << mos->getModel();
          int k = 0;
          for (map<string, string>::const_iterator it =mos->getParameters().begin() ; it != mos->getParameters().end(); ++it, k++) {
          if (k%6 == 0)
          cerr << endl << "| | | | +";
          cerr << " " << (*it).first << "=" << (*it).second;
          }
          } else if (dynamic_cast<SPICE::Resistor*>(inst)) {
          SPICE::Resistor* res = static_cast<SPICE::Resistor*>(inst);
          cerr << " " << res->getFirst() << " " << res->getSecond() << " " << res->getValue();
          } else if (dynamic_cast<SPICE::Capacitor*>(inst)) {
          SPICE::Capacitor* capa = static_cast<SPICE::Capacitor*>(inst);
          cerr << " " << capa->getPositive() << " " << capa->getNegative() << " " << capa->getValue();
          } else {
          for (size_t k = 0 ; k < inst->getConnectors().size() ; k++)
          cerr << " " << inst->getConnectors()[k];
          cerr << " " << inst->getModel();
          int l = 0;
          for (map<string, string>::const_iterator it = inst->getParameters().begin() ; it != inst->getParameters().end() ; ++it, l++) {
          if (l%6 == 0)
          cerr << endl << "| | | | +";
          cerr << " " << (*it).first << "=" << (*it).second;
          }
          }
          cerr << endl;
          }
          }
          }
          // INSTANCES
          vector<SPICE::Instance*> insts = circuit->getInstances();
          if (insts.size()) {
          cerr << "| + instances" << endl;
          for (size_t i = 0 ; i < insts.size() ; i++) {
          SPICE::Instance* inst = insts[i];
          cerr << "| | + " << inst->getName();
          if (dynamic_cast<SPICE::Mosfet*>(inst)) {
          SPICE::Mosfet* mos = static_cast<SPICE::Mosfet*>(inst);
          cerr << " " << mos->getDrain() << " " << mos->getGrid() << " " << mos->getSource() << " " << mos->getBulk() << " " << mos->getModel();
          int j = 0;
          for (map<string, string>::const_iterator it =mos->getParameters().begin() ; it != mos->getParameters().end(); ++it, j++) {
          if (j%6 == 0)
          cerr << endl << "| | | | +";
          cerr << " " << (*it).first << "=" << (*it).second;
          }
          } else if (dynamic_cast<SPICE::Resistor*>(inst)) {
          SPICE::Resistor* res = static_cast<SPICE::Resistor*>(inst);
          cerr << " " << res->getFirst() << " " << res->getSecond() << " " << res->getValue();
          } else if (dynamic_cast<SPICE::Capacitor*>(inst)) {
          SPICE::Capacitor* capa = static_cast<SPICE::Capacitor*>(inst);
          cerr << " " << capa->getPositive() << " " << capa->getNegative() << " " << capa->getValue();
          } else {
          for (size_t k = 0 ; k < inst->getConnectors().size() ; k++)
          cerr << " " << inst->getConnectors()[k];
          cerr << " " << inst->getModel();
          int l = 0;
          for (map<string, string>::const_iterator it = inst->getParameters().begin() ; it != inst->getParameters().end() ; ++it, l++) {
          if (l%6 == 0)
          cerr << endl << "| | | +";
          cerr << " " << (*it).first << "=" << (*it).second;
          }
          }
          cerr << endl;
          }
          }
          return 0;
          }

          Driver

          This C++ code (driveSpice.cpp) generates an myOTA.spi file equivalent to the included one.

          #include <string>
          using namespace std;
          #include "vlsisapd/spice/Circuit.h"
          #include "vlsisapd/spice/Subckt.h"
          #include "vlsisapd/spice/Instances.h"
          int main(int argc, char * argv[]) {
          SPICE::Circuit* circuit = new SPICE::Circuit();
          circuit->setTitle("* Single-ended two-stage amplifier");
          // PARAMS
          circuit->addParameter("CC_VALUE", "2.8794pF");
          circuit->addParameter("L_VALUE" , "0.340e-6");
          // SUBCKTS
          // CurrentMirror
          SPICE::Subckt* CM = circuit->addSubckt("currentMirrorPMOS");
          CM->addInterface("d1");
          CM->addInterface("d2");
          CM->addInterface("s1");
          CM->addInterface("s2");
          CM->addParameter("l_val" , "0.0" );
          CM->addParameter("w_val" , "0.0" );
          CM->addParameter("nf_val" , "1" );
          CM->addParameter("aeq_val" , "100e-6");
          CM->addParameter("temp_val", "27" );
          SPICE::Instance* cmP3 = new SPICE::Mosfet("P3", "d1", "d1", "s1", "s1", "psvt");
          cmP3->addParameter("l" , "l_val" );
          cmP3->addParameter("wf" , "{w_val/nf_val}");
          cmP3->addParameter("nf" , "nf_val" );
          cmP3->addParameter("aeq" , "aeq_val" );
          cmP3->addParameter("tempsimu", "temp_val" );
          CM->addInstance(cmP3);
          SPICE::Instance* cmP4 = new SPICE::Mosfet("P4", "d2", "d1", "s2", "s2", "psvt");
          cmP4->addParameter("l" , "l_val" );
          cmP4->addParameter("wf" , "{w_val/nf_val}");
          cmP4->addParameter("nf" , "nf_val" );
          cmP4->addParameter("aeq" , "aeq_val" );
          cmP4->addParameter("tempsimu", "temp_val" );
          CM->addInstance(cmP4);
          // DifferentialPair
          SPICE::Subckt* DP = circuit->addSubckt("diffPairNMOS");
          DP->addInterface("d1");
          DP->addInterface("d2");
          DP->addInterface("g1");
          DP->addInterface("g2");
          DP->addInterface("s");
          DP->addInterface("b");
          DP->addParameter("l_val" , "0.0" );
          DP->addParameter("w_val" , "0.0" );
          DP->addParameter("nf_val" , "1" );
          DP->addParameter("aeq_val" , "100e-6");
          DP->addParameter("temp_val", "27" );
          SPICE::Instance* dpN1 = new SPICE::Mosfet("N1", "d1", "g1", "s", "b", "nsvt");
          dpN1->addParameter("l" , "l_val" );
          dpN1->addParameter("wf" , "{w_val/nf_val}");
          dpN1->addParameter("nf" , "nf_val" );
          dpN1->addParameter("aeq" , "aeq_val" );
          dpN1->addParameter("tempsimu", "temp_val" );
          DP->addInstance(dpN1);
          SPICE::Instance* dpN2 = new SPICE::Mosfet("N2", "d2", "g2", "s", "b", "nsvt");
          dpN2->addParameter("l" , "l_val" );
          dpN2->addParameter("wf" , "{w_val/nf_val}");
          dpN2->addParameter("nf" , "nf_val" );
          dpN2->addParameter("aeq" , "aeq_val" );
          dpN2->addParameter("tempsimu", "temp_val" );
          DP->addInstance(dpN2);
          //INSTANCES
          SPICE::Instance* iCM = new SPICE::Instance("CM", "currentMirrorPMOS");
          iCM->addConnector("1");
          iCM->addConnector("2");
          iCM->addConnector("vdd");
          iCM->addConnector("vdd");
          iCM->addParameter("l_val" , "L_VALUE" );
          iCM->addParameter("w_val" , "3.889618e-06");
          iCM->addParameter("nf_val", "2" );
          circuit->addInstance(iCM);
          SPICE::Instance* iDP = new SPICE::Instance("DP", "diffPairNMOS");
          iDP->addConnector("1");
          iDP->addConnector("2");
          iDP->addConnector("vim");
          iDP->addConnector("vip");
          iDP->addConnector("3");
          iDP->addConnector("vss");
          iDP->addParameter("l_val" , "L_VALUE" );
          iDP->addParameter("w_val" , "7.683346e-07");
          iDP->addParameter("nf_val", "4" );
          circuit->addInstance(iDP);
          SPICE::Instance* iP6 = new SPICE::Mosfet("P6", "vout", "2", "vdd", "vdd", "psvt");
          iP6->addParameter("l_val" , "L_VALUE" );
          iP6->addParameter("w_val" , "3.558995e-05");
          iP6->addParameter("nf_val", "20" );
          circuit->addInstance(iP6);
          SPICE::Instance* iN5 = new SPICE::Mosfet("N5", "3", "4", "vss", "vss", "nsvt");
          iN5->addParameter("l_val" , "L_VALUE" );
          iN5->addParameter("w_val" , "2.536703e-06");
          iN5->addParameter("nf_val", "4" );
          circuit->addInstance(iN5);
          SPICE::Instance* iN7 = new SPICE::Mosfet("N7", "vout", "4", "vss", "vss", "nsvt");
          iN7->addParameter("l_val" , "L_VALUE" );
          iN7->addParameter("w_val" , "1.069083e-05");
          iN7->addParameter("nf_val", "16" );
          circuit->addInstance(iN7);
          SPICE::Instance* iN8 = new SPICE::Mosfet("N8", "4", "4", "vss", "vss", "nsvt");
          iN8->addParameter("l_val" , "L_VALUE" );
          iN8->addParameter("w_val" , "2.536703e-06");
          iN8->addParameter("nf_val", "4" );
          circuit->addInstance(iN8);
          circuit->addInstance(new SPICE::Capacitor("C1", "vout", "2", "CC_VALUE"));
          circuit->writeToFile("./myOTA.spi");
          return 0;
          }
          Note
          In order to compile these codes, a CMakeLists.txt file is provided. User must set the $VLSISAPD_TOP variable before running these commands in the directory containing the CMakeLists.txt file:
          %> mkdir build; cd build
          %> cmake ..
          %> make

          @@ -72,13 +72,13 @@ Python

          Parser

          The following python script (parseSpice.py) is an example of how to parse a SPICE file using python module.

          import sys
          from SPICE import *
          def printContents(circuit):
          print "+", circuit.title
          if len(circuit.getIncludes()):
          print "| + includes"
          for include in circuit.getIncludes():
          print "| |", include
          if len(circuit.getLibraries()):
          print "| + libraries"
          for (lib, typ) in circuit.getLibraries():
          print "| |", lib, typ
          if len(circuit.getParameters()):
          print "| + parameters"
          for (name, value) in circuit.getParameters().items():
          print "| | %s=%s"%(name, value)
          if len(circuit.getOptions()):
          print "| + options"
          for (name, value) in circuit.getOptions().items():
          print "| | %s=%s"%(name, value)
          if len(circuit.getSources()):
          print "| + sources"
          for source in circuit.getSources():
          print "| |", source.getName(), source.getPositive(), source.getNegative(), source.getValue()
          if len(circuit.getSubckts()):
          print "| + subckts"
          for sub in circuit.getSubckts():
          print "| | +", sub.getName(),
          for interf in sub.getInterfaces():
          print interf,
          if len(sub.getParameters()):
          print "param:",
          for (name, value) in sub.getParameters().items():
          print "%s=%s"%(name,value),
          print
          for inst in sub.getInstances():
          print "| | | +", inst.getName(),
          if isinstance(inst, Mosfet):
          print inst.getDrain(), inst.getGrid(), inst.getSource(), inst.getBulk(), inst.getModel(),
          i = 0
          for (name, value) in inst.getParameters().items():
          if i%6 == 0:
          print
          print "| | | | +",
          print "%s=%s"%(name, value),
          i += 1
          elif isinstance(inst, Resistor):
          print inst.getFirst(), inst.getSecond(), inst.getValue(),
          elif isinstance(inst, Capacitor):
          print inst.getPositive(), inst.getNegative(), inst.getValue(),
          else:
          for conn in inst.getConnectors():
          print conn,
          print inst.getModel(),
          i = 0
          for (name, value) in inst.getParameters().items():
          if i%6 == 0:
          print
          print "| | | | +",
          print "%s=%s"%(name, value),
          i += 1
          print
          if len(circuit.getInstances()):
          print "| + instances"
          for inst in circuit.getInstances():
          print "| | | +", inst.getName(),
          if isinstance(inst, Mosfet):
          print inst.getDrain(), inst.getGrid(), inst.getSource(), inst.getBulk(), inst.getModel(),
          i = 0
          for (name, value) in inst.getParameters().items():
          if i%6 == 0:
          print
          print "| | | | +",
          print "%s=%s"%(name, value),
          i += 1
          elif isinstance(inst, Resistor):
          print inst.getFirst(), inst.getSecond(), inst.getValue(),
          elif isinstance(inst, Capacitor):
          print inst.getPositive(), inst.getNegative(), inst.getValue(),
          else:
          for conn in inst.getConnectors():
          print conn,
          print inst.getModel(),
          i = 0
          for (name, value) in inst.getParameters().items():
          if i%6 == 0:
          print
          print "| | | | +",
          print "%s=%s"%(name, value),
          i += 1
          print
          def usage():
          print "usage:", sys.argv[0], "[filename]"
          sys.exit(48)
          def main():
          if len(sys.argv) == 1:
          filename = "./OTA_miller.spi"
          elif len(sys.argv) == 2:
          filename = sys.argv[1]
          else:
          usage()
          circuit = Circuit.readFromFile(filename)
          printContents(circuit)
          if __name__ == "__main__":
          main()

          Driver

          -

          This python script (driveSpice.py) generates an myOTA.spi file equivalent to the included one.

          from SPICE import *
          circuit = Circuit()
          circuit.title = '* Single-ended two-stage amplifier'
          # PARAMS
          circuit.addParameter("CC_VALUE", "2.8794pF");
          circuit.addParameter("L_VALUE" , "0.340e-6");
          # SUBCKTS
          # CurrentMirror
          CM = circuit.addSubckt("currentMirrorPMOS");
          CM.addInterface("d1");
          CM.addInterface("d2");
          CM.addInterface("s1");
          CM.addInterface("s2");
          CM.addParameter("l_val" , "0.0" );
          CM.addParameter("w_val" , "0.0" );
          CM.addParameter("nf_val" , "1" );
          CM.addParameter("aeq_val" , "100e-6");
          CM.addParameter("temp_val", "27" );
          cmP3 = Mosfet("P3", "d1", "d1", "s1", "s1", "psvt");
          cmP3.addParameter("l" , "l_val" );
          cmP3.addParameter("wf" , "{w_val/nf_val}");
          cmP3.addParameter("nf" , "nf_val" );
          cmP3.addParameter("aeq" , "aeq_val" );
          cmP3.addParameter("tempsimu", "temp_val" );
          CM.addInstance(cmP3);
          cmP4 = Mosfet("P4", "d2", "d1", "s2", "s2", "psvt");
          cmP4.addParameter("l" , "l_val" );
          cmP4.addParameter("wf" , "{w_val/nf_val}");
          cmP4.addParameter("nf" , "nf_val" );
          cmP4.addParameter("aeq" , "aeq_val" );
          cmP4.addParameter("tempsimu", "temp_val" );
          CM.addInstance(cmP4);
          # DifferentialPair
          DP = circuit.addSubckt("diffPairNMOS");
          DP.addInterface("d1");
          DP.addInterface("d2");
          DP.addInterface("g1");
          DP.addInterface("g2");
          DP.addInterface("s");
          DP.addInterface("b");
          DP.addParameter("l_val" , "0.0" );
          DP.addParameter("w_val" , "0.0" );
          DP.addParameter("nf_val" , "1" );
          DP.addParameter("aeq_val" , "100e-6");
          DP.addParameter("temp_val", "27" );
          dpN1 = Mosfet("N1", "d1", "g1", "s", "b", "nsvt");
          dpN1.addParameter("l" , "l_val" );
          dpN1.addParameter("wf" , "{w_val/nf_val}");
          dpN1.addParameter("nf" , "nf_val" );
          dpN1.addParameter("aeq" , "aeq_val" );
          dpN1.addParameter("tempsimu", "temp_val" );
          DP.addInstance(dpN1);
          dpN2 = Mosfet("N2", "d2", "g2", "s", "b", "nsvt");
          dpN2.addParameter("l" , "l_val" );
          dpN2.addParameter("wf" , "{w_val/nf_val}");
          dpN2.addParameter("nf" , "nf_val" );
          dpN2.addParameter("aeq" , "aeq_val" );
          dpN2.addParameter("tempsimu", "temp_val" );
          DP.addInstance(dpN2);
          # INSTANCES
          iCM = Instance("CM", "currentMirrorPMOS");
          iCM.addConnector("1");
          iCM.addConnector("2");
          iCM.addConnector("vdd");
          iCM.addConnector("vdd");
          iCM.addParameter("l_val" , "L_VALUE" );
          iCM.addParameter("w_val" , "3.889618e-06");
          iCM.addParameter("nf_val", "2" );
          circuit.addInstance(iCM);
          iDP = Instance("DP", "diffPairNMOS");
          iDP.addConnector("1");
          iDP.addConnector("2");
          iDP.addConnector("vim");
          iDP.addConnector("vip");
          iDP.addConnector("3");
          iDP.addConnector("vss");
          iDP.addParameter("l_val" , "L_VALUE" );
          iDP.addParameter("w_val" , "7.683346e-07");
          iDP.addParameter("nf_val", "4" );
          circuit.addInstance(iDP);
          iP6 = Mosfet("P6", "vout", "2", "vdd", "vdd", "psvt");
          iP6.addParameter("l_val" , "L_VALUE" );
          iP6.addParameter("w_val" , "3.558995e-05");
          iP6.addParameter("nf_val", "20" );
          circuit.addInstance(iP6);
          iN5 = Mosfet("N5", "3", "4", "vss", "vss", "nsvt");
          iN5.addParameter("l_val" , "L_VALUE" );
          iN5.addParameter("w_val" , "2.536703e-06");
          iN5.addParameter("nf_val", "4" );
          circuit.addInstance(iN5);
          iN7 = Mosfet("N7", "vout", "4", "vss", "vss", "nsvt");
          iN7.addParameter("l_val" , "L_VALUE" );
          iN7.addParameter("w_val" , "1.069083e-05");
          iN7.addParameter("nf_val", "16" );
          circuit.addInstance(iN7);
          iN8 = Mosfet("N8", "4", "4", "vss", "vss", "nsvt");
          iN8.addParameter("l_val" , "L_VALUE" );
          iN8.addParameter("w_val" , "2.536703e-06");
          iN8.addParameter("nf_val", "4" );
          circuit.addInstance(iN8);
          capa = Capacitor("C1", "vout", "2", "CC_VALUE")
          circuit.addInstance(capa);
          circuit.writeToFile("./myOTA.spi");
          Note
          In order to run these two scripts (parseSpice.py & driveSpice.py), user must ensure that $PYTHONPATH variable points to the directory containing SPICE.so module.
          +

          This python script (driveSpice.py) generates an myOTA.spi file equivalent to the included one.

          from SPICE import *
          circuit = Circuit()
          circuit.title = '* Single-ended two-stage amplifier'
          # PARAMS
          circuit.addParameter("CC_VALUE", "2.8794pF");
          circuit.addParameter("L_VALUE" , "0.340e-6");
          # SUBCKTS
          # CurrentMirror
          CM = circuit.addSubckt("currentMirrorPMOS");
          CM.addInterface("d1");
          CM.addInterface("d2");
          CM.addInterface("s1");
          CM.addInterface("s2");
          CM.addParameter("l_val" , "0.0" );
          CM.addParameter("w_val" , "0.0" );
          CM.addParameter("nf_val" , "1" );
          CM.addParameter("aeq_val" , "100e-6");
          CM.addParameter("temp_val", "27" );
          cmP3 = Mosfet("P3", "d1", "d1", "s1", "s1", "psvt");
          cmP3.addParameter("l" , "l_val" );
          cmP3.addParameter("wf" , "{w_val/nf_val}");
          cmP3.addParameter("nf" , "nf_val" );
          cmP3.addParameter("aeq" , "aeq_val" );
          cmP3.addParameter("tempsimu", "temp_val" );
          CM.addInstance(cmP3);
          cmP4 = Mosfet("P4", "d2", "d1", "s2", "s2", "psvt");
          cmP4.addParameter("l" , "l_val" );
          cmP4.addParameter("wf" , "{w_val/nf_val}");
          cmP4.addParameter("nf" , "nf_val" );
          cmP4.addParameter("aeq" , "aeq_val" );
          cmP4.addParameter("tempsimu", "temp_val" );
          CM.addInstance(cmP4);
          # DifferentialPair
          DP = circuit.addSubckt("diffPairNMOS");
          DP.addInterface("d1");
          DP.addInterface("d2");
          DP.addInterface("g1");
          DP.addInterface("g2");
          DP.addInterface("s");
          DP.addInterface("b");
          DP.addParameter("l_val" , "0.0" );
          DP.addParameter("w_val" , "0.0" );
          DP.addParameter("nf_val" , "1" );
          DP.addParameter("aeq_val" , "100e-6");
          DP.addParameter("temp_val", "27" );
          dpN1 = Mosfet("N1", "d1", "g1", "s", "b", "nsvt");
          dpN1.addParameter("l" , "l_val" );
          dpN1.addParameter("wf" , "{w_val/nf_val}");
          dpN1.addParameter("nf" , "nf_val" );
          dpN1.addParameter("aeq" , "aeq_val" );
          dpN1.addParameter("tempsimu", "temp_val" );
          DP.addInstance(dpN1);
          dpN2 = Mosfet("N2", "d2", "g2", "s", "b", "nsvt");
          dpN2.addParameter("l" , "l_val" );
          dpN2.addParameter("wf" , "{w_val/nf_val}");
          dpN2.addParameter("nf" , "nf_val" );
          dpN2.addParameter("aeq" , "aeq_val" );
          dpN2.addParameter("tempsimu", "temp_val" );
          DP.addInstance(dpN2);
          # INSTANCES
          iCM = Instance("CM", "currentMirrorPMOS");
          iCM.addConnector("1");
          iCM.addConnector("2");
          iCM.addConnector("vdd");
          iCM.addConnector("vdd");
          iCM.addParameter("l_val" , "L_VALUE" );
          iCM.addParameter("w_val" , "3.889618e-06");
          iCM.addParameter("nf_val", "2" );
          circuit.addInstance(iCM);
          iDP = Instance("DP", "diffPairNMOS");
          iDP.addConnector("1");
          iDP.addConnector("2");
          iDP.addConnector("vim");
          iDP.addConnector("vip");
          iDP.addConnector("3");
          iDP.addConnector("vss");
          iDP.addParameter("l_val" , "L_VALUE" );
          iDP.addParameter("w_val" , "7.683346e-07");
          iDP.addParameter("nf_val", "4" );
          circuit.addInstance(iDP);
          iP6 = Mosfet("P6", "vout", "2", "vdd", "vdd", "psvt");
          iP6.addParameter("l_val" , "L_VALUE" );
          iP6.addParameter("w_val" , "3.558995e-05");
          iP6.addParameter("nf_val", "20" );
          circuit.addInstance(iP6);
          iN5 = Mosfet("N5", "3", "4", "vss", "vss", "nsvt");
          iN5.addParameter("l_val" , "L_VALUE" );
          iN5.addParameter("w_val" , "2.536703e-06");
          iN5.addParameter("nf_val", "4" );
          circuit.addInstance(iN5);
          iN7 = Mosfet("N7", "vout", "4", "vss", "vss", "nsvt");
          iN7.addParameter("l_val" , "L_VALUE" );
          iN7.addParameter("w_val" , "1.069083e-05");
          iN7.addParameter("nf_val", "16" );
          circuit.addInstance(iN7);
          iN8 = Mosfet("N8", "4", "4", "vss", "vss", "nsvt");
          iN8.addParameter("l_val" , "L_VALUE" );
          iN8.addParameter("w_val" , "2.536703e-06");
          iN8.addParameter("nf_val", "4" );
          circuit.addInstance(iN8);
          capa = Capacitor("C1", "vout", "2", "CC_VALUE")
          circuit.addInstance(capa);
          circuit.writeToFile("./myOTA.spi");
          Note
          In order to run these two scripts (parseSpice.py & driveSpice.py), user must ensure that $PYTHONPATH variable points to the directory containing SPICE.so module.

          - +
          Generated by doxygen 1.8.14 on Thu Oct 18 2018Generated by doxygen 1.8.14 on Sun May 26 2019 Return to top of page
          diff --git a/vlsisapd/doc/html/struct_s_p_i_c_e_1_1map__item.html b/vlsisapd/doc/html/struct_s_p_i_c_e_1_1map__item.html index 2a0e7863..5890f94c 100644 --- a/vlsisapd/doc/html/struct_s_p_i_c_e_1_1map__item.html +++ b/vlsisapd/doc/html/struct_s_p_i_c_e_1_1map__item.html @@ -38,7 +38,7 @@
          - +
          Generated by doxygen 1.8.14 on Thu Oct 18 2018Generated by doxygen 1.8.14 on Sun May 26 2019 Return to top of page
          diff --git a/vlsisapd/doc/latex/annotated.tex b/vlsisapd/doc/latex/annotated.tex index 7dab8c9b..a91bf174 100644 --- a/vlsisapd/doc/latex/annotated.tex +++ b/vlsisapd/doc/latex/annotated.tex @@ -1,63 +1,51 @@ \section{Data Structures} Here are the data structures with brief descriptions\+:\begin{DoxyCompactList} \item\contentsline{section}{\mbox{\hyperlink{class_d_t_r_1_1_a_rule}{A\+Rule}} }{\pageref{class_d_t_r_1_1_a_rule}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_bloc}{Bloc}} }{\pageref{class_open_chams_1_1_bloc}}{} +\item\contentsline{section}{\mbox{\hyperlink{class_bloc}{Bloc}} }{\pageref{class_bloc}}{} \item\contentsline{section}{\mbox{\hyperlink{class_s_p_i_c_e_1_1_capacitor}{Capacitor}} }{\pageref{class_s_p_i_c_e_1_1_capacitor}}{} \item\contentsline{section}{\mbox{\hyperlink{class_c_i_f_1_1_circuit}{Circuit}} }{\pageref{class_c_i_f_1_1_circuit}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_circuit}{Circuit}} }{\pageref{class_open_chams_1_1_circuit}}{} \item\contentsline{section}{\mbox{\hyperlink{class_s_p_i_c_e_1_1_circuit}{Circuit}} }{\pageref{class_s_p_i_c_e_1_1_circuit}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_net_1_1_connection}{Net\+::\+Connection}} }{\pageref{class_open_chams_1_1_net_1_1_connection}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_operator_1_1_constraint}{Operator\+::\+Constraint}} }{\pageref{class_open_chams_1_1_operator_1_1_constraint}}{} +\item\contentsline{section}{\mbox{\hyperlink{class_circuit}{Circuit}} }{\pageref{class_circuit}}{} +\item\contentsline{section}{\mbox{\hyperlink{class_net_1_1_connection}{Net\+::\+Connection}} }{\pageref{class_net_1_1_connection}}{} +\item\contentsline{section}{\mbox{\hyperlink{class_operator_1_1_constraint}{Operator\+::\+Constraint}} }{\pageref{class_operator_1_1_constraint}}{} \item\contentsline{section}{\mbox{\hyperlink{class_s_p_i_c_e_1_1_current}{Current}} }{\pageref{class_s_p_i_c_e_1_1_current}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_d_d_p}{D\+DP}} }{\pageref{class_open_chams_1_1_d_d_p}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_designer_cstr_o_c}{Designer\+Cstr\+OC}} }{\pageref{class_open_chams_1_1_designer_cstr_o_c}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_device}{Device}} }{\pageref{class_open_chams_1_1_device}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_d_slicing_node}{D\+Slicing\+Node}} }{\pageref{class_open_chams_1_1_d_slicing_node}}{} +\item\contentsline{section}{\mbox{\hyperlink{class_device}{Device}} }{\pageref{class_device}}{} \item\contentsline{section}{\mbox{\hyperlink{class_d_t_r_1_1_d_t_r_exception}{D\+T\+R\+Exception}} }{\pageref{class_d_t_r_1_1_d_t_r_exception}}{} \item\contentsline{section}{\mbox{\hyperlink{class_a_g_d_s_1_1_element}{Element}} }{\pageref{class_a_g_d_s_1_1_element}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_equation}{Equation}} }{\pageref{class_open_chams_1_1_equation}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_group}{Group}} }{\pageref{class_open_chams_1_1_group}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_high_level_cstr}{High\+Level\+Cstr}} }{\pageref{class_open_chams_1_1_high_level_cstr}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_h_slicing_node}{H\+Slicing\+Node}} }{\pageref{class_open_chams_1_1_h_slicing_node}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_h_v_slicing_node}{H\+V\+Slicing\+Node}} }{\pageref{class_open_chams_1_1_h_v_slicing_node}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_schematic_1_1_infos}{Schematic\+::\+Infos}} }{\pageref{class_open_chams_1_1_schematic_1_1_infos}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_instance}{Instance}} }{\pageref{class_open_chams_1_1_instance}}{} +\item\contentsline{section}{\mbox{\hyperlink{class_group}{Group}} }{\pageref{class_group}}{} +\item\contentsline{section}{\mbox{\hyperlink{class_schematic_1_1_infos}{Schematic\+::\+Infos}} }{\pageref{class_schematic_1_1_infos}}{} \item\contentsline{section}{\mbox{\hyperlink{class_s_p_i_c_e_1_1_instance}{Instance}} }{\pageref{class_s_p_i_c_e_1_1_instance}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_instance_point}{Instance\+Point}} }{\pageref{class_open_chams_1_1_instance_point}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_intermediate_point}{Intermediate\+Point}} }{\pageref{class_open_chams_1_1_intermediate_point}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_layout}{Layout}} }{\pageref{class_open_chams_1_1_layout}}{} +\item\contentsline{section}{\mbox{\hyperlink{class_instance}{Instance}} }{\pageref{class_instance}}{} +\item\contentsline{section}{\mbox{\hyperlink{class_instance_point}{Instance\+Point}} }{\pageref{class_instance_point}}{} +\item\contentsline{section}{\mbox{\hyperlink{class_intermediate_point}{Intermediate\+Point}} }{\pageref{class_intermediate_point}}{} +\item\contentsline{section}{\mbox{\hyperlink{class_layout}{Layout}} }{\pageref{class_layout}}{} \item\contentsline{section}{\mbox{\hyperlink{class_a_g_d_s_1_1_library}{Library}} }{\pageref{class_a_g_d_s_1_1_library}}{} -\item\contentsline{section}{\mbox{\hyperlink{struct_open_chams_1_1map__item}{map\+\_\+item$<$ Key, Val $>$}} }{\pageref{struct_open_chams_1_1map__item}}{} \item\contentsline{section}{\mbox{\hyperlink{struct_s_p_i_c_e_1_1map__item}{map\+\_\+item$<$ Key, Val $>$}} }{\pageref{struct_s_p_i_c_e_1_1map__item}}{} \item\contentsline{section}{\mbox{\hyperlink{class_s_p_i_c_e_1_1_mosfet}{Mosfet}} }{\pageref{class_s_p_i_c_e_1_1_mosfet}}{} \item\contentsline{section}{\mbox{\hyperlink{class_name}{Name}} }{\pageref{class_name}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_net}{Net}} }{\pageref{class_open_chams_1_1_net}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_netlist}{Netlist}} }{\pageref{class_open_chams_1_1_netlist}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_node}{Node}} }{\pageref{class_open_chams_1_1_node}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_n_r_c_cstr}{N\+R\+C\+Cstr}} }{\pageref{class_open_chams_1_1_n_r_c_cstr}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_open_chams_exception}{Open\+Chams\+Exception}} }{\pageref{class_open_chams_1_1_open_chams_exception}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_operator}{Operator}} }{\pageref{class_open_chams_1_1_operator}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_parameters}{Parameters}} }{\pageref{class_open_chams_1_1_parameters}}{} +\item\contentsline{section}{\mbox{\hyperlink{class_net}{Net}} }{\pageref{class_net}}{} +\item\contentsline{section}{\mbox{\hyperlink{class_netlist}{Netlist}} }{\pageref{class_netlist}}{} +\item\contentsline{section}{\mbox{\hyperlink{class_node}{Node}} }{\pageref{class_node}}{} +\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_exception}{Open\+Chams\+Exception}} }{\pageref{class_open_chams_exception}}{} +\item\contentsline{section}{\mbox{\hyperlink{class_operator}{Operator}} }{\pageref{class_operator}}{} +\item\contentsline{section}{\mbox{\hyperlink{class_parameters}{Parameters}} }{\pageref{class_parameters}}{} \item\contentsline{section}{\mbox{\hyperlink{class_c_i_f_1_1_polygon}{Polygon}} }{\pageref{class_c_i_f_1_1_polygon}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_port}{Port}} }{\pageref{class_open_chams_1_1_port}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_port_point}{Port\+Point}} }{\pageref{class_open_chams_1_1_port_point}}{} +\item\contentsline{section}{\mbox{\hyperlink{class_port}{Port}} }{\pageref{class_port}}{} +\item\contentsline{section}{\mbox{\hyperlink{class_port_point}{Port\+Point}} }{\pageref{class_port_point}}{} \item\contentsline{section}{\mbox{\hyperlink{class_a_g_d_s_1_1_rectangle}{Rectangle}} }{\pageref{class_a_g_d_s_1_1_rectangle}}{} \item\contentsline{section}{\mbox{\hyperlink{class_s_p_i_c_e_1_1_resistor}{Resistor}} }{\pageref{class_s_p_i_c_e_1_1_resistor}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_r_slicing_node}{R\+Slicing\+Node}} }{\pageref{class_open_chams_1_1_r_slicing_node}}{} \item\contentsline{section}{\mbox{\hyperlink{class_d_t_r_1_1_rule}{Rule}} }{\pageref{class_d_t_r_1_1_rule}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_schematic}{Schematic}} }{\pageref{class_open_chams_1_1_schematic}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_simul_model}{Simul\+Model}} }{\pageref{class_open_chams_1_1_simul_model}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_sizing}{Sizing}} }{\pageref{class_open_chams_1_1_sizing}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_slicing_node}{Slicing\+Node}} }{\pageref{class_open_chams_1_1_slicing_node}}{} +\item\contentsline{section}{\mbox{\hyperlink{class_schematic}{Schematic}} }{\pageref{class_schematic}}{} +\item\contentsline{section}{\mbox{\hyperlink{class_simul_model}{Simul\+Model}} }{\pageref{class_simul_model}}{} +\item\contentsline{section}{\mbox{\hyperlink{class_sizing}{Sizing}} }{\pageref{class_sizing}}{} \item\contentsline{section}{\mbox{\hyperlink{class_s_p_i_c_e_1_1_source}{Source}} }{\pageref{class_s_p_i_c_e_1_1_source}}{} \item\contentsline{section}{\mbox{\hyperlink{class_s_p_i_c_e_1_1_spice_exception}{Spice\+Exception}} }{\pageref{class_s_p_i_c_e_1_1_spice_exception}}{} \item\contentsline{section}{\mbox{\hyperlink{class_a_g_d_s_1_1_structure}{Structure}} }{\pageref{class_a_g_d_s_1_1_structure}}{} \item\contentsline{section}{\mbox{\hyperlink{class_s_p_i_c_e_1_1_subckt}{Subckt}} }{\pageref{class_s_p_i_c_e_1_1_subckt}}{} \item\contentsline{section}{\mbox{\hyperlink{class_d_t_r_1_1_techno}{Techno}} }{\pageref{class_d_t_r_1_1_techno}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_transistor}{Transistor}} }{\pageref{class_open_chams_1_1_transistor}}{} +\item\contentsline{section}{\mbox{\hyperlink{class_transistor}{Transistor}} }{\pageref{class_transistor}}{} \item\contentsline{section}{\mbox{\hyperlink{class_s_p_i_c_e_1_1_value}{Value}} }{\pageref{class_s_p_i_c_e_1_1_value}}{} \item\contentsline{section}{\mbox{\hyperlink{class_s_p_i_c_e_1_1_voltage}{Voltage}} }{\pageref{class_s_p_i_c_e_1_1_voltage}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_v_slicing_node}{V\+Slicing\+Node}} }{\pageref{class_open_chams_1_1_v_slicing_node}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_wire}{Wire}} }{\pageref{class_open_chams_1_1_wire}}{} -\item\contentsline{section}{\mbox{\hyperlink{class_open_chams_1_1_wire_point}{Wire\+Point}} }{\pageref{class_open_chams_1_1_wire_point}}{} +\item\contentsline{section}{\mbox{\hyperlink{class_wire}{Wire}} }{\pageref{class_wire}}{} +\item\contentsline{section}{\mbox{\hyperlink{class_wire_point}{Wire\+Point}} }{\pageref{class_wire_point}}{} \end{DoxyCompactList} diff --git a/vlsisapd/doc/latex/class_a_g_d_s_1_1_element.pdf b/vlsisapd/doc/latex/class_a_g_d_s_1_1_element.pdf index dea56c0c..16fbe731 100644 Binary files a/vlsisapd/doc/latex/class_a_g_d_s_1_1_element.pdf and b/vlsisapd/doc/latex/class_a_g_d_s_1_1_element.pdf differ diff --git a/vlsisapd/doc/latex/class_a_g_d_s_1_1_rectangle.pdf b/vlsisapd/doc/latex/class_a_g_d_s_1_1_rectangle.pdf index acb4ae05..8af0862f 100644 Binary files a/vlsisapd/doc/latex/class_a_g_d_s_1_1_rectangle.pdf and b/vlsisapd/doc/latex/class_a_g_d_s_1_1_rectangle.pdf differ diff --git a/vlsisapd/doc/latex/class_bloc.tex b/vlsisapd/doc/latex/class_bloc.tex new file mode 100644 index 00000000..0cf56ee8 --- /dev/null +++ b/vlsisapd/doc/latex/class_bloc.tex @@ -0,0 +1,6 @@ +\hypertarget{class_bloc}{}\section{Bloc Class Reference} +\label{class_bloc}\index{Bloc@{Bloc}} + + +\subsection{Detailed Description} +This class describes a bloc of the placement tree. \ No newline at end of file diff --git a/vlsisapd/doc/latex/class_circuit.tex b/vlsisapd/doc/latex/class_circuit.tex new file mode 100644 index 00000000..32aa8176 --- /dev/null +++ b/vlsisapd/doc/latex/class_circuit.tex @@ -0,0 +1,6 @@ +\hypertarget{class_circuit}{}\section{Circuit Class Reference} +\label{class_circuit}\index{Circuit@{Circuit}} + + +\subsection{Detailed Description} +This class is the root class whihch means that having this object in hand allows to get/set any information contained in the Open\+Chams file parsed/drived. \ No newline at end of file diff --git a/vlsisapd/doc/latex/class_d_t_r_1_1_a_rule.pdf b/vlsisapd/doc/latex/class_d_t_r_1_1_a_rule.pdf index e2e20dc7..dc71c86f 100644 Binary files a/vlsisapd/doc/latex/class_d_t_r_1_1_a_rule.pdf and b/vlsisapd/doc/latex/class_d_t_r_1_1_a_rule.pdf differ diff --git a/vlsisapd/doc/latex/class_d_t_r_1_1_rule.pdf b/vlsisapd/doc/latex/class_d_t_r_1_1_rule.pdf index 1b06ce01..e7f8c7bb 100644 Binary files a/vlsisapd/doc/latex/class_d_t_r_1_1_rule.pdf and b/vlsisapd/doc/latex/class_d_t_r_1_1_rule.pdf differ diff --git a/vlsisapd/doc/latex/class_device.tex b/vlsisapd/doc/latex/class_device.tex new file mode 100644 index 00000000..a1b23254 --- /dev/null +++ b/vlsisapd/doc/latex/class_device.tex @@ -0,0 +1,12 @@ +\hypertarget{class_device}{}\section{Device Class Reference} +\label{class_device}\index{Device@{Device}} + + +\subsection{Detailed Description} +This class describes a \mbox{\hyperlink{class_device}{Device}}. + +A device is a leaf instance which means its model is not defined in a external file but is described inside the device. As an instance, the \mbox{\hyperlink{class_device}{Device}} inherits all \mbox{\hyperlink{class_instance}{Instance}} methods and adds specific properties\+: mos type, bulk connection and list of internal transistors. + +\begin{DoxyNote}{Note} +Althought today \mbox{\hyperlink{class_device}{Device}} object only consider Transistor\+Family devices, it will have to consider other devices, such as Capacitor when C\+H\+A\+MS project will. +\end{DoxyNote} diff --git a/vlsisapd/doc/latex/class_group.tex b/vlsisapd/doc/latex/class_group.tex new file mode 100644 index 00000000..049f4650 --- /dev/null +++ b/vlsisapd/doc/latex/class_group.tex @@ -0,0 +1,6 @@ +\hypertarget{class_group}{}\section{Group Class Reference} +\label{class_group}\index{Group@{Group}} + + +\subsection{Detailed Description} +This class describes a group of the placement tree. \ No newline at end of file diff --git a/vlsisapd/doc/latex/class_instance.tex b/vlsisapd/doc/latex/class_instance.tex new file mode 100644 index 00000000..d013b921 --- /dev/null +++ b/vlsisapd/doc/latex/class_instance.tex @@ -0,0 +1,8 @@ +\hypertarget{class_instance}{}\section{Instance Class Reference} +\label{class_instance}\index{Instance@{Instance}} + + +\subsection{Detailed Description} +This class describes an instance. + +Basicaly an instance is a subcircuit of the current (top) circuit. \ No newline at end of file diff --git a/vlsisapd/doc/latex/class_instance_point.tex b/vlsisapd/doc/latex/class_instance_point.tex new file mode 100644 index 00000000..83b27135 --- /dev/null +++ b/vlsisapd/doc/latex/class_instance_point.tex @@ -0,0 +1,6 @@ +\hypertarget{class_instance_point}{}\section{Instance\+Point Class Reference} +\label{class_instance_point}\index{Instance\+Point@{Instance\+Point}} + + +\subsection{Detailed Description} +This class describes a wire point associated to an instance\textquotesingle{}s connector. \ No newline at end of file diff --git a/vlsisapd/doc/latex/class_intermediate_point.tex b/vlsisapd/doc/latex/class_intermediate_point.tex new file mode 100644 index 00000000..e07bf698 --- /dev/null +++ b/vlsisapd/doc/latex/class_intermediate_point.tex @@ -0,0 +1,6 @@ +\hypertarget{class_intermediate_point}{}\section{Intermediate\+Point Class Reference} +\label{class_intermediate_point}\index{Intermediate\+Point@{Intermediate\+Point}} + + +\subsection{Detailed Description} +This class describes a wire point defined by its (x,y) coordinates. \ No newline at end of file diff --git a/vlsisapd/doc/latex/class_layout.tex b/vlsisapd/doc/latex/class_layout.tex new file mode 100644 index 00000000..a8c2ec22 --- /dev/null +++ b/vlsisapd/doc/latex/class_layout.tex @@ -0,0 +1,12 @@ +\hypertarget{class_layout}{}\section{Layout Class Reference} +\label{class_layout}\index{Layout@{Layout}} + + +\subsection{Detailed Description} +This class describes layout informations for an \mbox{\hyperlink{class_instance}{Instance}}. + +The \mbox{\hyperlink{class_layout}{Layout}} object is used to store all informations relative to physical layout of the instance (such as the layout style). + +\begin{DoxyNote}{Note} +The \mbox{\hyperlink{class_layout}{Layout}} object is optionnal in \mbox{\hyperlink{class_circuit}{Circuit}}. +\end{DoxyNote} diff --git a/vlsisapd/doc/latex/class_net.tex b/vlsisapd/doc/latex/class_net.tex new file mode 100644 index 00000000..281d0eba --- /dev/null +++ b/vlsisapd/doc/latex/class_net.tex @@ -0,0 +1,11 @@ +\hypertarget{class_net}{}\section{Net Class Reference} +\label{class_net}\index{Net@{Net}} +\subsection*{Data Structures} +\begin{DoxyCompactItemize} +\item +class \mbox{\hyperlink{class_net_1_1_connection}{Connection}} +\end{DoxyCompactItemize} + + +\subsection{Detailed Description} +This class describes a \mbox{\hyperlink{class_net}{Net}}. \ No newline at end of file diff --git a/vlsisapd/doc/latex/class_net_1_1_connection.tex b/vlsisapd/doc/latex/class_net_1_1_connection.tex new file mode 100644 index 00000000..7503bd4f --- /dev/null +++ b/vlsisapd/doc/latex/class_net_1_1_connection.tex @@ -0,0 +1,6 @@ +\hypertarget{class_net_1_1_connection}{}\section{Net\+:\+:Connection Class Reference} +\label{class_net_1_1_connection}\index{Net\+::\+Connection@{Net\+::\+Connection}} + + +\subsection{Detailed Description} +This class describe a \mbox{\hyperlink{class_net_1_1_connection}{Connection}} in a \mbox{\hyperlink{class_net}{Net}}. A connection is a couple (instance\+Name, connector\+Name) used to represent all the connectors linked to a net. \ No newline at end of file diff --git a/vlsisapd/doc/latex/class_netlist.tex b/vlsisapd/doc/latex/class_netlist.tex new file mode 100644 index 00000000..e7f29b6c --- /dev/null +++ b/vlsisapd/doc/latex/class_netlist.tex @@ -0,0 +1,12 @@ +\hypertarget{class_netlist}{}\section{Netlist Class Reference} +\label{class_netlist}\index{Netlist@{Netlist}} + + +\subsection{Detailed Description} +This class describes a netlist. + +A netlist contains the list of all circuit\textquotesingle{}s instances and nets. + +\begin{DoxyNote}{Note} +A \mbox{\hyperlink{class_circuit}{Circuit}} must have one and only netlist. If no netlist is defined the \mbox{\hyperlink{class_circuit}{Circuit}} cannot be driven to file. +\end{DoxyNote} diff --git a/vlsisapd/doc/latex/class_node.tex b/vlsisapd/doc/latex/class_node.tex new file mode 100644 index 00000000..6c431de5 --- /dev/null +++ b/vlsisapd/doc/latex/class_node.tex @@ -0,0 +1,8 @@ +\hypertarget{class_node}{}\section{Node Class Reference} +\label{class_node}\index{Node@{Node}} + + +\subsection{Detailed Description} +This class describes a node of the placement tree. + +This is an abstract class used to easily managed blocs and groups of the placement tree. \ No newline at end of file diff --git a/vlsisapd/doc/latex/class_open_chams_exception.tex b/vlsisapd/doc/latex/class_open_chams_exception.tex new file mode 100644 index 00000000..cffc855e --- /dev/null +++ b/vlsisapd/doc/latex/class_open_chams_exception.tex @@ -0,0 +1,6 @@ +\hypertarget{class_open_chams_exception}{}\section{Open\+Chams\+Exception Class Reference} +\label{class_open_chams_exception}\index{Open\+Chams\+Exception@{Open\+Chams\+Exception}} + + +\subsection{Detailed Description} +This class describes the exceptions throwed by the Open\+Chams library in case of errors. \ No newline at end of file diff --git a/vlsisapd/doc/latex/class_operator.tex b/vlsisapd/doc/latex/class_operator.tex new file mode 100644 index 00000000..3503f1d8 --- /dev/null +++ b/vlsisapd/doc/latex/class_operator.tex @@ -0,0 +1,11 @@ +\hypertarget{class_operator}{}\section{Operator Class Reference} +\label{class_operator}\index{Operator@{Operator}} +\subsection*{Data Structures} +\begin{DoxyCompactItemize} +\item +class \mbox{\hyperlink{class_operator_1_1_constraint}{Constraint}} +\end{DoxyCompactItemize} + + +\subsection{Detailed Description} +This class describes an operator of a sizing procedure. \ No newline at end of file diff --git a/vlsisapd/doc/latex/class_operator_1_1_constraint.tex b/vlsisapd/doc/latex/class_operator_1_1_constraint.tex new file mode 100644 index 00000000..ef070113 --- /dev/null +++ b/vlsisapd/doc/latex/class_operator_1_1_constraint.tex @@ -0,0 +1,6 @@ +\hypertarget{class_operator_1_1_constraint}{}\section{Operator\+:\+:Constraint Class Reference} +\label{class_operator_1_1_constraint}\index{Operator\+::\+Constraint@{Operator\+::\+Constraint}} + + +\subsection{Detailed Description} +This class describes a constraint. A constraint is used to set that a parameter\textquotesingle{}s value is defined relative to another parameter value or to an equation\+: device\+A.\+paramI = device\+B.\+paramJ $\ast$ factor device\+A.\+paramI = equation $\ast$ factor \ No newline at end of file diff --git a/vlsisapd/doc/latex/class_parameters.tex b/vlsisapd/doc/latex/class_parameters.tex new file mode 100644 index 00000000..20704d30 --- /dev/null +++ b/vlsisapd/doc/latex/class_parameters.tex @@ -0,0 +1,6 @@ +\hypertarget{class_parameters}{}\section{Parameters Class Reference} +\label{class_parameters}\index{Parameters@{Parameters}} + + +\subsection{Detailed Description} +This class describes a set of \mbox{\hyperlink{class_parameters}{Parameters}}. \mbox{\hyperlink{class_parameters}{Parameters}} consist in two maps associating a parameter name to a double value or a std\+::string (equation). \ No newline at end of file diff --git a/vlsisapd/doc/latex/class_port.tex b/vlsisapd/doc/latex/class_port.tex new file mode 100644 index 00000000..e7e41eee --- /dev/null +++ b/vlsisapd/doc/latex/class_port.tex @@ -0,0 +1,12 @@ +\hypertarget{class_port}{}\section{Port Class Reference} +\label{class_port}\index{Port@{Port}} + + +\subsection{Detailed Description} +This class describes port. + +A port is used by schematic to position the input/output ports of the circuit. + +\begin{DoxyNote}{Note} +Althought the \mbox{\hyperlink{class_port}{Port}} object is related to \mbox{\hyperlink{class_schematic}{Schematic}}, it is handled by \mbox{\hyperlink{class_net}{Net}} object since a port always belongs to a \mbox{\hyperlink{class_net}{Net}}. +\end{DoxyNote} diff --git a/vlsisapd/doc/latex/class_port_point.tex b/vlsisapd/doc/latex/class_port_point.tex new file mode 100644 index 00000000..68240967 --- /dev/null +++ b/vlsisapd/doc/latex/class_port_point.tex @@ -0,0 +1,6 @@ +\hypertarget{class_port_point}{}\section{Port\+Point Class Reference} +\label{class_port_point}\index{Port\+Point@{Port\+Point}} + + +\subsection{Detailed Description} +this class describes a wire point associated to a \mbox{\hyperlink{class_port}{Port}}. \ No newline at end of file diff --git a/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_capacitor.pdf b/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_capacitor.pdf index 98517096..630a84c9 100644 Binary files a/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_capacitor.pdf and b/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_capacitor.pdf differ diff --git a/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_circuit.tex b/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_circuit.tex index 7679e145..a00d2962 100644 --- a/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_circuit.tex +++ b/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_circuit.tex @@ -32,9 +32,8 @@ const strpair\+\_\+vector \& \mbox{\hyperlink{class_s_p_i_c_e_1_1_circuit_a3e6a7 \mbox{\Hypertarget{class_s_p_i_c_e_1_1_circuit_a4ee11ef79ef893c5621e0e7d26a7f9a7}\label{class_s_p_i_c_e_1_1_circuit_a4ee11ef79ef893c5621e0e7d26a7f9a7}} const strings\+\_\+map \& \mbox{\hyperlink{class_s_p_i_c_e_1_1_circuit_a4ee11ef79ef893c5621e0e7d26a7f9a7}{get\+Options}} () \begin{DoxyCompactList}\small\item\em returns the options of the circuit. \end{DoxyCompactList}\item -\mbox{\Hypertarget{class_s_p_i_c_e_1_1_circuit_a4c46676f9ead2db537a0dd963b4f08f1}\label{class_s_p_i_c_e_1_1_circuit_a4c46676f9ead2db537a0dd963b4f08f1}} const strings\+\_\+map \& \mbox{\hyperlink{class_s_p_i_c_e_1_1_circuit_a4c46676f9ead2db537a0dd963b4f08f1}{get\+Parameters}} () -\begin{DoxyCompactList}\small\item\em returns the parameters of the circuit. \end{DoxyCompactList}\item +\begin{DoxyCompactList}\small\item\em returns all circuit\textquotesingle{}s parameters. \end{DoxyCompactList}\item \mbox{\Hypertarget{class_s_p_i_c_e_1_1_circuit_ac18caa525ed386c44874ee643c88e27b}\label{class_s_p_i_c_e_1_1_circuit_ac18caa525ed386c44874ee643c88e27b}} const std\+::vector$<$ \mbox{\hyperlink{class_s_p_i_c_e_1_1_source}{Source}} $\ast$ $>$ \& \mbox{\hyperlink{class_s_p_i_c_e_1_1_circuit_ac18caa525ed386c44874ee643c88e27b}{get\+Sources}} () \begin{DoxyCompactList}\small\item\em returns the sources of the circuit. \end{DoxyCompactList}\item @@ -46,6 +45,11 @@ std\+::string \mbox{\hyperlink{class_s_p_i_c_e_1_1_circuit_ad19721dd878c04c854a7 \begin{DoxyCompactList}\small\item\em returns the title of the circuit. \end{DoxyCompactList}\item void \mbox{\hyperlink{class_s_p_i_c_e_1_1_circuit_a798df9ebd558e22c85eeceb5202e3123}{set\+Title}} (std\+::string) \begin{DoxyCompactList}\small\item\em sets the title of the circuit. \end{DoxyCompactList}\end{DoxyCompactItemize} +\subsection*{Static Public Member Functions} +\begin{DoxyCompactItemize} +\item +static \mbox{\hyperlink{class_s_p_i_c_e_1_1_circuit}{Circuit}} $\ast$ \mbox{\hyperlink{class_s_p_i_c_e_1_1_circuit_aa8294fe7d9ceddb5653d08ecae3eaf36}{read\+From\+File}} (const std\+::string \&) +\begin{DoxyCompactList}\small\item\em creates and returns a \mbox{\hyperlink{class_s_p_i_c_e_1_1_circuit}{Circuit}} object based on a database source file. \end{DoxyCompactList}\end{DoxyCompactItemize} \subsection{Detailed Description} @@ -123,18 +127,28 @@ The value is represented as a std\+::string to keep the optionnal unity. \index{S\+P\+I\+C\+E\+::\+Circuit@{S\+P\+I\+C\+E\+::\+Circuit}!add\+Parameter@{add\+Parameter}} \index{add\+Parameter@{add\+Parameter}!S\+P\+I\+C\+E\+::\+Circuit@{S\+P\+I\+C\+E\+::\+Circuit}} \subsubsection{\texorpdfstring{add\+Parameter()}{addParameter()}} -{\footnotesize\ttfamily void add\+Parameter (\begin{DoxyParamCaption}\item[{std\+::string}]{name, }\item[{std\+::string}]{value }\end{DoxyParamCaption})} +{\footnotesize\ttfamily void add\+Parameter (\begin{DoxyParamCaption}\item[{std\+::string}]{name, }\item[{std\+::string}]{value }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [inline]}} adds a parameter to the circuit. +adds an equation parameter to the circuit. + \begin{DoxyParams}{Parameters} {\em name} & the name of the parameter. \\ \hline {\em value} & the value of the parameter.\\ \hline +{\em name} & the name of the parameter. \\ +\hline +{\em equation} & the equation string of the parameter.\\ +\hline +{\em name} & the name of the parameter. \\ +\hline +{\em value} & the value of the parameter.\\ +\hline \end{DoxyParams} \begin{DoxyNote}{Note} The value is represented as a std\+::string to keep the optionnal unity. @@ -172,6 +186,34 @@ adds a subcircuit to the circuit. \begin{DoxyReturn}{Returns} the newly created \mbox{\hyperlink{class_s_p_i_c_e_1_1_subckt}{Subckt}}. \end{DoxyReturn} +\mbox{\Hypertarget{class_s_p_i_c_e_1_1_circuit_a4c46676f9ead2db537a0dd963b4f08f1}\label{class_s_p_i_c_e_1_1_circuit_a4c46676f9ead2db537a0dd963b4f08f1}} +\index{S\+P\+I\+C\+E\+::\+Circuit@{S\+P\+I\+C\+E\+::\+Circuit}!get\+Parameters@{get\+Parameters}} +\index{get\+Parameters@{get\+Parameters}!S\+P\+I\+C\+E\+::\+Circuit@{S\+P\+I\+C\+E\+::\+Circuit}} +\subsubsection{\texorpdfstring{get\+Parameters()}{getParameters()}} +{\footnotesize\ttfamily const Circuit\+::strings\+\_\+map \& get\+Parameters (\begin{DoxyParamCaption}{ }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [inline]}} + + + +returns all circuit\textquotesingle{}s parameters. + +returns the parameters of the circuit. \mbox{\Hypertarget{class_s_p_i_c_e_1_1_circuit_aa8294fe7d9ceddb5653d08ecae3eaf36}\label{class_s_p_i_c_e_1_1_circuit_aa8294fe7d9ceddb5653d08ecae3eaf36}} +\index{S\+P\+I\+C\+E\+::\+Circuit@{S\+P\+I\+C\+E\+::\+Circuit}!read\+From\+File@{read\+From\+File}} +\index{read\+From\+File@{read\+From\+File}!S\+P\+I\+C\+E\+::\+Circuit@{S\+P\+I\+C\+E\+::\+Circuit}} +\subsubsection{\texorpdfstring{read\+From\+File()}{readFromFile()}} +{\footnotesize\ttfamily \mbox{\hyperlink{class_s_p_i_c_e_1_1_circuit}{Circuit}} $\ast$ read\+From\+File (\begin{DoxyParamCaption}\item[{const std\+::string \&}]{filename }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [static]}} + + + +creates and returns a \mbox{\hyperlink{class_s_p_i_c_e_1_1_circuit}{Circuit}} object based on a database source file. + + +\begin{DoxyParams}{Parameters} +{\em file\+Path} & the source file name.\\ +\hline +\end{DoxyParams} +\begin{DoxyReturn}{Returns} +the newly created \mbox{\hyperlink{class_s_p_i_c_e_1_1_circuit}{Circuit}}. +\end{DoxyReturn} \mbox{\Hypertarget{class_s_p_i_c_e_1_1_circuit_a798df9ebd558e22c85eeceb5202e3123}\label{class_s_p_i_c_e_1_1_circuit_a798df9ebd558e22c85eeceb5202e3123}} \index{S\+P\+I\+C\+E\+::\+Circuit@{S\+P\+I\+C\+E\+::\+Circuit}!set\+Title@{set\+Title}} \index{set\+Title@{set\+Title}!S\+P\+I\+C\+E\+::\+Circuit@{S\+P\+I\+C\+E\+::\+Circuit}} diff --git a/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_current.pdf b/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_current.pdf index 831db527..0c2b5ea5 100644 Binary files a/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_current.pdf and b/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_current.pdf differ diff --git a/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_instance.pdf b/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_instance.pdf index 7a14264c..402d2c6b 100644 Binary files a/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_instance.pdf and b/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_instance.pdf differ diff --git a/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_instance.tex b/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_instance.tex index b4226aaf..bb0ab748 100644 --- a/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_instance.tex +++ b/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_instance.tex @@ -12,10 +12,9 @@ Inheritance diagram for Instance\+:\begin{figure}[H] void \mbox{\hyperlink{class_s_p_i_c_e_1_1_instance_af9aeca34e780851a2b024df7c5ff5b54}{add\+Connector}} (std\+::string connector) \begin{DoxyCompactList}\small\item\em adds a connector to the instance. \end{DoxyCompactList}\item void \mbox{\hyperlink{class_s_p_i_c_e_1_1_instance_a8d69bbbea5ece0949e100c464e412f20}{add\+Parameter}} (std\+::string name, std\+::string value) -\begin{DoxyCompactList}\small\item\em add a parameter to the instance. \end{DoxyCompactList}\item -\mbox{\Hypertarget{class_s_p_i_c_e_1_1_instance_acce8940edeaa3d79c522006f987e0711}\label{class_s_p_i_c_e_1_1_instance_acce8940edeaa3d79c522006f987e0711}} +\begin{DoxyCompactList}\small\item\em adds a parameter to the instance. \end{DoxyCompactList}\item const std\+::vector$<$ std\+::string $>$ \& \mbox{\hyperlink{class_s_p_i_c_e_1_1_instance_acce8940edeaa3d79c522006f987e0711}{get\+Connectors}} () -\begin{DoxyCompactList}\small\item\em returns the connectors of the instance. \end{DoxyCompactList}\item +\begin{DoxyCompactList}\small\item\em returns the map of instance\textquotesingle{}s connectors. \end{DoxyCompactList}\item \mbox{\Hypertarget{class_s_p_i_c_e_1_1_instance_afc74cbe93df9c473a53db83a325f8f9d}\label{class_s_p_i_c_e_1_1_instance_afc74cbe93df9c473a53db83a325f8f9d}} std\+::string \mbox{\hyperlink{class_s_p_i_c_e_1_1_instance_afc74cbe93df9c473a53db83a325f8f9d}{get\+Model}} () \begin{DoxyCompactList}\small\item\em returns the model of the instance. \end{DoxyCompactList}\item @@ -51,6 +50,12 @@ creates a new instance. \hline {\em model} & the model of the instance. \\ \hline +{\em netlist} & the netlist to which the instance belongs.\\ +\hline +{\em name} & the name of the instance. \\ +\hline +{\em model} & the model of the instance. \\ +\hline \end{DoxyParams} @@ -67,6 +72,8 @@ adds a connector to the instance. \begin{DoxyParams}{Parameters} +{\em name} & the name of the connector.\\ +\hline {\em connector} & the connector to add. \\ \hline \end{DoxyParams} @@ -74,20 +81,38 @@ adds a connector to the instance. \index{S\+P\+I\+C\+E\+::\+Instance@{S\+P\+I\+C\+E\+::\+Instance}!add\+Parameter@{add\+Parameter}} \index{add\+Parameter@{add\+Parameter}!S\+P\+I\+C\+E\+::\+Instance@{S\+P\+I\+C\+E\+::\+Instance}} \subsubsection{\texorpdfstring{add\+Parameter()}{addParameter()}} -{\footnotesize\ttfamily void add\+Parameter (\begin{DoxyParamCaption}\item[{std\+::string}]{name, }\item[{std\+::string}]{value }\end{DoxyParamCaption})} +{\footnotesize\ttfamily void add\+Parameter (\begin{DoxyParamCaption}\item[{std\+::string}]{name, }\item[{std\+::string}]{value }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [inline]}} -add a parameter to the instance. +adds a parameter to the instance. + +add a parameter to the instance. + +adds an equation parameter to the instance. \begin{DoxyParams}{Parameters} {\em name} & the name of the parameter. \\ \hline -{\em value} & the value of the parameter. \\ +{\em value} & the value of the parameter.\\ +\hline +{\em name} & the name of the parameter. \\ +\hline +{\em equation} & the equation string of the parameter. \\ \hline \end{DoxyParams} -\mbox{\Hypertarget{class_s_p_i_c_e_1_1_instance_a324e4ff99afdcd5972d8c57461d12ef5}\label{class_s_p_i_c_e_1_1_instance_a324e4ff99afdcd5972d8c57461d12ef5}} +\mbox{\Hypertarget{class_s_p_i_c_e_1_1_instance_acce8940edeaa3d79c522006f987e0711}\label{class_s_p_i_c_e_1_1_instance_acce8940edeaa3d79c522006f987e0711}} +\index{S\+P\+I\+C\+E\+::\+Instance@{S\+P\+I\+C\+E\+::\+Instance}!get\+Connectors@{get\+Connectors}} +\index{get\+Connectors@{get\+Connectors}!S\+P\+I\+C\+E\+::\+Instance@{S\+P\+I\+C\+E\+::\+Instance}} +\subsubsection{\texorpdfstring{get\+Connectors()}{getConnectors()}} +{\footnotesize\ttfamily const std\+::vector$<$ std\+::string $>$ \& get\+Connectors (\begin{DoxyParamCaption}{ }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [inline]}} + + + +returns the map of instance\textquotesingle{}s connectors. + +returns the connectors of the instance. \mbox{\Hypertarget{class_s_p_i_c_e_1_1_instance_a324e4ff99afdcd5972d8c57461d12ef5}\label{class_s_p_i_c_e_1_1_instance_a324e4ff99afdcd5972d8c57461d12ef5}} \index{S\+P\+I\+C\+E\+::\+Instance@{S\+P\+I\+C\+E\+::\+Instance}!get\+Parameter\+Value@{get\+Parameter\+Value}} \index{get\+Parameter\+Value@{get\+Parameter\+Value}!S\+P\+I\+C\+E\+::\+Instance@{S\+P\+I\+C\+E\+::\+Instance}} \subsubsection{\texorpdfstring{get\+Parameter\+Value()}{getParameterValue()}} diff --git a/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_mosfet.pdf b/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_mosfet.pdf index c6119829..ad52d283 100644 Binary files a/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_mosfet.pdf and b/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_mosfet.pdf differ diff --git a/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_resistor.pdf b/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_resistor.pdf index 92ba0f0f..97637e0d 100644 Binary files a/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_resistor.pdf and b/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_resistor.pdf differ diff --git a/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_source.pdf b/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_source.pdf index ce3a49fe..d0d65b47 100644 Binary files a/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_source.pdf and b/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_source.pdf differ diff --git a/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_voltage.pdf b/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_voltage.pdf index 6bb7437d..19c98181 100644 Binary files a/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_voltage.pdf and b/vlsisapd/doc/latex/class_s_p_i_c_e_1_1_voltage.pdf differ diff --git a/vlsisapd/doc/latex/class_schematic.tex b/vlsisapd/doc/latex/class_schematic.tex new file mode 100644 index 00000000..6ec348b7 --- /dev/null +++ b/vlsisapd/doc/latex/class_schematic.tex @@ -0,0 +1,17 @@ +\hypertarget{class_schematic}{}\section{Schematic Class Reference} +\label{class_schematic}\index{Schematic@{Schematic}} +\subsection*{Data Structures} +\begin{DoxyCompactItemize} +\item +class \mbox{\hyperlink{class_schematic_1_1_infos}{Infos}} +\end{DoxyCompactItemize} + + +\subsection{Detailed Description} +This class describes schematic informations. + +The \mbox{\hyperlink{class_schematic}{Schematic}} object is used to store all informations relative to schematic of the circuit. + +\begin{DoxyNote}{Note} +The \mbox{\hyperlink{class_schematic}{Schematic}} object is optionnal in \mbox{\hyperlink{class_circuit}{Circuit}}. +\end{DoxyNote} diff --git a/vlsisapd/doc/latex/class_schematic_1_1_infos.tex b/vlsisapd/doc/latex/class_schematic_1_1_infos.tex new file mode 100644 index 00000000..66793190 --- /dev/null +++ b/vlsisapd/doc/latex/class_schematic_1_1_infos.tex @@ -0,0 +1,6 @@ +\hypertarget{class_schematic_1_1_infos}{}\section{Schematic\+:\+:Infos Class Reference} +\label{class_schematic_1_1_infos}\index{Schematic\+::\+Infos@{Schematic\+::\+Infos}} + + +\subsection{Detailed Description} +This class describes schematic informations for an instance. It contains x and y coordinates and the orientation of the instance. \ No newline at end of file diff --git a/vlsisapd/doc/latex/class_simul_model.tex b/vlsisapd/doc/latex/class_simul_model.tex new file mode 100644 index 00000000..6b408687 --- /dev/null +++ b/vlsisapd/doc/latex/class_simul_model.tex @@ -0,0 +1,6 @@ +\hypertarget{class_simul_model}{}\section{Simul\+Model Class Reference} +\label{class_simul_model}\index{Simul\+Model@{Simul\+Model}} + + +\subsection{Detailed Description} +This class describes a simulation model used by \mbox{\hyperlink{class_operator}{Operator}} in \mbox{\hyperlink{class_sizing}{Sizing}} procedure. \ No newline at end of file diff --git a/vlsisapd/doc/latex/class_sizing.tex b/vlsisapd/doc/latex/class_sizing.tex new file mode 100644 index 00000000..eceecf29 --- /dev/null +++ b/vlsisapd/doc/latex/class_sizing.tex @@ -0,0 +1,12 @@ +\hypertarget{class_sizing}{}\section{Sizing Class Reference} +\label{class_sizing}\index{Sizing@{Sizing}} + + +\subsection{Detailed Description} +This class describes a sizing procedure. + +The \mbox{\hyperlink{class_sizing}{Sizing}} object is used to store all informations relative to sizing procedure as we defined it in {\bfseries C\+H\+A\+MS}. + +\begin{DoxyNote}{Note} +The \mbox{\hyperlink{class_sizing}{Sizing}} object is optionnal in \mbox{\hyperlink{class_circuit}{Circuit}}. +\end{DoxyNote} diff --git a/vlsisapd/doc/latex/class_transistor.tex b/vlsisapd/doc/latex/class_transistor.tex new file mode 100644 index 00000000..b69a2328 --- /dev/null +++ b/vlsisapd/doc/latex/class_transistor.tex @@ -0,0 +1,8 @@ +\hypertarget{class_transistor}{}\section{Transistor Class Reference} +\label{class_transistor}\index{Transistor@{Transistor}} + + +\subsection{Detailed Description} +This class describes a \mbox{\hyperlink{class_transistor}{Transistor}}. + +The transistor object is used to describe the inside of a \mbox{\hyperlink{class_device}{Device}}. The goal is to explicit the connection between the transistor and the device\textquotesingle{}s nets. \ No newline at end of file diff --git a/vlsisapd/doc/latex/class_wire.tex b/vlsisapd/doc/latex/class_wire.tex new file mode 100644 index 00000000..c96d6372 --- /dev/null +++ b/vlsisapd/doc/latex/class_wire.tex @@ -0,0 +1,17 @@ +\hypertarget{class_wire}{}\section{Wire Class Reference} +\label{class_wire}\index{Wire@{Wire}} + + +\subsection{Detailed Description} +This class describes wire. + +A wire is used by schematic to the connections between instances. It is defined by\+: +\begin{DoxyItemize} +\item a start point (\mbox{\hyperlink{class_instance_point}{Instance\+Point}} or \mbox{\hyperlink{class_port_point}{Port\+Point}}), +\item a end point (\mbox{\hyperlink{class_instance_point}{Instance\+Point}} or \mbox{\hyperlink{class_port_point}{Port\+Point}}), +\item a list of \mbox{\hyperlink{class_intermediate_point}{Intermediate\+Point}}, this list may be empty. +\end{DoxyItemize} + +\begin{DoxyNote}{Note} +Althought the \mbox{\hyperlink{class_wire}{Wire}} object is related to \mbox{\hyperlink{class_schematic}{Schematic}}, it is handled by \mbox{\hyperlink{class_net}{Net}} object since a wire is always associated to a \mbox{\hyperlink{class_net}{Net}}. +\end{DoxyNote} diff --git a/vlsisapd/doc/latex/class_wire_point.tex b/vlsisapd/doc/latex/class_wire_point.tex new file mode 100644 index 00000000..779e6f84 --- /dev/null +++ b/vlsisapd/doc/latex/class_wire_point.tex @@ -0,0 +1,6 @@ +\hypertarget{class_wire_point}{}\section{Wire\+Point Class Reference} +\label{class_wire_point}\index{Wire\+Point@{Wire\+Point}} + + +\subsection{Detailed Description} +This class describes wire point. A wire point is an abstract object used to define all \char`\"{}direction changing\char`\"{} points of a wire. \ No newline at end of file diff --git a/vlsisapd/doc/latex/hierarchy.tex b/vlsisapd/doc/latex/hierarchy.tex index 920308bf..d98a1aa1 100644 --- a/vlsisapd/doc/latex/hierarchy.tex +++ b/vlsisapd/doc/latex/hierarchy.tex @@ -1,67 +1,48 @@ \section{Class Hierarchy} This inheritance list is sorted roughly, but not completely, alphabetically\+:\begin{DoxyCompactList} +\item \contentsline{section}{Bloc}{\pageref{class_bloc}}{} \item \contentsline{section}{Circuit}{\pageref{class_c_i_f_1_1_circuit}}{} -\item \contentsline{section}{Circuit}{\pageref{class_open_chams_1_1_circuit}}{} \item \contentsline{section}{Circuit}{\pageref{class_s_p_i_c_e_1_1_circuit}}{} -\item \contentsline{section}{Net\+:\+:Connection}{\pageref{class_open_chams_1_1_net_1_1_connection}}{} -\item \contentsline{section}{Operator\+:\+:Constraint}{\pageref{class_open_chams_1_1_operator_1_1_constraint}}{} +\item \contentsline{section}{Circuit}{\pageref{class_circuit}}{} +\item \contentsline{section}{Net\+:\+:Connection}{\pageref{class_net_1_1_connection}}{} +\item \contentsline{section}{Operator\+:\+:Constraint}{\pageref{class_operator_1_1_constraint}}{} +\item \contentsline{section}{Device}{\pageref{class_device}}{} \item \contentsline{section}{D\+T\+R\+Exception}{\pageref{class_d_t_r_1_1_d_t_r_exception}}{} \item \contentsline{section}{Element}{\pageref{class_a_g_d_s_1_1_element}}{} \begin{DoxyCompactList} \item \contentsline{section}{Rectangle}{\pageref{class_a_g_d_s_1_1_rectangle}}{} \end{DoxyCompactList} -\item \contentsline{section}{Equation}{\pageref{class_open_chams_1_1_equation}}{} -\begin{DoxyCompactList} -\item \contentsline{section}{D\+DP}{\pageref{class_open_chams_1_1_d_d_p}}{} -\item \contentsline{section}{Designer\+Cstr\+OC}{\pageref{class_open_chams_1_1_designer_cstr_o_c}}{} -\item \contentsline{section}{High\+Level\+Cstr}{\pageref{class_open_chams_1_1_high_level_cstr}}{} -\item \contentsline{section}{N\+R\+C\+Cstr}{\pageref{class_open_chams_1_1_n_r_c_cstr}}{} -\end{DoxyCompactList} -\item \contentsline{section}{Schematic\+:\+:Infos}{\pageref{class_open_chams_1_1_schematic_1_1_infos}}{} -\item \contentsline{section}{Instance}{\pageref{class_open_chams_1_1_instance}}{} -\begin{DoxyCompactList} -\item \contentsline{section}{Device}{\pageref{class_open_chams_1_1_device}}{} -\end{DoxyCompactList} +\item \contentsline{section}{Group}{\pageref{class_group}}{} +\item \contentsline{section}{Schematic\+:\+:Infos}{\pageref{class_schematic_1_1_infos}}{} \item \contentsline{section}{Instance}{\pageref{class_s_p_i_c_e_1_1_instance}}{} \begin{DoxyCompactList} \item \contentsline{section}{Capacitor}{\pageref{class_s_p_i_c_e_1_1_capacitor}}{} \item \contentsline{section}{Mosfet}{\pageref{class_s_p_i_c_e_1_1_mosfet}}{} \item \contentsline{section}{Resistor}{\pageref{class_s_p_i_c_e_1_1_resistor}}{} \end{DoxyCompactList} -\item \contentsline{section}{Layout}{\pageref{class_open_chams_1_1_layout}}{} +\item \contentsline{section}{Instance}{\pageref{class_instance}}{} +\item \contentsline{section}{Instance\+Point}{\pageref{class_instance_point}}{} +\item \contentsline{section}{Intermediate\+Point}{\pageref{class_intermediate_point}}{} +\item \contentsline{section}{Layout}{\pageref{class_layout}}{} \item \contentsline{section}{Library}{\pageref{class_a_g_d_s_1_1_library}}{} -\item \contentsline{section}{map\+\_\+item$<$ Key, Val $>$}{\pageref{struct_open_chams_1_1map__item}}{} \item \contentsline{section}{map\+\_\+item$<$ Key, Val $>$}{\pageref{struct_s_p_i_c_e_1_1map__item}}{} \item \contentsline{section}{Name}{\pageref{class_name}}{} -\item \contentsline{section}{Net}{\pageref{class_open_chams_1_1_net}}{} -\item \contentsline{section}{Netlist}{\pageref{class_open_chams_1_1_netlist}}{} -\item \contentsline{section}{Node}{\pageref{class_open_chams_1_1_node}}{} -\begin{DoxyCompactList} -\item \contentsline{section}{Bloc}{\pageref{class_open_chams_1_1_bloc}}{} -\item \contentsline{section}{Group}{\pageref{class_open_chams_1_1_group}}{} -\end{DoxyCompactList} -\item \contentsline{section}{Open\+Chams\+Exception}{\pageref{class_open_chams_1_1_open_chams_exception}}{} -\item \contentsline{section}{Operator}{\pageref{class_open_chams_1_1_operator}}{} -\item \contentsline{section}{Parameters}{\pageref{class_open_chams_1_1_parameters}}{} +\item \contentsline{section}{Net}{\pageref{class_net}}{} +\item \contentsline{section}{Netlist}{\pageref{class_netlist}}{} +\item \contentsline{section}{Node}{\pageref{class_node}}{} +\item \contentsline{section}{Open\+Chams\+Exception}{\pageref{class_open_chams_exception}}{} +\item \contentsline{section}{Operator}{\pageref{class_operator}}{} +\item \contentsline{section}{Parameters}{\pageref{class_parameters}}{} \item \contentsline{section}{Polygon}{\pageref{class_c_i_f_1_1_polygon}}{} -\item \contentsline{section}{Port}{\pageref{class_open_chams_1_1_port}}{} +\item \contentsline{section}{Port}{\pageref{class_port}}{} +\item \contentsline{section}{Port\+Point}{\pageref{class_port_point}}{} \item \contentsline{section}{Rule}{\pageref{class_d_t_r_1_1_rule}}{} \begin{DoxyCompactList} \item \contentsline{section}{A\+Rule}{\pageref{class_d_t_r_1_1_a_rule}}{} \end{DoxyCompactList} -\item \contentsline{section}{Schematic}{\pageref{class_open_chams_1_1_schematic}}{} -\item \contentsline{section}{Simul\+Model}{\pageref{class_open_chams_1_1_simul_model}}{} -\item \contentsline{section}{Sizing}{\pageref{class_open_chams_1_1_sizing}}{} -\item \contentsline{section}{Slicing\+Node}{\pageref{class_open_chams_1_1_slicing_node}}{} -\begin{DoxyCompactList} -\item \contentsline{section}{D\+Slicing\+Node}{\pageref{class_open_chams_1_1_d_slicing_node}}{} -\item \contentsline{section}{H\+V\+Slicing\+Node}{\pageref{class_open_chams_1_1_h_v_slicing_node}}{} -\begin{DoxyCompactList} -\item \contentsline{section}{H\+Slicing\+Node}{\pageref{class_open_chams_1_1_h_slicing_node}}{} -\item \contentsline{section}{V\+Slicing\+Node}{\pageref{class_open_chams_1_1_v_slicing_node}}{} -\end{DoxyCompactList} -\item \contentsline{section}{R\+Slicing\+Node}{\pageref{class_open_chams_1_1_r_slicing_node}}{} -\end{DoxyCompactList} +\item \contentsline{section}{Schematic}{\pageref{class_schematic}}{} +\item \contentsline{section}{Simul\+Model}{\pageref{class_simul_model}}{} +\item \contentsline{section}{Sizing}{\pageref{class_sizing}}{} \item \contentsline{section}{Source}{\pageref{class_s_p_i_c_e_1_1_source}}{} \begin{DoxyCompactList} \item \contentsline{section}{Current}{\pageref{class_s_p_i_c_e_1_1_current}}{} @@ -71,13 +52,8 @@ This inheritance list is sorted roughly, but not completely, alphabetically\+:\b \item \contentsline{section}{Structure}{\pageref{class_a_g_d_s_1_1_structure}}{} \item \contentsline{section}{Subckt}{\pageref{class_s_p_i_c_e_1_1_subckt}}{} \item \contentsline{section}{Techno}{\pageref{class_d_t_r_1_1_techno}}{} -\item \contentsline{section}{Transistor}{\pageref{class_open_chams_1_1_transistor}}{} +\item \contentsline{section}{Transistor}{\pageref{class_transistor}}{} \item \contentsline{section}{Value}{\pageref{class_s_p_i_c_e_1_1_value}}{} -\item \contentsline{section}{Wire}{\pageref{class_open_chams_1_1_wire}}{} -\item \contentsline{section}{Wire\+Point}{\pageref{class_open_chams_1_1_wire_point}}{} -\begin{DoxyCompactList} -\item \contentsline{section}{Instance\+Point}{\pageref{class_open_chams_1_1_instance_point}}{} -\item \contentsline{section}{Intermediate\+Point}{\pageref{class_open_chams_1_1_intermediate_point}}{} -\item \contentsline{section}{Port\+Point}{\pageref{class_open_chams_1_1_port_point}}{} -\end{DoxyCompactList} +\item \contentsline{section}{Wire}{\pageref{class_wire}}{} +\item \contentsline{section}{Wire\+Point}{\pageref{class_wire_point}}{} \end{DoxyCompactList} diff --git a/vlsisapd/doc/latex/openchams.tex b/vlsisapd/doc/latex/openchams.tex index 0757bd32..ccc5b1d5 100644 --- a/vlsisapd/doc/latex/openchams.tex +++ b/vlsisapd/doc/latex/openchams.tex @@ -6,272 +6,50 @@ The database has many objects that can be arranged in five categories\+: \begin{DoxyItemize} \item General \begin{DoxyItemize} -\item \mbox{\hyperlink{class_open_chams_1_1_circuit}{Open\+Chams\+::\+Circuit}} +\item Open\+Chams\+::\+Circuit \item Open\+Chams\+::\+Name -\item \mbox{\hyperlink{class_open_chams_1_1_open_chams_exception}{Open\+Chams\+::\+Open\+Chams\+Exception}} +\item Open\+Chams\+::\+Open\+Chams\+Exception \end{DoxyItemize} -\item Netlist +\item \mbox{\hyperlink{class_netlist}{Netlist}} \begin{DoxyItemize} -\item \mbox{\hyperlink{class_open_chams_1_1_netlist}{Open\+Chams\+::\+Netlist}} -\item \mbox{\hyperlink{class_open_chams_1_1_instance}{Open\+Chams\+::\+Instance}} -\item \mbox{\hyperlink{class_open_chams_1_1_device}{Open\+Chams\+::\+Device}} -\item \mbox{\hyperlink{class_open_chams_1_1_transistor}{Open\+Chams\+::\+Transistor}} -\item \mbox{\hyperlink{class_open_chams_1_1_parameters}{Open\+Chams\+::\+Parameters}} -\item \mbox{\hyperlink{class_open_chams_1_1_net}{Open\+Chams\+::\+Net}} +\item Open\+Chams\+::\+Netlist +\item Open\+Chams\+::\+Instance +\item Open\+Chams\+::\+Device +\item Open\+Chams\+::\+Transistor +\item Open\+Chams\+::\+Parameters +\item Open\+Chams\+::\+Net \end{DoxyItemize} -\item Sizing +\item \mbox{\hyperlink{class_sizing}{Sizing}} \begin{DoxyItemize} -\item \mbox{\hyperlink{class_open_chams_1_1_sizing}{Open\+Chams\+::\+Sizing}} -\item \mbox{\hyperlink{class_open_chams_1_1_operator}{Open\+Chams\+::\+Operator}} -\item \mbox{\hyperlink{class_open_chams_1_1_simul_model}{Open\+Chams\+::\+Simul\+Model}} +\item Open\+Chams\+::\+Sizing +\item Open\+Chams\+::\+Operator +\item Open\+Chams\+::\+Simul\+Model \end{DoxyItemize} -\item Schematic +\item \mbox{\hyperlink{class_schematic}{Schematic}} \begin{DoxyItemize} -\item \mbox{\hyperlink{class_open_chams_1_1_schematic}{Open\+Chams\+::\+Schematic}} -\item \mbox{\hyperlink{class_open_chams_1_1_port}{Open\+Chams\+::\+Port}} -\item \mbox{\hyperlink{class_open_chams_1_1_wire}{Open\+Chams\+::\+Wire}} -\item \mbox{\hyperlink{class_open_chams_1_1_wire_point}{Open\+Chams\+::\+Wire\+Point}} -\item \mbox{\hyperlink{class_open_chams_1_1_instance_point}{Open\+Chams\+::\+Instance\+Point}} -\item \mbox{\hyperlink{class_open_chams_1_1_port_point}{Open\+Chams\+::\+Port\+Point}} -\item \mbox{\hyperlink{class_open_chams_1_1_intermediate_point}{Open\+Chams\+::\+Intermediate\+Point}} +\item Open\+Chams\+::\+Schematic +\item Open\+Chams\+::\+Port +\item Open\+Chams\+::\+Wire +\item Open\+Chams\+::\+Wire\+Point +\item Open\+Chams\+::\+Instance\+Point +\item Open\+Chams\+::\+Port\+Point +\item Open\+Chams\+::\+Intermediate\+Point \end{DoxyItemize} -\item Layout +\item \mbox{\hyperlink{class_layout}{Layout}} \begin{DoxyItemize} -\item \mbox{\hyperlink{class_open_chams_1_1_layout}{Open\+Chams\+::\+Layout}} -\item \mbox{\hyperlink{class_open_chams_1_1_node}{Open\+Chams\+::\+Node}} -\item \mbox{\hyperlink{class_open_chams_1_1_bloc}{Open\+Chams\+::\+Bloc}} -\item \mbox{\hyperlink{class_open_chams_1_1_group}{Open\+Chams\+::\+Group}} +\item Open\+Chams\+::\+Layout +\item Open\+Chams\+::\+Node +\item Open\+Chams\+::\+Bloc +\item Open\+Chams\+::\+Group \end{DoxyItemize} \end{DoxyItemize}\hypertarget{openchams_openChamsParser}{}\subsection{Using the parser}\label{openchams_openChamsParser} -Simply load an O\+P\+E\+N\+C\+H\+A\+MS file using the static function \mbox{\hyperlink{class_open_chams_1_1_circuit_ad0aa3183bdea59e62f69c295026b7fe7}{Open\+Chams\+::\+Circuit\+::read\+From\+File()}} and then get the netlist object (\mbox{\hyperlink{class_open_chams_1_1_circuit_a4085d6a7b6958ffdd7ab5df7e6d6e53f}{Open\+Chams\+::\+Circuit\+::get\+Netlist()}}) or the sizing procedure (\mbox{\hyperlink{class_open_chams_1_1_circuit_a0ce52bc8747f684ec0123faa8ff97b6d}{Open\+Chams\+::\+Circuit\+::get\+Sizing()}}, might be N\+U\+LL) or any other useful information (see \mbox{\hyperlink{class_open_chams_1_1_circuit}{Open\+Chams\+::\+Circuit}}).\hypertarget{openchams_openChamsDriver}{}\subsection{Using the driver}\label{openchams_openChamsDriver} -Using the driver is very simple, user has to create an \mbox{\hyperlink{class_open_chams_1_1_circuit}{Open\+Chams\+::\+Circuit}} object and simply add \mbox{\hyperlink{class_open_chams_1_1_netlist}{Open\+Chams\+::\+Netlist}} (mandatory) and \mbox{\hyperlink{class_open_chams_1_1_sizing}{Open\+Chams\+::\+Sizing}} (optionnal) or \mbox{\hyperlink{class_open_chams_1_1_schematic}{Open\+Chams\+::\+Schematic}} (optionnal) or \mbox{\hyperlink{class_open_chams_1_1_layout}{Open\+Chams\+::\+Layout}} (optinnal) to it. Finally use the \mbox{\hyperlink{class_open_chams_1_1_circuit_a2eb07935ec946a07edcee2255b781193}{Open\+Chams\+::\+Circuit\+::write\+To\+File()}} method to dump the database to file.\hypertarget{openchams_openChamsExamples}{}\section{Examples}\label{openchams_openChamsExamples} +Simply load an O\+P\+E\+N\+C\+H\+A\+MS file using the static function Open\+Chams\+::\+Circuit\+::read\+From\+File() and then get the netlist object (Open\+Chams\+::\+Circuit\+::get\+Netlist()) or the sizing procedure (Open\+Chams\+::\+Circuit\+::get\+Sizing(), might be N\+U\+LL) or any other useful information (see Open\+Chams\+::\+Circuit).\hypertarget{openchams_openChamsDriver}{}\subsection{Using the driver}\label{openchams_openChamsDriver} +Using the driver is very simple, user has to create an Open\+Chams\+::\+Circuit object and simply add Open\+Chams\+::\+Netlist (mandatory) and Open\+Chams\+::\+Sizing (optionnal) or Open\+Chams\+::\+Schematic (optionnal) or Open\+Chams\+::\+Layout (optinnal) to it. Finally use the Open\+Chams\+::\+Circuit\+::write\+To\+File() method to dump the database to file.\hypertarget{openchams_openChamsExamples}{}\section{Examples}\label{openchams_openChamsExamples} As said is the global presentation, V\+L\+SI S\+A\+PD project provides C++ libraries and Python modules for each supported format. In this section we present simple code examples to parse and drive a O\+P\+E\+N\+C\+H\+A\+MS file using C++ or Python. The O\+P\+E\+N\+C\+H\+A\+MS files considered are the same for all examples\+: {\ttfamily inverter.\+xml} and {\ttfamily buffer.\+xml} \begin{DoxyCodeInclude} - -<\textcolor{keywordtype}{circuit} \textcolor{keyword}{name}=\textcolor{stringliteral}{"inverter"} \textcolor{keyword}{techno}=\textcolor{stringliteral}{"myTech"}> - <\textcolor{keywordtype}{parameters}> - <\textcolor{keywordtype}{parameter} \textcolor{keyword}{name}=\textcolor{stringliteral}{"temp"} \textcolor{keyword}{value}=\textcolor{stringliteral}{"27.0"}/> - <\textcolor{keywordtype}{parameter} \textcolor{keyword}{name}=\textcolor{stringliteral}{"Vdd"} \textcolor{keyword}{value}=\textcolor{stringliteral}{"1.2"}/> - <\textcolor{keywordtype}{parameter} \textcolor{keyword}{name}=\textcolor{stringliteral}{"Vss"} \textcolor{keyword}{value}=\textcolor{stringliteral}{"0.0"}/> - <\textcolor{keywordtype}{parameter} \textcolor{keyword}{name}=\textcolor{stringliteral}{"L"} \textcolor{keyword}{value}=\textcolor{stringliteral}{"0.10e-6"}/> - <\textcolor{keywordtype}{parameter} \textcolor{keyword}{name}=\textcolor{stringliteral}{"Ids"} \textcolor{keyword}{value}=\textcolor{stringliteral}{"30e-6"}/> - <\textcolor{keywordtype}{parameter} \textcolor{keyword}{name}=\textcolor{stringliteral}{"Veg"} \textcolor{keyword}{value}=\textcolor{stringliteral}{"0.12"}/> - <\textcolor{keywordtype}{parameterEq} \textcolor{keyword}{name}=\textcolor{stringliteral}{"complex"} \textcolor{keyword}{equation}=\textcolor{stringliteral}{"myEq"}/> - - <\textcolor{keywordtype}{netlist}> - <\textcolor{keywordtype}{instances}> - <\textcolor{keywordtype}{instance} \textcolor{keyword}{name}=\textcolor{stringliteral}{"nmos1"} \textcolor{keyword}{model}=\textcolor{stringliteral}{"Transistor"} \textcolor{keyword}{order}=\textcolor{stringliteral}{"1"} \textcolor{keyword}{mostype}=\textcolor{stringliteral}{"NMOS"} \textcolor{keyword}{sourceBulkConnected}=\textcolor{stringliteral}{"True"}> - <\textcolor{keywordtype}{connectors}> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"G"}/> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"D"}/> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"S"}/> - - <\textcolor{keywordtype}{transistors}> - <\textcolor{keywordtype}{transistor} \textcolor{keyword}{name}=\textcolor{stringliteral}{"m1"}> - <\textcolor{keywordtype}{connection} \textcolor{keyword}{gate}=\textcolor{stringliteral}{"G"} \textcolor{keyword}{source}=\textcolor{stringliteral}{"S"} \textcolor{keyword}{drain}=\textcolor{stringliteral}{"D"} \textcolor{keyword}{bulk}=\textcolor{stringliteral}{"S"}/> - - - - <\textcolor{keywordtype}{instance} \textcolor{keyword}{name}=\textcolor{stringliteral}{"pmos1"} \textcolor{keyword}{model}=\textcolor{stringliteral}{"Transistor"} \textcolor{keyword}{order}=\textcolor{stringliteral}{"2"} \textcolor{keyword}{mostype}=\textcolor{stringliteral}{"PMOS"} \textcolor{keyword}{sourceBulkConnected}=\textcolor{stringliteral}{"True"}> - <\textcolor{keywordtype}{connectors}> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"G"}/> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"D"}/> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"S"}/> - - <\textcolor{keywordtype}{transistors}> - <\textcolor{keywordtype}{transistor} \textcolor{keyword}{name}=\textcolor{stringliteral}{"m1"}> - <\textcolor{keywordtype}{connection} \textcolor{keyword}{gate}=\textcolor{stringliteral}{"G"} \textcolor{keyword}{source}=\textcolor{stringliteral}{"S"} \textcolor{keyword}{drain}=\textcolor{stringliteral}{"D"} \textcolor{keyword}{bulk}=\textcolor{stringliteral}{"S"}/> - - - - - <\textcolor{keywordtype}{nets}> - <\textcolor{keywordtype}{net} \textcolor{keyword}{name}=\textcolor{stringliteral}{"vdd"} \textcolor{keyword}{type}=\textcolor{stringliteral}{"power"} \textcolor{keyword}{isExternal}=\textcolor{stringliteral}{"True"}> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{instance}=\textcolor{stringliteral}{"pmos1"} \textcolor{keyword}{name}=\textcolor{stringliteral}{"S"}/> - - <\textcolor{keywordtype}{net} \textcolor{keyword}{name}=\textcolor{stringliteral}{"vss"} \textcolor{keyword}{type}=\textcolor{stringliteral}{"ground"} \textcolor{keyword}{isExternal}=\textcolor{stringliteral}{"True"}> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{instance}=\textcolor{stringliteral}{"nmos1"} \textcolor{keyword}{name}=\textcolor{stringliteral}{"S"}/> - - <\textcolor{keywordtype}{net} \textcolor{keyword}{name}=\textcolor{stringliteral}{"in"} \textcolor{keyword}{type}=\textcolor{stringliteral}{"logical"} \textcolor{keyword}{isExternal}=\textcolor{stringliteral}{"True"}> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{instance}=\textcolor{stringliteral}{"nmos1"} \textcolor{keyword}{name}=\textcolor{stringliteral}{"G"}/> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{instance}=\textcolor{stringliteral}{"pmos1"} \textcolor{keyword}{name}=\textcolor{stringliteral}{"G"}/> - - <\textcolor{keywordtype}{net} \textcolor{keyword}{name}=\textcolor{stringliteral}{"out"} \textcolor{keyword}{type}=\textcolor{stringliteral}{"logical"} \textcolor{keyword}{isExternal}=\textcolor{stringliteral}{"True"}> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{instance}=\textcolor{stringliteral}{"nmos1"} \textcolor{keyword}{name}=\textcolor{stringliteral}{"D"}/> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{instance}=\textcolor{stringliteral}{"pmos1"} \textcolor{keyword}{name}=\textcolor{stringliteral}{"D"}/> - - - - <\textcolor{keywordtype}{schematic}> - <\textcolor{keywordtype}{instance} \textcolor{keyword}{name}=\textcolor{stringliteral}{"nmos1"} \textcolor{keyword}{x}=\textcolor{stringliteral}{"2490"} \textcolor{keyword}{y}=\textcolor{stringliteral}{"2600"} \textcolor{keyword}{orient}=\textcolor{stringliteral}{"ID"}/> - <\textcolor{keywordtype}{instance} \textcolor{keyword}{name}=\textcolor{stringliteral}{"pmos1"} \textcolor{keyword}{x}=\textcolor{stringliteral}{"2490"} \textcolor{keyword}{y}=\textcolor{stringliteral}{"2490"} \textcolor{keyword}{orient}=\textcolor{stringliteral}{"ID"}/> - <\textcolor{keywordtype}{net} \textcolor{keyword}{name}=\textcolor{stringliteral}{"vdd"}> - <\textcolor{keywordtype}{port} \textcolor{keyword}{type}=\textcolor{stringliteral}{"inV"} \textcolor{keyword}{idx}=\textcolor{stringliteral}{"0"} \textcolor{keyword}{x}=\textcolor{stringliteral}{"2525"} \textcolor{keyword}{y}=\textcolor{stringliteral}{"2430"} \textcolor{keyword}{orient}=\textcolor{stringliteral}{"ID"}/> - <\textcolor{keywordtype}{wire}> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"pmos1"} \textcolor{keyword}{plug}=\textcolor{stringliteral}{"S"}/> - \textcolor{comment}{} - <\textcolor{keywordtype}{connector} \textcolor{keyword}{idx}=\textcolor{stringliteral}{"0"}/> - - - <\textcolor{keywordtype}{net} \textcolor{keyword}{name}=\textcolor{stringliteral}{"vss"}> - <\textcolor{keywordtype}{port} \textcolor{keyword}{type}=\textcolor{stringliteral}{"inV"} \textcolor{keyword}{idx}=\textcolor{stringliteral}{"0"} \textcolor{keyword}{x}=\textcolor{stringliteral}{"2525"} \textcolor{keyword}{y}=\textcolor{stringliteral}{"2740"} \textcolor{keyword}{orient}=\textcolor{stringliteral}{"MY"}/> - <\textcolor{keywordtype}{wire}> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"nmos1"} \textcolor{keyword}{plug}=\textcolor{stringliteral}{"S"}/> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{idx}=\textcolor{stringliteral}{"0"}/> - - - <\textcolor{keywordtype}{net} \textcolor{keyword}{name}=\textcolor{stringliteral}{"in"}> - <\textcolor{keywordtype}{port} \textcolor{keyword}{type}=\textcolor{stringliteral}{"inH"} \textcolor{keyword}{idx}=\textcolor{stringliteral}{"0"} \textcolor{keyword}{x}=\textcolor{stringliteral}{"2415"} \textcolor{keyword}{y}=\textcolor{stringliteral}{"2520"} \textcolor{keyword}{orient}=\textcolor{stringliteral}{"ID"}/> - <\textcolor{keywordtype}{wire}> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"pmos1"} \textcolor{keyword}{plug}=\textcolor{stringliteral}{"G"}/> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"nmos1"} \textcolor{keyword}{plug}=\textcolor{stringliteral}{"G"}/> - - <\textcolor{keywordtype}{wire}> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{idx}=\textcolor{stringliteral}{"0"}/> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"pmos1"} \textcolor{keyword}{plug}=\textcolor{stringliteral}{"G"}/> - - - <\textcolor{keywordtype}{net} \textcolor{keyword}{name}=\textcolor{stringliteral}{"out"}> - <\textcolor{keywordtype}{port} \textcolor{keyword}{type}=\textcolor{stringliteral}{"outH"} \textcolor{keyword}{idx}=\textcolor{stringliteral}{"0"} \textcolor{keyword}{x}=\textcolor{stringliteral}{"2570"} \textcolor{keyword}{y}=\textcolor{stringliteral}{"2590"} \textcolor{keyword}{orient}=\textcolor{stringliteral}{"ID"}/> - <\textcolor{keywordtype}{wire}> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"pmos1"} \textcolor{keyword}{plug}=\textcolor{stringliteral}{"D"}/> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"nmos1"} \textcolor{keyword}{plug}=\textcolor{stringliteral}{"D"}/> - - <\textcolor{keywordtype}{wire}> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"nmos1"} \textcolor{keyword}{plug}=\textcolor{stringliteral}{"D"}/> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{idx}=\textcolor{stringliteral}{"0"}/> - - - - <\textcolor{keywordtype}{sizing}> - <\textcolor{keywordtype}{instance} \textcolor{keyword}{name}=\textcolor{stringliteral}{"pmos1"} \textcolor{keyword}{operator}=\textcolor{stringliteral}{"OPVG(Veg)"} \textcolor{keyword}{simulModel}=\textcolor{stringliteral}{"BSIM3V3"}> - <\textcolor{keywordtype}{constraint} \textcolor{keyword}{param}=\textcolor{stringliteral}{"Temp"} \textcolor{keyword}{ref}=\textcolor{stringliteral}{"design"} \textcolor{keyword}{refParam}=\textcolor{stringliteral}{"temp"}/> - <\textcolor{keywordtype}{constraint} \textcolor{keyword}{param}=\textcolor{stringliteral}{"Ids"} \textcolor{keyword}{ref}=\textcolor{stringliteral}{"design"} \textcolor{keyword}{refParam}=\textcolor{stringliteral}{"Ids"}/> - <\textcolor{keywordtype}{constraint} \textcolor{keyword}{param}=\textcolor{stringliteral}{"L"} \textcolor{keyword}{ref}=\textcolor{stringliteral}{"design"} \textcolor{keyword}{refParam}=\textcolor{stringliteral}{"L"}/> - <\textcolor{keywordtype}{constraint} \textcolor{keyword}{param}=\textcolor{stringliteral}{"Veg"} \textcolor{keyword}{ref}=\textcolor{stringliteral}{"design"} \textcolor{keyword}{refParam}=\textcolor{stringliteral}{"Veg"}/> - <\textcolor{keywordtype}{constraint} \textcolor{keyword}{param}=\textcolor{stringliteral}{"Vd"} \textcolor{keyword}{ref}=\textcolor{stringliteral}{"design"} \textcolor{keyword}{refParam}=\textcolor{stringliteral}{"Vdd"} \textcolor{keyword}{factor}=\textcolor{stringliteral}{"0.5"}/> - <\textcolor{keywordtype}{constraint} \textcolor{keyword}{param}=\textcolor{stringliteral}{"Vs"} \textcolor{keyword}{ref}=\textcolor{stringliteral}{"design"} \textcolor{keyword}{refParam}=\textcolor{stringliteral}{"Vdd"}/> - - <\textcolor{keywordtype}{instance} \textcolor{keyword}{name}=\textcolor{stringliteral}{"nmos1"} \textcolor{keyword}{operator}=\textcolor{stringliteral}{"OPW(Vg,Vs)"} \textcolor{keyword}{simulModel}=\textcolor{stringliteral}{"BSIM3V3"}> - <\textcolor{keywordtype}{constraint} \textcolor{keyword}{param}=\textcolor{stringliteral}{"Temp"} \textcolor{keyword}{ref}=\textcolor{stringliteral}{"design"} \textcolor{keyword}{refParam}=\textcolor{stringliteral}{"temp"}/> - <\textcolor{keywordtype}{constraint} \textcolor{keyword}{param}=\textcolor{stringliteral}{"Ids"} \textcolor{keyword}{ref}=\textcolor{stringliteral}{"design"} \textcolor{keyword}{refParam}=\textcolor{stringliteral}{"Ids"}/> - <\textcolor{keywordtype}{constraint} \textcolor{keyword}{param}=\textcolor{stringliteral}{"L"} \textcolor{keyword}{ref}=\textcolor{stringliteral}{"design"} \textcolor{keyword}{refParam}=\textcolor{stringliteral}{"L"}/> - <\textcolor{keywordtype}{constraint} \textcolor{keyword}{param}=\textcolor{stringliteral}{"Vs"} \textcolor{keyword}{ref}=\textcolor{stringliteral}{"design"} \textcolor{keyword}{refParam}=\textcolor{stringliteral}{"Vdd"}/> - <\textcolor{keywordtype}{constraint} \textcolor{keyword}{param}=\textcolor{stringliteral}{"Vg"} \textcolor{keyword}{ref}=\textcolor{stringliteral}{"pmos1"} \textcolor{keyword}{refParam}=\textcolor{stringliteral}{"Vg"}/> - <\textcolor{keywordtype}{constraint} \textcolor{keyword}{param}=\textcolor{stringliteral}{"Vd"} \textcolor{keyword}{ref}=\textcolor{stringliteral}{"pmos1"} \textcolor{keyword}{refParam}=\textcolor{stringliteral}{"Vd"}/> - <\textcolor{keywordtype}{constraint} \textcolor{keyword}{param}=\textcolor{stringliteral}{"another"} \textcolor{keyword}{refEquation}=\textcolor{stringliteral}{"myEq"} \textcolor{keyword}{factor}=\textcolor{stringliteral}{"-2.5"}/> - - <\textcolor{keywordtype}{equations}> - <\textcolor{keywordtype}{eq} \textcolor{keyword}{name}=\textcolor{stringliteral}{"myEq"} \textcolor{keyword}{equation}=\textcolor{stringliteral}{"A/more+complex*equation"}/> - - - <\textcolor{keywordtype}{layout}> - <\textcolor{keywordtype}{instance} \textcolor{keyword}{name}=\textcolor{stringliteral}{"pmos1"} \textcolor{keyword}{style}=\textcolor{stringliteral}{"Common transistor"}/> - <\textcolor{keywordtype}{instance} \textcolor{keyword}{name}=\textcolor{stringliteral}{"nmos1"} \textcolor{keyword}{style}=\textcolor{stringliteral}{"Rotate transistor"}/> - <\textcolor{keywordtype}{hbtree}> - <\textcolor{keywordtype}{group} \textcolor{keyword}{name}=\textcolor{stringliteral}{"g1"} \textcolor{keyword}{align}=\textcolor{stringliteral}{"vertical"}> - <\textcolor{keywordtype}{bloc} \textcolor{keyword}{name}=\textcolor{stringliteral}{"nmos1"}> - <\textcolor{keywordtype}{bloc} \textcolor{keyword}{name}=\textcolor{stringliteral}{"pmos1"} \textcolor{keyword}{position}=\textcolor{stringliteral}{"top"}/> - - - - - \end{DoxyCodeInclude} \begin{DoxyCodeInclude} - -<\textcolor{keywordtype}{circuit} \textcolor{keyword}{name}=\textcolor{stringliteral}{"buffer"} \textcolor{keyword}{techno}=\textcolor{stringliteral}{"myTech"}> - <\textcolor{keywordtype}{subCircuitsPaths}> - <\textcolor{keywordtype}{path} \textcolor{keyword}{path}=\textcolor{stringliteral}{"."}/> - - <\textcolor{keywordtype}{netlist}> - <\textcolor{keywordtype}{instances}> - <\textcolor{keywordtype}{instance} \textcolor{keyword}{name}=\textcolor{stringliteral}{"inv1"} \textcolor{keyword}{model}=\textcolor{stringliteral}{"inverter"}> - <\textcolor{keywordtype}{connectors}> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"vdd"}/> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"vss"}/> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"in"} /> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"out"}/> - - - <\textcolor{keywordtype}{instance} \textcolor{keyword}{name}=\textcolor{stringliteral}{"inv2"} \textcolor{keyword}{model}=\textcolor{stringliteral}{"inverter"}> - <\textcolor{keywordtype}{connectors}> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"vdd"}/> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"vss"}/> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"in"} /> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"out"}/> - - - - <\textcolor{keywordtype}{nets}> - <\textcolor{keywordtype}{net} \textcolor{keyword}{name}=\textcolor{stringliteral}{"vdd"} \textcolor{keyword}{type}=\textcolor{stringliteral}{"power"} \textcolor{keyword}{isExternal}=\textcolor{stringliteral}{"True"}> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{instance}=\textcolor{stringliteral}{"inv1"} \textcolor{keyword}{name}=\textcolor{stringliteral}{"vdd"}/> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{instance}=\textcolor{stringliteral}{"inv2"} \textcolor{keyword}{name}=\textcolor{stringliteral}{"vdd"}/> - - <\textcolor{keywordtype}{net} \textcolor{keyword}{name}=\textcolor{stringliteral}{"vss"} \textcolor{keyword}{type}=\textcolor{stringliteral}{"ground"} \textcolor{keyword}{isExternal}=\textcolor{stringliteral}{"True"}> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{instance}=\textcolor{stringliteral}{"inv1"} \textcolor{keyword}{name}=\textcolor{stringliteral}{"vss"}/> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{instance}=\textcolor{stringliteral}{"inv2"} \textcolor{keyword}{name}=\textcolor{stringliteral}{"vss"}/> - - <\textcolor{keywordtype}{net} \textcolor{keyword}{name}=\textcolor{stringliteral}{"in"} \textcolor{keyword}{type}=\textcolor{stringliteral}{"logical"} \textcolor{keyword}{isExternal}=\textcolor{stringliteral}{"True"}> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{instance}=\textcolor{stringliteral}{"inv1"} \textcolor{keyword}{name}=\textcolor{stringliteral}{"in"}/> - - <\textcolor{keywordtype}{net} \textcolor{keyword}{name}=\textcolor{stringliteral}{"out"} \textcolor{keyword}{type}=\textcolor{stringliteral}{"logical"} \textcolor{keyword}{isExternal}=\textcolor{stringliteral}{"True"}> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{instance}=\textcolor{stringliteral}{"inv2"} \textcolor{keyword}{name}=\textcolor{stringliteral}{"out"}/> - - <\textcolor{keywordtype}{net} \textcolor{keyword}{name}=\textcolor{stringliteral}{"internal"} \textcolor{keyword}{type}=\textcolor{stringliteral}{"logical"} \textcolor{keyword}{isExternal}=\textcolor{stringliteral}{"False"}> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{instance}=\textcolor{stringliteral}{"inv1"} \textcolor{keyword}{name}=\textcolor{stringliteral}{"out"}/> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{instance}=\textcolor{stringliteral}{"inv2"} \textcolor{keyword}{name}=\textcolor{stringliteral}{"in"}/> - - - - <\textcolor{keywordtype}{schematic}> - <\textcolor{keywordtype}{instance} \textcolor{keyword}{name}=\textcolor{stringliteral}{"inv1"} \textcolor{keyword}{x}=\textcolor{stringliteral}{"2490"} \textcolor{keyword}{y}=\textcolor{stringliteral}{"2600"} \textcolor{keyword}{orient}=\textcolor{stringliteral}{"ID"}/> - <\textcolor{keywordtype}{instance} \textcolor{keyword}{name}=\textcolor{stringliteral}{"inv2"} \textcolor{keyword}{x}=\textcolor{stringliteral}{"2490"} \textcolor{keyword}{y}=\textcolor{stringliteral}{"2300"} \textcolor{keyword}{orient}=\textcolor{stringliteral}{"ID"}/> - <\textcolor{keywordtype}{net} \textcolor{keyword}{name}=\textcolor{stringliteral}{"in"}> - <\textcolor{keywordtype}{port} \textcolor{keyword}{type}=\textcolor{stringliteral}{"inV"} \textcolor{keyword}{idx}=\textcolor{stringliteral}{"0"} \textcolor{keyword}{x}=\textcolor{stringliteral}{"2415"} \textcolor{keyword}{y}=\textcolor{stringliteral}{"2700"} \textcolor{keyword}{orient}=\textcolor{stringliteral}{"MY"}/> - <\textcolor{keywordtype}{wire}> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"inv1"} \textcolor{keyword}{plug}=\textcolor{stringliteral}{"in"}/> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{idx}=\textcolor{stringliteral}{"0"}/> - - - <\textcolor{keywordtype}{net} \textcolor{keyword}{name}=\textcolor{stringliteral}{"internal"}> - <\textcolor{keywordtype}{wire}> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"inv1"} \textcolor{keyword}{plug}=\textcolor{stringliteral}{"out"}/> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"inv2"} \textcolor{keyword}{plug}=\textcolor{stringliteral}{"in"}/> - - - <\textcolor{keywordtype}{net} \textcolor{keyword}{name}=\textcolor{stringliteral}{"out"}> - <\textcolor{keywordtype}{port} \textcolor{keyword}{type}=\textcolor{stringliteral}{"outV"} \textcolor{keyword}{idx}=\textcolor{stringliteral}{"0"} \textcolor{keyword}{x}=\textcolor{stringliteral}{"2415"} \textcolor{keyword}{y}=\textcolor{stringliteral}{"2200"} \textcolor{keyword}{orient}=\textcolor{stringliteral}{"MY"}/> - <\textcolor{keywordtype}{wire}> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"inv2"} \textcolor{keyword}{plug}=\textcolor{stringliteral}{"out"}/> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{idx}=\textcolor{stringliteral}{"0"}/> - - - <\textcolor{keywordtype}{net} \textcolor{keyword}{name}=\textcolor{stringliteral}{"vdd"}> - <\textcolor{keywordtype}{port} \textcolor{keyword}{type}=\textcolor{stringliteral}{"inH"} \textcolor{keyword}{idx}=\textcolor{stringliteral}{"0"} \textcolor{keyword}{x}=\textcolor{stringliteral}{"2200"} \textcolor{keyword}{y}=\textcolor{stringliteral}{"2500"} \textcolor{keyword}{orient}=\textcolor{stringliteral}{"ID"}/> - <\textcolor{keywordtype}{wire}> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{idx}=\textcolor{stringliteral}{"0"}/> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"inv2"} \textcolor{keyword}{plug}=\textcolor{stringliteral}{"vdd"}/> - - <\textcolor{keywordtype}{wire}> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"inv1"} \textcolor{keyword}{plug}=\textcolor{stringliteral}{"vdd"}/> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"inv2"} \textcolor{keyword}{plug}=\textcolor{stringliteral}{"vdd"}/> - - - <\textcolor{keywordtype}{net} \textcolor{keyword}{name}=\textcolor{stringliteral}{"vss"}> - <\textcolor{keywordtype}{port} \textcolor{keyword}{type}=\textcolor{stringliteral}{"inH"} \textcolor{keyword}{idx}=\textcolor{stringliteral}{"0"} \textcolor{keyword}{x}=\textcolor{stringliteral}{"2700"} \textcolor{keyword}{y}=\textcolor{stringliteral}{"2500"} \textcolor{keyword}{orient}=\textcolor{stringliteral}{"MX"}/> - <\textcolor{keywordtype}{wire}> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{idx}=\textcolor{stringliteral}{"0"}/> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"inv2"} \textcolor{keyword}{plug}=\textcolor{stringliteral}{"vss"}/> - - <\textcolor{keywordtype}{wire}> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"inv1"} \textcolor{keyword}{plug}=\textcolor{stringliteral}{"vss"}/> - <\textcolor{keywordtype}{connector} \textcolor{keyword}{name}=\textcolor{stringliteral}{"inv2"} \textcolor{keyword}{plug}=\textcolor{stringliteral}{"vss"}/> - - - - \end{DoxyCodeInclude} @@ -279,420 +57,10 @@ All source codes are available in the {\ttfamily examples} directory.\hypertarge \hypertarget{openchams_openChamsParseC}{}\subsubsection{Parser}\label{openchams_openChamsParseC} The following code ({\ttfamily parse\+Open\+Chams.\+cpp}) is an example of how to parse a O\+P\+E\+N\+C\+H\+A\+MS file using C++ library. \begin{DoxyCodeInclude} -\textcolor{preprocessor}{#include } -\textcolor{preprocessor}{#include } -\textcolor{preprocessor}{#include } -\textcolor{preprocessor}{#include } -\textcolor{keyword}{using namespace }\mbox{\hyperlink{namespacestd}{std}}; - -\textcolor{preprocessor}{#include "vlsisapd/openChams/Circuit.h"} -\textcolor{preprocessor}{#include "vlsisapd/openChams/Name.h"} -\textcolor{preprocessor}{#include "vlsisapd/openChams/Parameters.h"} -\textcolor{preprocessor}{#include "vlsisapd/openChams/Netlist.h"} -\textcolor{preprocessor}{#include "vlsisapd/openChams/Instance.h"} -\textcolor{preprocessor}{#include "vlsisapd/openChams/Device.h"} -\textcolor{preprocessor}{#include "vlsisapd/openChams/Net.h"} -\textcolor{preprocessor}{#include "vlsisapd/openChams/Transistor.h"} -\textcolor{preprocessor}{#include "vlsisapd/openChams/Schematic.h"} -\textcolor{preprocessor}{#include "vlsisapd/openChams/Sizing.h"} -\textcolor{preprocessor}{#include "vlsisapd/openChams/Operator.h"} -\textcolor{preprocessor}{#include "vlsisapd/openChams/Layout.h"} -\textcolor{preprocessor}{#include "vlsisapd/openChams/Node.h"} -\textcolor{preprocessor}{#include "vlsisapd/openChams/Port.h"} -\textcolor{preprocessor}{#include "vlsisapd/openChams/Wire.h"} -\textcolor{preprocessor}{#include "vlsisapd/openChams/OpenChamsException.h"} - -\textcolor{keywordtype}{void} printHBTree(\mbox{\hyperlink{class_open_chams_1_1_node}{OpenChams::Node}}* node, \textcolor{keywordtype}{unsigned} indent) \{ - \textcolor{keywordflow}{if} (!node) \textcolor{keywordflow}{return}; \textcolor{comment}{// since we pass nnode->getRight and node-getTop without checking for NULL} - \textcolor{keywordflow}{for} (\textcolor{keywordtype}{unsigned} i = 0 ; i < indent ; i++) \{ - cerr << \textcolor{stringliteral}{" |"}; - \} - \textcolor{keywordtype}{string} pos = \textcolor{stringliteral}{""}; - \textcolor{keywordflow}{switch}(node->\mbox{\hyperlink{class_open_chams_1_1_node_a566f4d0bebb46cfd31384a8394a7dbb9}{getPosition}}()) \{ - \textcolor{keywordflow}{case} OpenChams::Node::TOP: - pos = \textcolor{stringliteral}{"top"}; - \textcolor{keywordflow}{break}; - \textcolor{keywordflow}{case} OpenChams::Node::RIGHT: - pos = \textcolor{stringliteral}{"right"}; - \textcolor{keywordflow}{break}; - \textcolor{keywordflow}{default}: - \textcolor{keywordflow}{break}; - \} - \mbox{\hyperlink{class_open_chams_1_1_bloc}{OpenChams::Bloc}}* bloc = \textcolor{keyword}{dynamic\_cast<}\mbox{\hyperlink{class_open_chams_1_1_bloc}{OpenChams::Bloc}}*\textcolor{keyword}{>}(node); - \textcolor{keywordflow}{if} (bloc) \{ - cerr << \textcolor{stringliteral}{" bloc: "} << bloc->\mbox{\hyperlink{class_open_chams_1_1_node_a3fd7335faa33dce2f87c7e50eef3e294}{getName}}().getString() << \textcolor{stringliteral}{" - "} << pos << endl; - printHBTree(bloc->\mbox{\hyperlink{class_open_chams_1_1_node_af59967a8c2d5a04ca0a58e2ef29bead1}{getTop}}() , indent+1); - printHBTree(bloc->\mbox{\hyperlink{class_open_chams_1_1_node_a9533ddcf078ddfc2a4e9bd9ffafa51cb}{getRight}}(), indent+1); - \textcolor{keywordflow}{return}; - \} - \mbox{\hyperlink{class_open_chams_1_1_group}{OpenChams::Group}}* group = \textcolor{keyword}{dynamic\_cast<}\mbox{\hyperlink{class_open_chams_1_1_group}{OpenChams::Group}}*\textcolor{keyword}{>}(node); - \textcolor{keywordflow}{if} (group) \{ - \textcolor{keywordtype}{string} align = \textcolor{stringliteral}{"none"}; - \textcolor{keywordflow}{switch}(group->\mbox{\hyperlink{class_open_chams_1_1_group_a7cff0c4a6957f23fb1ea4598f4b8a0b8}{getAlign}}()) \{ - \textcolor{keywordflow}{case} OpenChams::Group::VERTICAL: - align = \textcolor{stringliteral}{"vertical"}; - \textcolor{keywordflow}{break}; - \textcolor{keywordflow}{case} OpenChams::Group::HORIZONTAL: - align = \textcolor{stringliteral}{"horizontal"}; - \textcolor{keywordflow}{break}; - \textcolor{keywordflow}{default}: - \textcolor{keywordflow}{break}; - \} - cerr << \textcolor{stringliteral}{" group: "} << group->\mbox{\hyperlink{class_open_chams_1_1_node_a3fd7335faa33dce2f87c7e50eef3e294}{getName}}().getString() << \textcolor{stringliteral}{" - "} << pos << \textcolor{stringliteral}{" - align: "} << align - << \textcolor{stringliteral}{" - isolated: "} << group->\mbox{\hyperlink{class_open_chams_1_1_group_ab5ae4a4550c418c974ff6e59967eeec2}{isIsolated}}() << \textcolor{stringliteral}{" - paired: "} << group-> - \mbox{\hyperlink{class_open_chams_1_1_group_aee0abf07a6e9d41f511c648e6eaecea3}{isPaired}}() << endl; - printHBTree(group->getRootNode(), indent+1); - printHBTree(group->\mbox{\hyperlink{class_open_chams_1_1_node_af59967a8c2d5a04ca0a58e2ef29bead1}{getTop}}() , indent+1); - printHBTree(group->\mbox{\hyperlink{class_open_chams_1_1_node_a9533ddcf078ddfc2a4e9bd9ffafa51cb}{getRight}}() , indent+1); - \textcolor{keywordflow}{return}; - \} - cerr << \textcolor{stringliteral}{"[ERROR] printHBTree: node is nor a bloc nor a group !"} << endl; - \textcolor{keywordflow}{return}; -\} - -\textcolor{keywordtype}{int} main(\textcolor{keywordtype}{int} argc, \textcolor{keywordtype}{char} * argv[]) \{ - \textcolor{keywordtype}{string} file = \textcolor{stringliteral}{""}; - \textcolor{keywordflow}{if} (argc == 1) - file = \textcolor{stringliteral}{"./inverter.xml"}; - \textcolor{keywordflow}{else} \textcolor{keywordflow}{if} (argc == 2) - file = argv[1]; - \textcolor{keywordflow}{else} \{ - cerr << \textcolor{stringliteral}{"Usage: openChamsParser [filename]"} << endl; - exit(1); - \} - - \mbox{\hyperlink{class_open_chams_1_1_circuit}{OpenChams::Circuit}}* circuit = NULL; - \textcolor{keywordflow}{try} \{ - circuit = \mbox{\hyperlink{class_open_chams_1_1_circuit_ad0aa3183bdea59e62f69c295026b7fe7}{OpenChams::Circuit::readFromFile}}(file); - \} \textcolor{keywordflow}{catch} (\mbox{\hyperlink{class_open_chams_1_1_open_chams_exception}{OpenChams::OpenChamsException}}& e) \{ - cerr << e.what() << endl; - exit(48); - \} - - cerr << circuit->\mbox{\hyperlink{class_open_chams_1_1_circuit_a2858c0c4e8b5108f041237cf5a802029}{getName}}().getString() << endl; - cerr << \textcolor{stringliteral}{" + parameters"} << endl; - \mbox{\hyperlink{class_open_chams_1_1_parameters}{OpenChams::Parameters}} params = circuit->\mbox{\hyperlink{class_open_chams_1_1_circuit_a2e51ad4344607fc279c5c8cda4edae02}{getParameters}}(); - \textcolor{keywordflow}{if} (!params.\mbox{\hyperlink{class_open_chams_1_1_parameters_af337ffd75e4f019ce15302c60715d84b}{isEmpty}}()) \{ - \textcolor{keywordflow}{for} (map::const\_iterator it = params.\mbox{\hyperlink{class_open_chams_1_1_parameters_a0f890d16c3b2a0bcbdf060854ea07877}{getValues}}().begin() ; it != - params.\mbox{\hyperlink{class_open_chams_1_1_parameters_a0f890d16c3b2a0bcbdf060854ea07877}{getValues}}().end() ; ++it) \{ - cerr << \textcolor{stringliteral}{" | | "} << ((*it).first).getString() << \textcolor{stringliteral}{" : "} << (*it).second << endl; - \} - \} - cerr << \textcolor{stringliteral}{" + netlist"} << endl; - cerr << \textcolor{stringliteral}{" | + instances"} << endl; - \mbox{\hyperlink{class_open_chams_1_1_netlist}{OpenChams::Netlist}}* netlist = circuit->\mbox{\hyperlink{class_open_chams_1_1_circuit_a4085d6a7b6958ffdd7ab5df7e6d6e53f}{getNetlist}}(); - \textcolor{keywordflow}{if} (netlist && !netlist->\mbox{\hyperlink{class_open_chams_1_1_netlist_adab62a25face462baec9a7fffb2b6158}{hasNoInstances}}()) \{ - \textcolor{keywordflow}{for} (\textcolor{keywordtype}{size\_t} i = 0 ; i < netlist->\mbox{\hyperlink{class_open_chams_1_1_netlist_a8e6e58ffab876152a740092520c35d73}{getInstances}}().size() ; i++) \{ - \mbox{\hyperlink{class_open_chams_1_1_instance}{OpenChams::Instance}}* inst = netlist->\mbox{\hyperlink{class_open_chams_1_1_netlist_a8e6e58ffab876152a740092520c35d73}{getInstances}}()[i]; - \mbox{\hyperlink{class_open_chams_1_1_device}{OpenChams::Device}}* dev = NULL; - \textcolor{keywordflow}{if} (dynamic\_cast(inst)) \{ - dev = \textcolor{keyword}{static\_cast<}\mbox{\hyperlink{class_open_chams_1_1_device}{OpenChams::Device}}*\textcolor{keyword}{>}(inst); - cerr << \textcolor{stringliteral}{" | | + "} << dev->getName().getString() << \textcolor{stringliteral}{" : "} << dev->getModel().getString() << \textcolor{stringliteral}{ - " - "} << dev->getOrder() << \textcolor{stringliteral}{" - "} << dev->\mbox{\hyperlink{class_open_chams_1_1_device_a831ce553c23908f447a5be332ecd5946}{getMosType}}().getString() << \textcolor{stringliteral}{" - "} << (dev-> - \mbox{\hyperlink{class_open_chams_1_1_device_a29ed1982e1a8b3a634df8d0c70039669}{isSourceBulkConnected}}()?\textcolor{stringliteral}{"true"}:\textcolor{stringliteral}{"false"}) << endl; - \} \textcolor{keywordflow}{else} \{ - cerr << \textcolor{stringliteral}{" | | + "} << inst->getName().getString() << \textcolor{stringliteral}{" : "} << inst->getModel().getString() < - < \textcolor{stringliteral}{" - "} << inst->getOrder() << endl; - \} - cerr << \textcolor{stringliteral}{" | | | + connectors"} << endl; - \textcolor{keywordflow}{for} (map::const\_iterator cit = inst-> - \mbox{\hyperlink{class_open_chams_1_1_instance_a745fe0a50eb770ce3bea36ef0e62c8ca}{getConnectors}}().begin() ; cit != inst->\mbox{\hyperlink{class_open_chams_1_1_instance_a745fe0a50eb770ce3bea36ef0e62c8ca}{getConnectors}}().end() ; ++cit) \{ - \textcolor{keywordflow}{if} ((*cit).second) - cerr << \textcolor{stringliteral}{" | | | | "} << ((*cit).first).getString() << \textcolor{stringliteral}{" : "} << ((*cit).second)->getName( - ).getString() << endl; - \textcolor{keywordflow}{else} - cerr << \textcolor{stringliteral}{" | | | | "} << ((*cit).first).getString() << endl; \textcolor{comment}{// no net connected !} - \} - \textcolor{keywordflow}{if} (dev) \{ - cerr << \textcolor{stringliteral}{" | | | + transistors"} << endl; - \textcolor{keywordflow}{for} (\textcolor{keywordtype}{size\_t} j = 0 ; j < dev->\mbox{\hyperlink{class_open_chams_1_1_device_a4033525cab6387eb057f71f5feed9802}{getTransistors}}().size() ; j++) \{ - \mbox{\hyperlink{class_open_chams_1_1_transistor}{OpenChams::Transistor}}* tr = dev-> - \mbox{\hyperlink{class_open_chams_1_1_device_a4033525cab6387eb057f71f5feed9802}{getTransistors}}()[j]; - cerr << \textcolor{stringliteral}{" | | | | name: "} << tr->\mbox{\hyperlink{class_open_chams_1_1_transistor_a2858c0c4e8b5108f041237cf5a802029}{getName}}().getString() << \textcolor{stringliteral}{" - gate: "} << tr-> - \mbox{\hyperlink{class_open_chams_1_1_transistor_a99f1449aa735ff6cb4927b4f6aa34d9d}{getGate}}().getString() << \textcolor{stringliteral}{" - source: "} << tr->\mbox{\hyperlink{class_open_chams_1_1_transistor_aee4d52a0b13e6db247c1a6c051aede25}{getSource}}().getString() << \textcolor{stringliteral}{" - drain: "} << tr - ->\mbox{\hyperlink{class_open_chams_1_1_transistor_a62ea0998b3a61310a8331873f5bcce58}{getDrain}}().getString() << \textcolor{stringliteral}{" - bulk: "} << tr->\mbox{\hyperlink{class_open_chams_1_1_transistor_a27ba43f825f9243556ec65d306a2b1a7}{getBulk}}().getString() << endl; - \} - \} - \} - \} - cerr << \textcolor{stringliteral}{" | + nets"} << endl; - \textcolor{keywordtype}{bool} schematicNet = \textcolor{keyword}{false}; \textcolor{comment}{// define wether net sections are needed in schematic section} - \textcolor{keywordflow}{if} (!netlist->\mbox{\hyperlink{class_open_chams_1_1_netlist_a36089e1b3a3f2d3f7c9dcc8e3c3bd6d8}{hasNoNets}}()) \{ - \textcolor{keywordflow}{for} (\textcolor{keywordtype}{size\_t} i = 0 ; i < netlist->\mbox{\hyperlink{class_open_chams_1_1_netlist_abf36db82efb99a8ec8ae4b454be00019}{getNets}}().size() ; i++) \{ - \mbox{\hyperlink{class_open_chams_1_1_net}{OpenChams::Net}}* net = netlist->\mbox{\hyperlink{class_open_chams_1_1_netlist_abf36db82efb99a8ec8ae4b454be00019}{getNets}}()[i]; - cerr << \textcolor{stringliteral}{" | | + "} << net->\mbox{\hyperlink{class_open_chams_1_1_net_a3fd7335faa33dce2f87c7e50eef3e294}{getName}}().getString() << \textcolor{stringliteral}{" : "} << net-> - \mbox{\hyperlink{class_open_chams_1_1_net_a7a88ff26f0ba9cfbfa5059c565d1e30b}{getType}}().getString() << \textcolor{stringliteral}{" - "} << (net->\mbox{\hyperlink{class_open_chams_1_1_net_ab2570574db49633f58f7b64099d6852c}{isExternal}}()?\textcolor{stringliteral}{"true"}:\textcolor{stringliteral}{"false"}) << endl; - cerr << \textcolor{stringliteral}{" | | | + connections"} << endl; - \textcolor{keywordflow}{for} (\textcolor{keywordtype}{size\_t} j = 0 ; j < net->\mbox{\hyperlink{class_open_chams_1_1_net_a87e7c71b25171dd479af0488865c8179}{getConnections}}().size() ; j++) \{ - \mbox{\hyperlink{class_open_chams_1_1_net_1_1_connection}{OpenChams::Net::Connection}}* connect = net-> - \mbox{\hyperlink{class_open_chams_1_1_net_a87e7c71b25171dd479af0488865c8179}{getConnections}}()[j]; - cerr << \textcolor{stringliteral}{" | | | | "} << connect->\mbox{\hyperlink{class_open_chams_1_1_net_1_1_connection_a7d21af8ef567328876b39f135d6c94ca}{getInstanceName}}().getString() << \textcolor{stringliteral}{"."} << - connect->\mbox{\hyperlink{class_open_chams_1_1_net_1_1_connection_a33e7a2599cd477f8190c85d2aba9ce88}{getConnectorName}}().getString() << endl; - \} - \textcolor{keywordflow}{if} (!net->\mbox{\hyperlink{class_open_chams_1_1_net_a3eef7a6d1e945441f197f0918ab8895e}{hasNoPorts}}() || !net->\mbox{\hyperlink{class_open_chams_1_1_net_ac9470e72b26d4cddef3d13e69057ee54}{hasNoWires}}()) - schematicNet = \textcolor{keyword}{true}; - \} - \} - \mbox{\hyperlink{class_open_chams_1_1_schematic}{OpenChams::Schematic}}* schematic = circuit->\mbox{\hyperlink{class_open_chams_1_1_circuit_af6f967a5685ac92fe760f4eb95c8c51f}{getSchematic}}(); - \textcolor{keywordflow}{if} (schematic && !schematic->\mbox{\hyperlink{class_open_chams_1_1_schematic_adab62a25face462baec9a7fffb2b6158}{hasNoInstances}}()) \{ - cerr << \textcolor{stringliteral}{" + schematic"} << endl; - \textcolor{keywordflow}{for} (map::const\_iterator sit = schematic-> - \mbox{\hyperlink{class_open_chams_1_1_schematic_afa015b02922d82de9c44e8ffe8dc5d56}{getInstances}}().begin() ; sit != schematic->\mbox{\hyperlink{class_open_chams_1_1_schematic_afa015b02922d82de9c44e8ffe8dc5d56}{getInstances}}().end() ; ++sit) \{ - \mbox{\hyperlink{class_open_chams_1_1_schematic_1_1_infos}{OpenChams::Schematic::Infos}}* inf = (*sit).second; - cerr << \textcolor{stringliteral}{" | + instance: name: "} << ((*sit).first).getString() << \textcolor{stringliteral}{" - x: "} << inf-> - \mbox{\hyperlink{class_open_chams_1_1_schematic_1_1_infos_a2b69e4312b7814c6efce42f851893409}{getX}}() << \textcolor{stringliteral}{" - y: "} << inf->\mbox{\hyperlink{class_open_chams_1_1_schematic_1_1_infos_a15f19cf52955c8c3406831b288681358}{getY}}() << \textcolor{stringliteral}{" - orientation: "} << inf-> - \mbox{\hyperlink{class_open_chams_1_1_schematic_1_1_infos_ac7e0f89be2baffb526b2dca46da7aa47}{getOrientation}}().getString() << endl; - \} - \textcolor{keywordflow}{if} (schematicNet) \{ - \textcolor{keywordflow}{for} (\textcolor{keywordtype}{size\_t} i = 0 ; i < netlist->\mbox{\hyperlink{class_open_chams_1_1_netlist_abf36db82efb99a8ec8ae4b454be00019}{getNets}}().size() ; i++) \{ - \mbox{\hyperlink{class_open_chams_1_1_net}{OpenChams::Net}}* net = netlist->\mbox{\hyperlink{class_open_chams_1_1_netlist_abf36db82efb99a8ec8ae4b454be00019}{getNets}}()[i]; - cerr << \textcolor{stringliteral}{" | + net name: "} << net->\mbox{\hyperlink{class_open_chams_1_1_net_a3fd7335faa33dce2f87c7e50eef3e294}{getName}}().getString() << endl; - \textcolor{keywordflow}{if} (!net->\mbox{\hyperlink{class_open_chams_1_1_net_a3eef7a6d1e945441f197f0918ab8895e}{hasNoPorts}}()) \{ - \textcolor{keywordflow}{for} (\textcolor{keywordtype}{size\_t} j = 0 ; j < net->\mbox{\hyperlink{class_open_chams_1_1_net_ae9d241ec6dd833b6d7813e14ff2d9eca}{getPorts}}().size() ; j++) \{ - \mbox{\hyperlink{class_open_chams_1_1_port}{OpenChams::Port}}* port = net->\mbox{\hyperlink{class_open_chams_1_1_net_ae9d241ec6dd833b6d7813e14ff2d9eca}{getPorts}}()[j]; - cerr << \textcolor{stringliteral}{" | | + port type: "} << port->\mbox{\hyperlink{class_open_chams_1_1_port_a49fc4eb493558cf55dd00df9ef5f8f08}{getType}}().getString() << \textcolor{stringliteral}{" - idx: "} < - < port->\mbox{\hyperlink{class_open_chams_1_1_port_a743f20da85b9a06d9984c0adc337afc1}{getIndex}}() << \textcolor{stringliteral}{" - x: "} << port->\mbox{\hyperlink{class_open_chams_1_1_port_a344385751bee0720059403940d57a13e}{getX}}() << \textcolor{stringliteral}{" - y: "} << port-> - \mbox{\hyperlink{class_open_chams_1_1_port_aafa51c7f8f38a09febbb9ce7853f77b4}{getY}}() << \textcolor{stringliteral}{" - orientation: "} << port->\mbox{\hyperlink{class_open_chams_1_1_port_ace51e4bf9cee0319600c14723efa0dfb}{getOrientation}}().getString() << endl; - \} - \} - \textcolor{keywordflow}{if} (!net->\mbox{\hyperlink{class_open_chams_1_1_net_ac9470e72b26d4cddef3d13e69057ee54}{hasNoWires}}()) \{ - \textcolor{keywordflow}{for} (\textcolor{keywordtype}{size\_t} j = 0 ; j < net->\mbox{\hyperlink{class_open_chams_1_1_net_a2f8bcf7cad7711850efeca408f146b8a}{getWires}}().size() ; j++) \{ - \mbox{\hyperlink{class_open_chams_1_1_wire}{OpenChams::Wire}}* wire = net->\mbox{\hyperlink{class_open_chams_1_1_net_a2f8bcf7cad7711850efeca408f146b8a}{getWires}}()[j]; - cerr << \textcolor{stringliteral}{" | | + wire "}; - \mbox{\hyperlink{class_open_chams_1_1_wire_point}{OpenChams::WirePoint}}* start = wire-> - \mbox{\hyperlink{class_open_chams_1_1_wire_ad68ddfcb6d4cbbe3c06d03fb4350dcdb}{getStartPoint}}(); - \textcolor{keywordflow}{if} (dynamic\_cast(start)) \{ - \mbox{\hyperlink{class_open_chams_1_1_instance_point}{OpenChams::InstancePoint}}* iP = \textcolor{keyword}{static\_cast<} - \mbox{\hyperlink{class_open_chams_1_1_instance_point}{OpenChams::InstancePoint}}*\textcolor{keyword}{>}(start); - cerr << \textcolor{stringliteral}{"<"} << iP->\mbox{\hyperlink{class_open_chams_1_1_instance_point_a2858c0c4e8b5108f041237cf5a802029}{getName}}().getString() << \textcolor{stringliteral}{","} << iP-> - \mbox{\hyperlink{class_open_chams_1_1_instance_point_a646d464666fc56ab2e04a6b87fdd3279}{getPlug}}().getString() << \textcolor{stringliteral}{"> "}; - \} \textcolor{keywordflow}{else} \textcolor{keywordflow}{if} (dynamic\_cast(start)) \{ - \mbox{\hyperlink{class_open_chams_1_1_port_point}{OpenChams::PortPoint}}* pP = \textcolor{keyword}{static\_cast<} - \mbox{\hyperlink{class_open_chams_1_1_port_point}{OpenChams::PortPoint}}*\textcolor{keyword}{>}(start); - cerr << \textcolor{stringliteral}{"<"} << pP->\mbox{\hyperlink{class_open_chams_1_1_port_point_ab4018980dcd1fed5208e7a72846cd815}{getIndex}}() << \textcolor{stringliteral}{"> "}; - \} - \textcolor{keywordflow}{for} (\textcolor{keywordtype}{size\_t} k = 0 ; k < wire->\mbox{\hyperlink{class_open_chams_1_1_wire_aac2840e22e03db0ff2c0fe0f83c56fdd}{getIntermediatePoints}}().size() ; - k++) \{ - \mbox{\hyperlink{class_open_chams_1_1_intermediate_point}{OpenChams::IntermediatePoint}}* iP = wire-> - \mbox{\hyperlink{class_open_chams_1_1_wire_aac2840e22e03db0ff2c0fe0f83c56fdd}{getIntermediatePoints}}()[k]; - cerr << \textcolor{stringliteral}{"<"} << iP->\mbox{\hyperlink{class_open_chams_1_1_intermediate_point_a2b69e4312b7814c6efce42f851893409}{getX}}() << \textcolor{stringliteral}{","} << iP->\mbox{\hyperlink{class_open_chams_1_1_intermediate_point_a15f19cf52955c8c3406831b288681358}{getY}}() << \textcolor{stringliteral}{"> "}; - \} - \mbox{\hyperlink{class_open_chams_1_1_wire_point}{OpenChams::WirePoint}}* end = wire-> - \mbox{\hyperlink{class_open_chams_1_1_wire_ab1c91025a4117cede119f53d9eb8093b}{getEndPoint}}(); - \textcolor{keywordflow}{if} (dynamic\_cast(end)) \{ - \mbox{\hyperlink{class_open_chams_1_1_instance_point}{OpenChams::InstancePoint}}* iP = \textcolor{keyword}{static\_cast<} - \mbox{\hyperlink{class_open_chams_1_1_instance_point}{OpenChams::InstancePoint}}*\textcolor{keyword}{>}(end); - cerr << \textcolor{stringliteral}{"<"} << iP->\mbox{\hyperlink{class_open_chams_1_1_instance_point_a2858c0c4e8b5108f041237cf5a802029}{getName}}().getString() << \textcolor{stringliteral}{","} << iP-> - \mbox{\hyperlink{class_open_chams_1_1_instance_point_a646d464666fc56ab2e04a6b87fdd3279}{getPlug}}().getString() << \textcolor{stringliteral}{"> "}; - \} \textcolor{keywordflow}{else} \textcolor{keywordflow}{if} (dynamic\_cast(end)) \{ - \mbox{\hyperlink{class_open_chams_1_1_port_point}{OpenChams::PortPoint}}* pP = \textcolor{keyword}{static\_cast<} - \mbox{\hyperlink{class_open_chams_1_1_port_point}{OpenChams::PortPoint}}*\textcolor{keyword}{>}(end); - cerr << \textcolor{stringliteral}{"<"} << pP->\mbox{\hyperlink{class_open_chams_1_1_port_point_ab4018980dcd1fed5208e7a72846cd815}{getIndex}}() << \textcolor{stringliteral}{"> "}; - \} - cerr << endl; - \} - \} - - \} - \} - - \} - \mbox{\hyperlink{class_open_chams_1_1_sizing}{OpenChams::Sizing}}* sizing = circuit->\mbox{\hyperlink{class_open_chams_1_1_circuit_a0ce52bc8747f684ec0123faa8ff97b6d}{getSizing}}(); - \textcolor{keywordflow}{if} (sizing) \{ - cerr << \textcolor{stringliteral}{" + sizing"} << endl; - \textcolor{keywordflow}{if} (!sizing->\mbox{\hyperlink{class_open_chams_1_1_sizing_ac8a299add4fd32ff8bf99c889f4a79a6}{hasNoOperators}}()) \{ - \textcolor{keywordflow}{for} (map::const\_iterator oit = sizing-> - \mbox{\hyperlink{class_open_chams_1_1_sizing_ad35c9083b30dac45186f4f0eb49b435d}{getOperators}}().begin() ; oit != sizing->\mbox{\hyperlink{class_open_chams_1_1_sizing_ad35c9083b30dac45186f4f0eb49b435d}{getOperators}}().end() ; ++oit) \{ - \mbox{\hyperlink{class_open_chams_1_1_operator}{OpenChams::Operator}}* op = (*oit).second; - cerr << \textcolor{stringliteral}{" | + instance name: "} << ((*oit).first).getString() << \textcolor{stringliteral}{" - operator: "} << op-> - \mbox{\hyperlink{class_open_chams_1_1_operator_a2858c0c4e8b5108f041237cf5a802029}{getName}}().getString() << \textcolor{stringliteral}{" - simulModel: "} << op->\mbox{\hyperlink{class_open_chams_1_1_operator_aa189a1b119b44a8877c478e2d2357a89}{getSimulModel}}().getString() << endl; - \textcolor{keywordflow}{if} (!op->\mbox{\hyperlink{class_open_chams_1_1_operator_a9ac68ad3e43b1649a8582c8685f4886d}{hasNoConstraints}}()) \{ - \textcolor{keywordflow}{for} (map::const\_iterator cit = op-> - \mbox{\hyperlink{class_open_chams_1_1_operator_a0002889b395185948d7c71b261343620}{getConstraints}}().begin() ; cit != op->\mbox{\hyperlink{class_open_chams_1_1_operator_a0002889b395185948d7c71b261343620}{getConstraints}}().end() ; ++cit) \{ - \mbox{\hyperlink{class_open_chams_1_1_operator_1_1_constraint}{OpenChams::Operator::Constraint}}* cstr = (*cit). - second; - cerr << \textcolor{stringliteral}{" | | + param: "} << ((*cit).first).getString() << \textcolor{stringliteral}{" - ref: "} << cstr-> - \mbox{\hyperlink{class_open_chams_1_1_operator_1_1_constraint_a07cf74adaf661f0aaaa1818d24c2243d}{getRef}}().getString() << \textcolor{stringliteral}{" - refParam: "} << cstr->\mbox{\hyperlink{class_open_chams_1_1_operator_1_1_constraint_a621539b1a4f31053649031c8034b0bd3}{getRefParam}}().getString() << \textcolor{stringliteral}{" - factor: - "} << cstr->\mbox{\hyperlink{class_open_chams_1_1_operator_1_1_constraint_a973fc85365f2d3f07007d88a90d7ab1d}{getFactor}}() << endl; - \} - \} - \} - \} - \textcolor{comment}{// To update to the new equations.} - \textcolor{comment}{// if (!sizing->hasNoEquations()) \{} - \textcolor{comment}{// cerr << " | + equations" << endl;} - \textcolor{comment}{// for (map::const\_iterator eit = sizing->getEquations().begin() ; eit - != sizing->getEquations().end() ; ++eit) \{} - \textcolor{comment}{// cerr << " | | " << ((*eit).first).getString() << " : " << (*eit).second << endl;} - \textcolor{comment}{// \}} - \textcolor{comment}{// \}} - \} - \mbox{\hyperlink{class_open_chams_1_1_layout}{OpenChams::Layout}}* layout = circuit->\mbox{\hyperlink{class_open_chams_1_1_circuit_a403a908943f9a3e820fd25a86d00531d}{getLayout}}(); - \textcolor{keywordflow}{if} (layout) \{ - \textcolor{keywordflow}{if} (!layout->\mbox{\hyperlink{class_open_chams_1_1_layout_af27a31f10fcf22daa64f35c9c6bd2cda}{hasNoInstance}}()) \{ - cerr << \textcolor{stringliteral}{" + layout"} << endl; - \textcolor{keywordflow}{for} (map::const\_iterator lit = layout-> - \mbox{\hyperlink{class_open_chams_1_1_layout_ab0550a9050b7e788b2a18452c9df21f7}{getInstances}}().begin() ; lit != layout->\mbox{\hyperlink{class_open_chams_1_1_layout_ab0550a9050b7e788b2a18452c9df21f7}{getInstances}}().end() ; ++lit) \{ - cerr << \textcolor{stringliteral}{" | | instance name: "} << ((*lit).first).getString() << \textcolor{stringliteral}{" - style: "} << ((*lit).second - ).getString() << endl; - \} - \} - \mbox{\hyperlink{class_open_chams_1_1_node}{OpenChams::Node}}* root = layout->\mbox{\hyperlink{class_open_chams_1_1_layout_a13df4992219ef28a7dc014e9f5f0566a}{getHBTreeRoot}}(); - \textcolor{keywordflow}{if} (root) \{ - cerr << \textcolor{stringliteral}{" | + hbtree"} << endl; - printHBTree(root, 2); - \} - \} - - - \textcolor{keywordflow}{return} 0; -\} - \end{DoxyCodeInclude} \hypertarget{openchams_openChamsDriveC}{}\subsubsection{Driver}\label{openchams_openChamsDriveC} This C++ code ({\ttfamily drive\+Open\+Chams.\+cpp}) generates an inverter.\+xml file equivalent to the included one. \begin{DoxyCodeInclude} -\textcolor{preprocessor}{#include } -\textcolor{keyword}{using namespace }\mbox{\hyperlink{namespacestd}{std}}; - -\textcolor{preprocessor}{#include "vlsisapd/openChams/Circuit.h"} -\textcolor{preprocessor}{#include "vlsisapd/openChams/Netlist.h"} -\textcolor{preprocessor}{#include "vlsisapd/openChams/Instance.h"} -\textcolor{preprocessor}{#include "vlsisapd/openChams/Device.h"} -\textcolor{preprocessor}{#include "vlsisapd/openChams/Transistor.h"} -\textcolor{preprocessor}{#include "vlsisapd/openChams/Net.h"} -\textcolor{preprocessor}{#include "vlsisapd/openChams/Schematic.h"} -\textcolor{preprocessor}{#include "vlsisapd/openChams/Sizing.h"} -\textcolor{preprocessor}{#include "vlsisapd/openChams/Operator.h"} -\textcolor{preprocessor}{#include "vlsisapd/openChams/Layout.h"} -\textcolor{preprocessor}{#include "vlsisapd/openChams/Node.h"} -\textcolor{preprocessor}{#include "vlsisapd/openChams/Port.h"} -\textcolor{preprocessor}{#include "vlsisapd/openChams/Wire.h"} - -\textcolor{keywordtype}{int} main(\textcolor{keywordtype}{int} argc, \textcolor{keywordtype}{char} * argv[]) \{ - \mbox{\hyperlink{class_open_chams_1_1_circuit}{OpenChams::Circuit}}* circuit = \textcolor{keyword}{new} \mbox{\hyperlink{class_open_chams_1_1_circuit}{OpenChams::Circuit}}( - OpenChams::Name(\textcolor{stringliteral}{"design"}), OpenChams::Name(\textcolor{stringliteral}{"myTech"})); - \textcolor{comment}{// value parameters} - circuit->addParameter(OpenChams::Name(\textcolor{stringliteral}{"temp"}), \textcolor{stringliteral}{"27.0"} ); - circuit->addParameter(OpenChams::Name(\textcolor{stringliteral}{"Vdd"}) , \textcolor{stringliteral}{"1.2"} ); - circuit->addParameter(OpenChams::Name(\textcolor{stringliteral}{"Vss"}) , \textcolor{stringliteral}{"0.0"} ); - circuit->addParameter(OpenChams::Name(\textcolor{stringliteral}{"L"}) , \textcolor{stringliteral}{"0.1e-6"}); - circuit->addParameter(OpenChams::Name(\textcolor{stringliteral}{"Ids"}) , \textcolor{stringliteral}{"30e-6"} ); - circuit->addParameter(OpenChams::Name(\textcolor{stringliteral}{"Veg"}) , \textcolor{stringliteral}{"0.12"} ); - \textcolor{comment}{// equation parameters} - circuit->addParameter(OpenChams::Name(\textcolor{stringliteral}{"complex"}), \textcolor{stringliteral}{"myEq"}); - - \textcolor{comment}{// netlist} - \mbox{\hyperlink{class_open_chams_1_1_netlist}{OpenChams::Netlist}}* netlist = circuit->\mbox{\hyperlink{class_open_chams_1_1_circuit_a3f11671c7ea7b4e2cc3487bd7954b667}{createNetlist}}(); - \textcolor{comment}{// instances} - \textcolor{comment}{// nmos1} - \mbox{\hyperlink{class_open_chams_1_1_device}{OpenChams::Device}}* inst\_nmos1 = netlist->\mbox{\hyperlink{class_open_chams_1_1_netlist_a8e1798a2516c32fbab629ce8d60d4b1d}{addDevice}}(OpenChams::Name(\textcolor{stringliteral}{"nmos1"}), - OpenChams::Name(\textcolor{stringliteral}{"Transistor"}), 1, OpenChams::Name(\textcolor{stringliteral}{"NMOS"}), \textcolor{keyword}{true}); - inst\_nmos1->addConnector(OpenChams::Name(\textcolor{stringliteral}{"G"})); - inst\_nmos1->addConnector(OpenChams::Name(\textcolor{stringliteral}{"S"})); - inst\_nmos1->addConnector(OpenChams::Name(\textcolor{stringliteral}{"D"})); - \mbox{\hyperlink{class_open_chams_1_1_transistor}{OpenChams::Transistor}}* tr\_nmos1 = inst\_nmos1-> - \mbox{\hyperlink{class_open_chams_1_1_device_ad45d34f8765dd113a5b12289efe66c07}{addTransistor}}(OpenChams::Name(\textcolor{stringliteral}{"m1"})); - tr\_nmos1->\mbox{\hyperlink{class_open_chams_1_1_transistor_a705b53a51f0e265533b228f6e8beaf50}{setGate}} (OpenChams::Name(\textcolor{stringliteral}{"G"})); \textcolor{comment}{// the name of the connector of inst\_nmos1} - tr\_nmos1->\mbox{\hyperlink{class_open_chams_1_1_transistor_abc4a5d86e639ea13e27551722e2f9c17}{setSource}}(OpenChams::Name(\textcolor{stringliteral}{"S"})); - tr\_nmos1->\mbox{\hyperlink{class_open_chams_1_1_transistor_a72ff8491040e3fdc1c8bd62b2392ab82}{setDrain}} (OpenChams::Name(\textcolor{stringliteral}{"D"})); - tr\_nmos1->\mbox{\hyperlink{class_open_chams_1_1_transistor_a1484abe63e3f8ffbc2911c5230fa7091}{setBulk}} (OpenChams::Name(\textcolor{stringliteral}{"S"})); - \textcolor{comment}{// pmos1} - \mbox{\hyperlink{class_open_chams_1_1_device}{OpenChams::Device}}* inst\_pmos1 = netlist->\mbox{\hyperlink{class_open_chams_1_1_netlist_a8e1798a2516c32fbab629ce8d60d4b1d}{addDevice}}(OpenChams::Name(\textcolor{stringliteral}{"pmos1"}), - OpenChams::Name(\textcolor{stringliteral}{"Transistor"}), 2, OpenChams::Name(\textcolor{stringliteral}{"PMOS"}), \textcolor{keyword}{true}); - inst\_pmos1->addConnector(OpenChams::Name(\textcolor{stringliteral}{"G"})); - inst\_pmos1->addConnector(OpenChams::Name(\textcolor{stringliteral}{"S"})); - inst\_pmos1->addConnector(OpenChams::Name(\textcolor{stringliteral}{"D"})); - \mbox{\hyperlink{class_open_chams_1_1_transistor}{OpenChams::Transistor}}* tr\_pmos1 = inst\_pmos1-> - \mbox{\hyperlink{class_open_chams_1_1_device_ad45d34f8765dd113a5b12289efe66c07}{addTransistor}}(OpenChams::Name(\textcolor{stringliteral}{"m1"})); - tr\_pmos1->\mbox{\hyperlink{class_open_chams_1_1_transistor_a705b53a51f0e265533b228f6e8beaf50}{setGate}} (OpenChams::Name(\textcolor{stringliteral}{"G"})); \textcolor{comment}{// the name of the connector of inst\_pmos1} - tr\_pmos1->\mbox{\hyperlink{class_open_chams_1_1_transistor_abc4a5d86e639ea13e27551722e2f9c17}{setSource}}(OpenChams::Name(\textcolor{stringliteral}{"S"})); - tr\_pmos1->\mbox{\hyperlink{class_open_chams_1_1_transistor_a72ff8491040e3fdc1c8bd62b2392ab82}{setDrain}} (OpenChams::Name(\textcolor{stringliteral}{"D"})); - tr\_pmos1->\mbox{\hyperlink{class_open_chams_1_1_transistor_a1484abe63e3f8ffbc2911c5230fa7091}{setBulk}} (OpenChams::Name(\textcolor{stringliteral}{"S"})); - \textcolor{comment}{// nets} - \mbox{\hyperlink{class_open_chams_1_1_net}{OpenChams::Net}}* \_vdd = netlist->\mbox{\hyperlink{class_open_chams_1_1_netlist_a52be455a704925328843770552eca43d}{addNet}}(OpenChams::Name(\textcolor{stringliteral}{"vdd"}), OpenChams::Name(\textcolor{stringliteral}{" - power"}) , \textcolor{keyword}{true}); - \mbox{\hyperlink{class_open_chams_1_1_net}{OpenChams::Net}}* \_vss = netlist->\mbox{\hyperlink{class_open_chams_1_1_netlist_a52be455a704925328843770552eca43d}{addNet}}(OpenChams::Name(\textcolor{stringliteral}{"vss"}), OpenChams::Name(\textcolor{stringliteral}{" - ground"}) , \textcolor{keyword}{true}); - \mbox{\hyperlink{class_open_chams_1_1_net}{OpenChams::Net}}* \_in = netlist->\mbox{\hyperlink{class_open_chams_1_1_netlist_a52be455a704925328843770552eca43d}{addNet}}(OpenChams::Name(\textcolor{stringliteral}{"in"} ), OpenChams::Name(\textcolor{stringliteral}{" - logical"}), \textcolor{keyword}{true}); - \mbox{\hyperlink{class_open_chams_1_1_net}{OpenChams::Net}}* \_out = netlist->\mbox{\hyperlink{class_open_chams_1_1_netlist_a52be455a704925328843770552eca43d}{addNet}}(OpenChams::Name(\textcolor{stringliteral}{"out"}), OpenChams::Name(\textcolor{stringliteral}{" - logical"}), \textcolor{keyword}{true}); - \_vdd->\mbox{\hyperlink{class_open_chams_1_1_net_a40c2c019175ba3bfa4b90f4ad5d06483}{connectTo}}(OpenChams::Name(\textcolor{stringliteral}{"pmos1"}), OpenChams::Name(\textcolor{stringliteral}{"S"})); - \_vss->\mbox{\hyperlink{class_open_chams_1_1_net_a40c2c019175ba3bfa4b90f4ad5d06483}{connectTo}}(OpenChams::Name(\textcolor{stringliteral}{"nmos1"}), OpenChams::Name(\textcolor{stringliteral}{"S"})); - \_in->\mbox{\hyperlink{class_open_chams_1_1_net_a40c2c019175ba3bfa4b90f4ad5d06483}{connectTo}} (OpenChams::Name(\textcolor{stringliteral}{"nmos1"}), OpenChams::Name(\textcolor{stringliteral}{"G"})); - \_in->\mbox{\hyperlink{class_open_chams_1_1_net_a40c2c019175ba3bfa4b90f4ad5d06483}{connectTo}} (OpenChams::Name(\textcolor{stringliteral}{"pmos1"}), OpenChams::Name(\textcolor{stringliteral}{"G"})); - \_out->\mbox{\hyperlink{class_open_chams_1_1_net_a40c2c019175ba3bfa4b90f4ad5d06483}{connectTo}}(OpenChams::Name(\textcolor{stringliteral}{"nmos1"}), OpenChams::Name(\textcolor{stringliteral}{"D"})); - \_out->\mbox{\hyperlink{class_open_chams_1_1_net_a40c2c019175ba3bfa4b90f4ad5d06483}{connectTo}}(OpenChams::Name(\textcolor{stringliteral}{"pmos1"}), OpenChams::Name(\textcolor{stringliteral}{"D"})); - - \textcolor{comment}{// schematic} - \mbox{\hyperlink{class_open_chams_1_1_schematic}{OpenChams::Schematic}}* schematic = circuit-> - \mbox{\hyperlink{class_open_chams_1_1_circuit_a57a79a9916df4512648bb195decb7250}{createSchematic}}(); - schematic->\mbox{\hyperlink{class_open_chams_1_1_schematic_ac7fc9f5cdf1e22c53d42e6606e1af8ef}{addInstance}}(OpenChams::Name(\textcolor{stringliteral}{"nmos1"}), 2490, 2600, OpenChams::Name(\textcolor{stringliteral}{"ID"})); - schematic->\mbox{\hyperlink{class_open_chams_1_1_schematic_ac7fc9f5cdf1e22c53d42e6606e1af8ef}{addInstance}}(OpenChams::Name(\textcolor{stringliteral}{"pmos1"}), 2490, 2300, OpenChams::Name(\textcolor{stringliteral}{"ID"})); - \_vdd->\mbox{\hyperlink{class_open_chams_1_1_net_af395a7c9d6f3c2b24500b91260873664}{addPort}}(OpenChams::Name(\textcolor{stringliteral}{"inV"}), 0, 2490, 2100, OpenChams::Name(\textcolor{stringliteral}{"ID"})); - \mbox{\hyperlink{class_open_chams_1_1_wire}{OpenChams::Wire}}* wVdd = \_vdd->\mbox{\hyperlink{class_open_chams_1_1_net_a643a969f62770301b8b70ed63c36a55e}{addWire}}(); - wVdd->setStartPoint(OpenChams::Name(\textcolor{stringliteral}{"pmos1"}), OpenChams::Name(\textcolor{stringliteral}{"S"})); - wVdd->setEndPoint (0); - \_vss->\mbox{\hyperlink{class_open_chams_1_1_net_af395a7c9d6f3c2b24500b91260873664}{addPort}}(OpenChams::Name(\textcolor{stringliteral}{"inV"}), 0, 2490, 2800, OpenChams::Name(\textcolor{stringliteral}{"MY"})); - \mbox{\hyperlink{class_open_chams_1_1_wire}{OpenChams::Wire}}* wVss = \_vss->\mbox{\hyperlink{class_open_chams_1_1_net_a643a969f62770301b8b70ed63c36a55e}{addWire}}(); - wVss->setStartPoint(OpenChams::Name(\textcolor{stringliteral}{"nmos1"}), OpenChams::Name(\textcolor{stringliteral}{"S"})); - wVss->setEndPoint (0); - \_in->\mbox{\hyperlink{class_open_chams_1_1_net_af395a7c9d6f3c2b24500b91260873664}{addPort}}(OpenChams::Name(\textcolor{stringliteral}{"inH"}), 0, 2190, 2500, OpenChams::Name(\textcolor{stringliteral}{"ID"})); - \mbox{\hyperlink{class_open_chams_1_1_wire}{OpenChams::Wire}}* wIn = \_in->\mbox{\hyperlink{class_open_chams_1_1_net_a643a969f62770301b8b70ed63c36a55e}{addWire}}(); - wIn->setStartPoint(OpenChams::Name(\textcolor{stringliteral}{"pmos1"}), OpenChams::Name(\textcolor{stringliteral}{"G"})); - wIn->setEndPoint (OpenChams::Name(\textcolor{stringliteral}{"nmos1"}), OpenChams::Name(\textcolor{stringliteral}{"G"})); - \mbox{\hyperlink{class_open_chams_1_1_wire}{OpenChams::Wire}}* wIn1 = \_in->\mbox{\hyperlink{class_open_chams_1_1_net_a643a969f62770301b8b70ed63c36a55e}{addWire}}(); - wIn1->setStartPoint(0); - wIn1->setEndPoint (OpenChams::Name(\textcolor{stringliteral}{"pmos1"}), OpenChams::Name(\textcolor{stringliteral}{"G"})); - \_out->\mbox{\hyperlink{class_open_chams_1_1_net_af395a7c9d6f3c2b24500b91260873664}{addPort}}(OpenChams::Name(\textcolor{stringliteral}{"outH"}), 0, 2600, 2500, OpenChams::Name(\textcolor{stringliteral}{"ID"})); - \mbox{\hyperlink{class_open_chams_1_1_wire}{OpenChams::Wire}}* wOut = \_out->\mbox{\hyperlink{class_open_chams_1_1_net_a643a969f62770301b8b70ed63c36a55e}{addWire}}(); - wOut->setStartPoint(OpenChams::Name(\textcolor{stringliteral}{"pmos1"}), OpenChams::Name(\textcolor{stringliteral}{"D"})); - wOut->setEndPoint (OpenChams::Name(\textcolor{stringliteral}{"nmos1"}), OpenChams::Name(\textcolor{stringliteral}{"D"})); - \mbox{\hyperlink{class_open_chams_1_1_wire}{OpenChams::Wire}}* wOut1 = \_out->\mbox{\hyperlink{class_open_chams_1_1_net_a643a969f62770301b8b70ed63c36a55e}{addWire}}(); - wOut1->setStartPoint(OpenChams::Name(\textcolor{stringliteral}{"nmos1"}), OpenChams::Name(\textcolor{stringliteral}{"D"})); - wOut1->setEndPoint (0); - - \textcolor{comment}{// sizing} - \mbox{\hyperlink{class_open_chams_1_1_sizing}{OpenChams::Sizing}}* sizing = circuit->createSizing(); - \mbox{\hyperlink{class_open_chams_1_1_operator}{OpenChams::Operator}}* op\_pmos1 = sizing->\mbox{\hyperlink{class_open_chams_1_1_sizing_a712e045c11e463cff8411b3d0fd7f732}{addOperator}}(OpenChams::Name(\textcolor{stringliteral}{" - pmos1"}), OpenChams::Name(\textcolor{stringliteral}{"OPVG(Veg)"}), OpenChams::Name(\textcolor{stringliteral}{"BSIM3V3"})); - op\_pmos1->addConstraint(OpenChams::Name(\textcolor{stringliteral}{"Temp"}), OpenChams::Name(\textcolor{stringliteral}{"design"}), OpenChams::Name(\textcolor{stringliteral}{"temp"})); - op\_pmos1->addConstraint(OpenChams::Name(\textcolor{stringliteral}{"Ids"}) , OpenChams::Name(\textcolor{stringliteral}{"design"}), OpenChams::Name(\textcolor{stringliteral}{"Ids"}) ); - op\_pmos1->addConstraint(OpenChams::Name(\textcolor{stringliteral}{"L"}) , OpenChams::Name(\textcolor{stringliteral}{"design"}), OpenChams::Name(\textcolor{stringliteral}{"L"}) ); - op\_pmos1->addConstraint(OpenChams::Name(\textcolor{stringliteral}{"Veg"}) , OpenChams::Name(\textcolor{stringliteral}{"design"}), OpenChams::Name(\textcolor{stringliteral}{"Veg"}) ); - op\_pmos1->addConstraint(OpenChams::Name(\textcolor{stringliteral}{"Vd"}) , OpenChams::Name(\textcolor{stringliteral}{"design"}), OpenChams::Name(\textcolor{stringliteral}{"Vdd"}) , 0. - 5); - op\_pmos1->addConstraint(OpenChams::Name(\textcolor{stringliteral}{"Vs"}) , OpenChams::Name(\textcolor{stringliteral}{"design"}), OpenChams::Name(\textcolor{stringliteral}{"Vdd"}) ); - \mbox{\hyperlink{class_open_chams_1_1_operator}{OpenChams::Operator}}* op\_nmos1 = sizing->\mbox{\hyperlink{class_open_chams_1_1_sizing_a712e045c11e463cff8411b3d0fd7f732}{addOperator}}(OpenChams::Name(\textcolor{stringliteral}{" - nmos1"}), OpenChams::Name(\textcolor{stringliteral}{"OPW(Vg,Vs)"}), OpenChams::Name(\textcolor{stringliteral}{"BSIM3V3"})); - op\_nmos1->addConstraint(OpenChams::Name(\textcolor{stringliteral}{"Temp"}), OpenChams::Name(\textcolor{stringliteral}{"design"}), OpenChams::Name(\textcolor{stringliteral}{"temp"})); - op\_nmos1->addConstraint(OpenChams::Name(\textcolor{stringliteral}{"Ids"}) , OpenChams::Name(\textcolor{stringliteral}{"design"}), OpenChams::Name(\textcolor{stringliteral}{"Ids"} )); - op\_nmos1->addConstraint(OpenChams::Name(\textcolor{stringliteral}{"L"}) , OpenChams::Name(\textcolor{stringliteral}{"design"}), OpenChams::Name(\textcolor{stringliteral}{"L"} )); - op\_nmos1->addConstraint(OpenChams::Name(\textcolor{stringliteral}{"Vs"}) , OpenChams::Name(\textcolor{stringliteral}{"design"}), OpenChams::Name(\textcolor{stringliteral}{"Vdd"} )); - op\_nmos1->addConstraint(OpenChams::Name(\textcolor{stringliteral}{"Vg"}) , OpenChams::Name(\textcolor{stringliteral}{"pmos1"}) , OpenChams::Name(\textcolor{stringliteral}{"Vg"} )); - op\_nmos1->addConstraint(OpenChams::Name(\textcolor{stringliteral}{"Vd"}) , OpenChams::Name(\textcolor{stringliteral}{"pmos1"}) , OpenChams::Name(\textcolor{stringliteral}{"Vd"} )); - op\_nmos1->addConstraint(OpenChams::Name(\textcolor{stringliteral}{"another"}), OpenChams::Name(\textcolor{stringliteral}{"myEq"}), -2.5 ); - \textcolor{comment}{// layout} - \mbox{\hyperlink{class_open_chams_1_1_layout}{OpenChams::Layout}}* layout = circuit->\mbox{\hyperlink{class_open_chams_1_1_circuit_a725a691b0117c4b913b54e7bfd92832f}{createLayout}}(); - layout->\mbox{\hyperlink{class_open_chams_1_1_layout_a4cc1899e9b782de44700fa0e4ac477ef}{addInstance}}(OpenChams::Name(\textcolor{stringliteral}{"pmos1"}), OpenChams::Name(\textcolor{stringliteral}{"Common transistor"})); - layout->\mbox{\hyperlink{class_open_chams_1_1_layout_a4cc1899e9b782de44700fa0e4ac477ef}{addInstance}}(OpenChams::Name(\textcolor{stringliteral}{"nmos1"}), OpenChams::Name(\textcolor{stringliteral}{"Rotate transistor"})); - \textcolor{comment}{// create hbtree} - \mbox{\hyperlink{class_open_chams_1_1_group}{OpenChams::Group}}* g1 = \textcolor{keyword}{new} \mbox{\hyperlink{class_open_chams_1_1_group}{OpenChams::Group}}(\textcolor{stringliteral}{"g1"}); \textcolor{comment}{// default position - is NONE and default parent is NULL} - g1->\mbox{\hyperlink{class_open_chams_1_1_group_a9fc27b2bc4da99c723102153c4fbf1c0}{setAlign}}(OpenChams::Group::VERTICAL); - \mbox{\hyperlink{class_open_chams_1_1_bloc}{OpenChams::Bloc}}* b1 = \textcolor{keyword}{new} \mbox{\hyperlink{class_open_chams_1_1_bloc}{OpenChams::Bloc}}(\textcolor{stringliteral}{"nmos1"}, OpenChams::Node::NONE, - g1); - g1->\mbox{\hyperlink{class_open_chams_1_1_group_adc93b900e943312e905182fe44f21225}{setRootNode}}(b1); \textcolor{comment}{// b1 is root node of group g1} - \mbox{\hyperlink{class_open_chams_1_1_bloc}{OpenChams::Bloc}}* b2 = \textcolor{keyword}{new} \mbox{\hyperlink{class_open_chams_1_1_bloc}{OpenChams::Bloc}}(\textcolor{stringliteral}{"pmos1"}, OpenChams::Node::TOP, - b1); - b1->\mbox{\hyperlink{class_open_chams_1_1_node_a32e2fbbb73c6b7ee4a30189cc30106bf}{setTop}}(b2); \textcolor{comment}{// b2 is on top of b1} - layout->\mbox{\hyperlink{class_open_chams_1_1_layout_a6d828958e0faf1346b27276eab101858}{setHBTreeRoot}}(g1); \textcolor{comment}{// g1 is the root of the tree} - - circuit->\mbox{\hyperlink{class_open_chams_1_1_circuit_a2eb07935ec946a07edcee2255b781193}{writeToFile}}(\textcolor{stringliteral}{"./myInverter.xml"}); - \textcolor{keywordflow}{return} 0; -\} - \end{DoxyCodeInclude} @@ -709,243 +77,10 @@ In order to compile these codes, a C\+Make\+Lists.\+txt file is provided. User m \hypertarget{openchams_openChamsParsePython}{}\subsubsection{Parser}\label{openchams_openChamsParsePython} The following python script ({\ttfamily parse\+Open\+Chams.\+py}) is an example of how to parse a O\+P\+E\+N\+C\+H\+A\+MS file using python module. \begin{DoxyCodeInclude} -\textcolor{keyword}{import} sys - -\textcolor{keyword}{from} OPENCHAMS \textcolor{keyword}{import} * - -\textcolor{keyword}{def }printHBTree(node, indent): - \textcolor{keywordflow}{if} node == \textcolor{keywordtype}{None}: - \textcolor{keywordflow}{return} - \textcolor{keywordflow}{for} i \textcolor{keywordflow}{in} range(indent): - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" |"}, - \textcolor{keywordflow}{if} isinstance(node, Bloc): - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" bloc:"}, node.getName(), \textcolor{stringliteral}{"-"}, node.getPosition() - printHBTree(node.top , indent+1) - printHBTree(node.right, indent+1) - \textcolor{keywordflow}{return} - \textcolor{keywordflow}{if} isinstance(node, Group): - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" group:"}, node.getName(), \textcolor{stringliteral}{"-"}, node.getPosition(), \textcolor{stringliteral}{"-"}, node.align, \textcolor{stringliteral}{"-"}, node.isolated, \textcolor{stringliteral}{"-"}, - node.paired - printHBTree(node.rootNode, indent+1) - printHBTree(node.top , indent+1) - printHBTree(node.right , indent+1) - \textcolor{keywordflow}{return} - -\textcolor{keyword}{def }printContents(circuit): - \textcolor{keywordflow}{print} circuit.name - \textcolor{comment}{# circuit parameters} - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" + parameters"} - \textcolor{keywordflow}{for} param \textcolor{keywordflow}{in} circuit.parameters.getValues(): - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | |"}, param.key, \textcolor{stringliteral}{":"}, param.value - \textcolor{keywordflow}{for} param \textcolor{keywordflow}{in} circuit.parameters.getEqValues(): - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | |"}, param.key, \textcolor{stringliteral}{":"}, param.value - \textcolor{comment}{# netlist} - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" + netlist"} - \textcolor{comment}{# instances} - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | + instances"} - \textcolor{keywordflow}{for} instance \textcolor{keywordflow}{in} circuit.netlist.getInstances(): - \textcolor{keywordflow}{if} isinstance(instance, Device): - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | +"}, instance.name, \textcolor{stringliteral}{":"}, instance.model, instance.order, instance.mosType, - instance.sourceBulkConnected - \textcolor{keywordflow}{else}: - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | +"}, instance.name, \textcolor{stringliteral}{":"}, instance.model, instance.order - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | | + connectors"} - \textcolor{keywordflow}{for} conn \textcolor{keywordflow}{in} instance.getConnectors(): - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | | |"}, conn.key, \textcolor{stringliteral}{":"}, conn.value.name - \textcolor{keywordflow}{if} isinstance(instance, Device): - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | | + transistors"} - \textcolor{keywordflow}{for} tr \textcolor{keywordflow}{in} instance.getTransistors(): - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | | | name:"}, tr.name, \textcolor{stringliteral}{"- gate:"}, tr.gate, \textcolor{stringliteral}{"- source:"}, tr.source, \textcolor{stringliteral}{"- drain:"}, tr.drain, \textcolor{stringliteral}{ - "- bulk:"}, tr.bulk - \textcolor{comment}{# nets} - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | + nets"} - schematicNet = \textcolor{keyword}{False} - \textcolor{keywordflow}{for} net \textcolor{keywordflow}{in} circuit.netlist.getNets(): - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | +"}, net.name, \textcolor{stringliteral}{":"}, net.type, net.external - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | | + connections"} - \textcolor{keywordflow}{for} conn \textcolor{keywordflow}{in} net.getConnections(): - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | | | %s.%s"}%(conn.instanceName, conn.connectorName) - \textcolor{keywordflow}{if} \textcolor{keywordflow}{not} net.hasNoPorts() \textcolor{keywordflow}{or} \textcolor{keywordflow}{not} net.hasNoWires(): - schematicNet = \textcolor{keyword}{True} - \textcolor{comment}{# schematic} - \textcolor{keywordflow}{if} (circuit.schematic): - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" + schematic"} - \textcolor{keywordflow}{for} instance \textcolor{keywordflow}{in} circuit.schematic.getInstances(): - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | + instance name:"}, instance.key, \textcolor{stringliteral}{"- x:"}, instance.value.x, \textcolor{stringliteral}{"- y:"}, instance.value.y, \textcolor{stringliteral}{"- - orientation:"}, instance.value.orientation - \textcolor{keywordflow}{if} schematicNet: - \textcolor{keywordflow}{for} net \textcolor{keywordflow}{in} circuit.netlist.getNets(): - \textcolor{keywordflow}{if} net.hasNoPorts() \textcolor{keywordflow}{and} net.hasNoWires(): - \textcolor{keywordflow}{continue} - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | + net name:"}, net.name - \textcolor{keywordflow}{for} port \textcolor{keywordflow}{in} net.getPorts(): - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | + port type:"}, port.type, \textcolor{stringliteral}{"- idx:"}, port.index, \textcolor{stringliteral}{"- x:"}, port.x, \textcolor{stringliteral}{"- y:"}, port.y, \textcolor{stringliteral}{" - - orientation:"}, port.orientation - \textcolor{keywordflow}{for} wire \textcolor{keywordflow}{in} net.getWires(): - \textcolor{keywordflow}{if} isinstance(wire.startPoint, InstancePoint): - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | + wire <"} + wire.startPoint.name.getString() + \textcolor{stringliteral}{","} + - wire.startPoint.plug.getString() +\textcolor{stringliteral}{">"} - \textcolor{keywordflow}{elif} isinstance(wire.startPoint, PortPoint): - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | + wire <"} + str(wire.startPoint.index) + \textcolor{stringliteral}{">"} - \textcolor{keywordflow}{else}: - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" - - UNKNOWN START POINT"} - \textcolor{keywordflow}{for} point \textcolor{keywordflow}{in} wire.getIntermediatePoints(): - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | <"} + str(point.x) + \textcolor{stringliteral}{","} + str(point.y) + \textcolor{stringliteral}{">"} - \textcolor{keywordflow}{if} isinstance(wire.endPoint, InstancePoint): - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | <"} + wire.endPoint.name.getString() + \textcolor{stringliteral}{","} + - wire.endPoint.plug.getString() +\textcolor{stringliteral}{">"} - \textcolor{keywordflow}{elif} isinstance(wire.endPoint, PortPoint): - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | <"} + str(wire.endPoint.index) + \textcolor{stringliteral}{">"} - \textcolor{keywordflow}{else}: - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" - - UNKNOWN END POINT"} - \textcolor{comment}{# sizing} - \textcolor{keywordflow}{if} (circuit.sizing): - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" + sizing"} - \textcolor{keywordflow}{for} op \textcolor{keywordflow}{in} circuit.sizing.getOperators(): - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | + instance name:"}, op.key, \textcolor{stringliteral}{"- operator:"}, op.value.name, \textcolor{stringliteral}{"- simulModel:"}, - op.value.simulModel - \textcolor{keywordflow}{for} constraint \textcolor{keywordflow}{in} op.value.getConstraints(): - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | + param:"}, constraint.key, \textcolor{stringliteral}{"- ref:"}, constraint.value.ref, \textcolor{stringliteral}{"- refParam:"}, - constraint.value.refParam, \textcolor{stringliteral}{"- factor:"}, constraint.value.factor - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | + equations"} - \textcolor{keywordflow}{for} eq \textcolor{keywordflow}{in} circuit.sizing.getEquations(): - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | |"}, eq.key, \textcolor{stringliteral}{":"}, eq.value - \textcolor{comment}{# layout} - \textcolor{keywordflow}{if} (circuit.layout): - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" + layout"} - \textcolor{keywordflow}{for} inst \textcolor{keywordflow}{in} circuit.layout.getInstances(): - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | instance name:"}, inst.key, \textcolor{stringliteral}{"- style:"}, inst.value - \textcolor{keywordflow}{if} circuit.layout.hbTreeRoot != \textcolor{keywordtype}{None}: - \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | + hbtree"} - printHBTree(circuit.layout.hbTreeRoot, 2) - -\textcolor{keyword}{def }usage(): - \textcolor{keywordflow}{print} \textcolor{stringliteral}{"usage:"}, sys.argv[0], \textcolor{stringliteral}{"[filename]"} - sys.exit(48) - -\textcolor{keyword}{def }main(): - \textcolor{keywordflow}{if} len(sys.argv) == 1: - filename = \textcolor{stringliteral}{"./inverter.xml"} - \textcolor{keywordflow}{elif} len(sys.argv) == 2: - filename = sys.argv[1] - \textcolor{keywordflow}{else}: - usage() - - circuit = Circuit.readFromFile(filename) - printContents(circuit) - - -\textcolor{keywordflow}{if} \_\_name\_\_ == \textcolor{stringliteral}{"\_\_main\_\_"}: - main() - \end{DoxyCodeInclude} \hypertarget{openchams_openChamsDrivePython}{}\subsubsection{Driver}\label{openchams_openChamsDrivePython} This python script ({\ttfamily drive\+Open\+Chams.\+py}) generates an inverter.\+xml file equivalent to the included one. \begin{DoxyCodeInclude} -\textcolor{keyword}{from} OPENCHAMS \textcolor{keyword}{import} * - -circuit = Circuit(\mbox{\hyperlink{class_name}{Name}}(\textcolor{stringliteral}{"design"}), \mbox{\hyperlink{class_name}{Name}}(\textcolor{stringliteral}{"myTech"})) -\textcolor{comment}{# value parameters} -circuit.addParameter(\mbox{\hyperlink{class_name}{Name}}(\textcolor{stringliteral}{"temp"}), 27.0 ) -circuit.addParameter(\mbox{\hyperlink{class_name}{Name}}(\textcolor{stringliteral}{"Vdd"}) , 1.2 ) -circuit.addParameter(\mbox{\hyperlink{class_name}{Name}}(\textcolor{stringliteral}{"Vss"}) , 0.0 ) -circuit.addParameter(\mbox{\hyperlink{class_name}{Name}}(\textcolor{stringliteral}{"L"}) , 0.1e-6) -circuit.addParameter(\mbox{\hyperlink{class_name}{Name}}(\textcolor{stringliteral}{"Ids"}) , 30e-6 ) -circuit.addParameter(\mbox{\hyperlink{class_name}{Name}}(\textcolor{stringliteral}{"Veg"}) , 0.12 ) -\textcolor{comment}{# equation parameters} -circuit.addParameter(\mbox{\hyperlink{class_name}{Name}}(\textcolor{stringliteral}{"complex"}), \textcolor{stringliteral}{"myEq"}) - -\textcolor{comment}{# netlist :} -netlist = circuit.createNetlist() -\textcolor{comment}{# instances} -\textcolor{comment}{# nmos1} -inst\_nmos1 = netlist.addDevice(\textcolor{stringliteral}{"nmos1"}, \textcolor{stringliteral}{"Transistor"}, 1, \textcolor{stringliteral}{"NMOS"}, \textcolor{keyword}{True}) -inst\_nmos1.addConnector(\textcolor{stringliteral}{"G"}) -inst\_nmos1.addConnector(\textcolor{stringliteral}{"S"}) -inst\_nmos1.addConnector(\textcolor{stringliteral}{"D"}) -tr\_nmos1 = inst\_nmos1.addTransistor(\textcolor{stringliteral}{"m1"}) -tr\_nmos1.gate = \textcolor{stringliteral}{"G"} \textcolor{comment}{# the name of the connector of inst\_nmos1} -tr\_nmos1.source = \textcolor{stringliteral}{"S"} -tr\_nmos1.drain = \textcolor{stringliteral}{"D"} -tr\_nmos1.bulk = \textcolor{stringliteral}{"S"} -\textcolor{comment}{# pmos1} -inst\_pmos1 = netlist.addDevice(\textcolor{stringliteral}{"pmos1"}, \textcolor{stringliteral}{"Transistor"}, 2, \textcolor{stringliteral}{"PMOS"}, \textcolor{keyword}{True}) -inst\_pmos1.addConnector(\textcolor{stringliteral}{"G"}) -inst\_pmos1.addConnector(\textcolor{stringliteral}{"S"}) -inst\_pmos1.addConnector(\textcolor{stringliteral}{"D"}) -tr\_pmos1 = inst\_pmos1.addTransistor(\textcolor{stringliteral}{"m1"}) -tr\_pmos1.gate = \textcolor{stringliteral}{"G"} \textcolor{comment}{# the name of the connector of inst\_pmos1} -tr\_pmos1.source = \textcolor{stringliteral}{"S"} -tr\_pmos1.drain = \textcolor{stringliteral}{"D"} -tr\_pmos1.bulk = \textcolor{stringliteral}{"S"} -\textcolor{comment}{# nets} -\_vdd = netlist.addNet(\textcolor{stringliteral}{"vdd"}, \textcolor{stringliteral}{"power"} , \textcolor{keyword}{True}) -\_vss = netlist.addNet(\textcolor{stringliteral}{"vss"}, \textcolor{stringliteral}{"ground"} , \textcolor{keyword}{True}) -\_in = netlist.addNet(\textcolor{stringliteral}{"in"} , \textcolor{stringliteral}{"logical"}, \textcolor{keyword}{True}) -\_out = netlist.addNet(\textcolor{stringliteral}{"out"}, \textcolor{stringliteral}{"logical"}, \textcolor{keyword}{True}) -\_vdd.connectTo(\textcolor{stringliteral}{"pmos1"}, \textcolor{stringliteral}{"S"}) -\_vss.connectTo(\textcolor{stringliteral}{"nmos1"}, \textcolor{stringliteral}{"S"}) -\_in.connectTo (\textcolor{stringliteral}{"nmos1"}, \textcolor{stringliteral}{"G"}) -\_in.connectTo (\textcolor{stringliteral}{"pmos1"}, \textcolor{stringliteral}{"G"}) -\_out.connectTo(\textcolor{stringliteral}{"nmos1"}, \textcolor{stringliteral}{"D"}) -\_out.connectTo(\textcolor{stringliteral}{"pmos1"}, \textcolor{stringliteral}{"D"}) -\textcolor{comment}{# schematic} -schematic = circuit.createSchematic() -schematic.addInstance(\textcolor{stringliteral}{"nmos1"}, 2490, 2600, \textcolor{stringliteral}{"ID"}) -schematic.addInstance(\textcolor{stringliteral}{"pmos1"}, 2490, 2300, \textcolor{stringliteral}{"ID"}) -\_vdd.addPort(\textcolor{stringliteral}{"inV"} , 0, 2490, 2100, \textcolor{stringliteral}{"ID"}) -\_vss.addPort(\textcolor{stringliteral}{"inV"} , 0, 2490, 2800, \textcolor{stringliteral}{"MY"}) -\_in.addPort (\textcolor{stringliteral}{"inH"} , 0, 2190, 2500, \textcolor{stringliteral}{"ID"}) -\_out.addPort(\textcolor{stringliteral}{"outH"}, 0, 2600, 2500, \textcolor{stringliteral}{"ID"}) -wireVdd = \_vdd.addWire() -wireVdd.setStartPoint(\textcolor{stringliteral}{"pmos1"}, \textcolor{stringliteral}{"S"}) -wireVdd.setEndPoint(0) -wireVss = \_vss.addWire() -wireVss.setStartPoint(\textcolor{stringliteral}{"nmos1"}, \textcolor{stringliteral}{"S"}) -wireVss.setEndPoint(0) -wireIn0 = \_in.addWire() -wireIn1 = \_in.addWire() -wireIn0.setStartPoint(\textcolor{stringliteral}{"pmos1"}, \textcolor{stringliteral}{"G"}) -wireIn0.setEndPoint (\textcolor{stringliteral}{"nmos1"}, \textcolor{stringliteral}{"G"}) -wireIn1.setStartPoint(0) -wireIn1.setEndPoint (\textcolor{stringliteral}{"pmos1"}, \textcolor{stringliteral}{"G"}) -wireOut0 = \_out.addWire() -wireOut1 = \_out.addWire() -wireOut0.setStartPoint(\textcolor{stringliteral}{"pmos1"}, \textcolor{stringliteral}{"D"}) -wireOut0.setEndPoint (\textcolor{stringliteral}{"nmos1"}, \textcolor{stringliteral}{"D"}) -wireOut1.setStartPoint(\textcolor{stringliteral}{"nmos1"}, \textcolor{stringliteral}{"D"}) -wireOut1.setEndPoint (0) -\textcolor{comment}{# sizing} -sizing = circuit.createSizing() -op\_pmos1 = sizing.addOperator(\textcolor{stringliteral}{"pmos1"}, \textcolor{stringliteral}{"OPVG(Veg)"} , \textcolor{stringliteral}{"BSIM3V3"}) -op\_pmos1.addConstraint(\textcolor{stringliteral}{"Temp"}, \textcolor{stringliteral}{"design"}, \textcolor{stringliteral}{"temp"}) -op\_pmos1.addConstraint(\textcolor{stringliteral}{"Ids"} , \textcolor{stringliteral}{"design"}, \textcolor{stringliteral}{"Ids"} ) -op\_pmos1.addConstraint(\textcolor{stringliteral}{"L"} , \textcolor{stringliteral}{"design"}, \textcolor{stringliteral}{"L"} ) -op\_pmos1.addConstraint(\textcolor{stringliteral}{"Veg"} , \textcolor{stringliteral}{"design"}, \textcolor{stringliteral}{"Veg"} ) -op\_pmos1.addConstraint(\textcolor{stringliteral}{"Vd"} , \textcolor{stringliteral}{"design"}, \textcolor{stringliteral}{"Vdd"}, 0.5) -op\_pmos1.addConstraint(\textcolor{stringliteral}{"Vs"} , \textcolor{stringliteral}{"design"}, \textcolor{stringliteral}{"Vdd"} ) -op\_nmos1 = sizing.addOperator(\textcolor{stringliteral}{"nmos1"}, \textcolor{stringliteral}{"OPW(Vg,Vs)"}, \textcolor{stringliteral}{"BSIM3V3"}) -op\_nmos1.addConstraint(\textcolor{stringliteral}{"Temp"}, \textcolor{stringliteral}{"design"}, \textcolor{stringliteral}{"temp"}) -op\_nmos1.addConstraint(\textcolor{stringliteral}{"Ids"} , \textcolor{stringliteral}{"design"}, \textcolor{stringliteral}{"Ids"} ) -op\_nmos1.addConstraint(\textcolor{stringliteral}{"L"} , \textcolor{stringliteral}{"design"}, \textcolor{stringliteral}{"L"} ) -op\_nmos1.addConstraint(\textcolor{stringliteral}{"Vs"} , \textcolor{stringliteral}{"design"}, \textcolor{stringliteral}{"Vdd"} ) -op\_nmos1.addConstraint(\textcolor{stringliteral}{"Vg"} , \textcolor{stringliteral}{"pmos1"} , \textcolor{stringliteral}{"Vg"} ) -op\_nmos1.addConstraint(\textcolor{stringliteral}{"Vd"} , \textcolor{stringliteral}{"pmos1"} , \textcolor{stringliteral}{"Vd"} ) -op\_nmos1.addConstraint(\textcolor{stringliteral}{"another"}, \textcolor{stringliteral}{"myEq"}, -2.5 ) -\textcolor{comment}{# layout} -layout = circuit.createLayout() -layout.addInstance(\textcolor{stringliteral}{"pmos1"}, \textcolor{stringliteral}{"Common transistor"}) -layout.addInstance(\textcolor{stringliteral}{"nmos1"}, \textcolor{stringliteral}{"Rotate transistor"}) -\textcolor{comment}{# create hbtree} -g1 = Group(\textcolor{stringliteral}{"g1"}) -g1.align = Group.Align.VERTICAL -b1 = Bloc(\textcolor{stringliteral}{"nmos1"}, Node.Position.NONE, g1) -g1.rootNode = b1 -b2 = Bloc(\textcolor{stringliteral}{"pmos1"}, Node.Position.TOP, b1) -b1.top = b2 -layout.hbTreeRoot = g1 - -circuit.writeToFile(\textcolor{stringliteral}{"./myInverter.xml"}) \end{DoxyCodeInclude} diff --git a/vlsisapd/doc/latex/refman.tex b/vlsisapd/doc/latex/refman.tex index 96d2f5ee..0cc535cd 100644 --- a/vlsisapd/doc/latex/refman.tex +++ b/vlsisapd/doc/latex/refman.tex @@ -166,65 +166,53 @@ \input{spice} \chapter{Data Structure Documentation} \input{class_d_t_r_1_1_a_rule} -\input{class_open_chams_1_1_bloc} +\input{class_bloc} \input{class_s_p_i_c_e_1_1_capacitor} \input{class_c_i_f_1_1_circuit} -\input{class_open_chams_1_1_circuit} \input{class_s_p_i_c_e_1_1_circuit} -\input{class_open_chams_1_1_net_1_1_connection} -\input{class_open_chams_1_1_operator_1_1_constraint} +\input{class_circuit} +\input{class_net_1_1_connection} +\input{class_operator_1_1_constraint} \input{class_s_p_i_c_e_1_1_current} -\input{class_open_chams_1_1_d_d_p} -\input{class_open_chams_1_1_designer_cstr_o_c} -\input{class_open_chams_1_1_device} -\input{class_open_chams_1_1_d_slicing_node} +\input{class_device} \input{class_d_t_r_1_1_d_t_r_exception} \input{class_a_g_d_s_1_1_element} -\input{class_open_chams_1_1_equation} -\input{class_open_chams_1_1_group} -\input{class_open_chams_1_1_high_level_cstr} -\input{class_open_chams_1_1_h_slicing_node} -\input{class_open_chams_1_1_h_v_slicing_node} -\input{class_open_chams_1_1_schematic_1_1_infos} -\input{class_open_chams_1_1_instance} +\input{class_group} +\input{class_schematic_1_1_infos} \input{class_s_p_i_c_e_1_1_instance} -\input{class_open_chams_1_1_instance_point} -\input{class_open_chams_1_1_intermediate_point} -\input{class_open_chams_1_1_layout} +\input{class_instance} +\input{class_instance_point} +\input{class_intermediate_point} +\input{class_layout} \input{class_a_g_d_s_1_1_library} -\input{struct_open_chams_1_1map__item} \input{struct_s_p_i_c_e_1_1map__item} \input{class_s_p_i_c_e_1_1_mosfet} \input{class_name} -\input{class_open_chams_1_1_net} -\input{class_open_chams_1_1_netlist} -\input{class_open_chams_1_1_node} -\input{class_open_chams_1_1_n_r_c_cstr} -\input{class_open_chams_1_1_open_chams_exception} -\input{class_open_chams_1_1_operator} -\input{class_open_chams_1_1_parameters} +\input{class_net} +\input{class_netlist} +\input{class_node} +\input{class_open_chams_exception} +\input{class_operator} +\input{class_parameters} \input{class_c_i_f_1_1_polygon} -\input{class_open_chams_1_1_port} -\input{class_open_chams_1_1_port_point} +\input{class_port} +\input{class_port_point} \input{class_a_g_d_s_1_1_rectangle} \input{class_s_p_i_c_e_1_1_resistor} -\input{class_open_chams_1_1_r_slicing_node} \input{class_d_t_r_1_1_rule} -\input{class_open_chams_1_1_schematic} -\input{class_open_chams_1_1_simul_model} -\input{class_open_chams_1_1_sizing} -\input{class_open_chams_1_1_slicing_node} +\input{class_schematic} +\input{class_simul_model} +\input{class_sizing} \input{class_s_p_i_c_e_1_1_source} \input{class_s_p_i_c_e_1_1_spice_exception} \input{class_a_g_d_s_1_1_structure} \input{class_s_p_i_c_e_1_1_subckt} \input{class_d_t_r_1_1_techno} -\input{class_open_chams_1_1_transistor} +\input{class_transistor} \input{class_s_p_i_c_e_1_1_value} \input{class_s_p_i_c_e_1_1_voltage} -\input{class_open_chams_1_1_v_slicing_node} -\input{class_open_chams_1_1_wire} -\input{class_open_chams_1_1_wire_point} +\input{class_wire} +\input{class_wire_point} %--- End generated contents --- % Index diff --git a/vlsisapd/doc/latex/spice.tex b/vlsisapd/doc/latex/spice.tex index ed9bd045..a7e48e05 100644 --- a/vlsisapd/doc/latex/spice.tex +++ b/vlsisapd/doc/latex/spice.tex @@ -15,7 +15,7 @@ The database consists in several objects\+: \item \mbox{\hyperlink{class_s_p_i_c_e_1_1_voltage}{S\+P\+I\+C\+E\+::\+Voltage}} \item \mbox{\hyperlink{class_s_p_i_c_e_1_1_current}{S\+P\+I\+C\+E\+::\+Current}} \end{DoxyItemize}\hypertarget{spice_spiceParser}{}\subsection{Using the parser}\label{spice_spiceParser} -Simply load an Spice netlist file using the static function S\+P\+I\+C\+E\+::\+Circuit\+::read\+From\+File().\hypertarget{spice_spiceDriver}{}\subsection{Using the driver}\label{spice_spiceDriver} +Simply load an Spice netlist file using the static function \mbox{\hyperlink{class_s_p_i_c_e_1_1_circuit_aa8294fe7d9ceddb5653d08ecae3eaf36}{S\+P\+I\+C\+E\+::\+Circuit\+::read\+From\+File()}}.\hypertarget{spice_spiceDriver}{}\subsection{Using the driver}\label{spice_spiceDriver} Using the driver is very simple, user has to create a \mbox{\hyperlink{class_s_p_i_c_e_1_1_circuit}{S\+P\+I\+C\+E\+::\+Circuit}} object and simply add others Spice objects like \mbox{\hyperlink{class_s_p_i_c_e_1_1_subckt}{S\+P\+I\+C\+E\+::\+Subckt}} or \mbox{\hyperlink{class_s_p_i_c_e_1_1_instance}{S\+P\+I\+C\+E\+::\+Instance}} to it. Includes, libraries and parameters can also be added to \mbox{\hyperlink{class_s_p_i_c_e_1_1_circuit}{S\+P\+I\+C\+E\+::\+Circuit}}. Finally use the S\+P\+I\+C\+E\+::\+Circuit\+::write\+To\+File() method to dump the database to file.\hypertarget{spice_spiceExamples}{}\section{Examples}\label{spice_spiceExamples} As said is the global presentation, V\+L\+SI S\+A\+PD project provides C++ libraries and Python modules for each supported format. In this section we present simple code examples to parse and drive a S\+P\+I\+CE file using C++ or Python. The S\+P\+I\+CE file considered describes a simple Miller O\+TA\+: {\ttfamily O\+T\+A\+\_\+miller.\+spi} \begin{DoxyCodeInclude} @@ -77,7 +77,7 @@ The following code ({\ttfamily parse\+Spice.\+cpp}) is an example of how to pars \mbox{\hyperlink{class_s_p_i_c_e_1_1_circuit}{SPICE::Circuit}}* circuit = NULL; \textcolor{keywordflow}{try} \{ - circuit = SPICE::Circuit::readFromFile(file); + circuit = \mbox{\hyperlink{class_s_p_i_c_e_1_1_circuit_aa8294fe7d9ceddb5653d08ecae3eaf36}{SPICE::Circuit::readFromFile}}(file); \} \textcolor{keywordflow}{catch} (\mbox{\hyperlink{class_s_p_i_c_e_1_1_spice_exception}{SPICE::SpiceException}}& e) \{ cerr << e.what() << endl; exit(48); @@ -509,7 +509,7 @@ This python script ({\ttfamily drive\+Spice.\+py}) generates an my\+O\+T\+A.\+sp \begin{DoxyCodeInclude} \textcolor{keyword}{from} SPICE \textcolor{keyword}{import} * -circuit = Circuit() +circuit = \mbox{\hyperlink{class_circuit}{Circuit}}() circuit.title = \textcolor{stringliteral}{'* Single-ended two-stage amplifier'} @@ -577,7 +577,7 @@ dpN2.addParameter(\textcolor{stringliteral}{"tempsimu"}, \textcolor{stringlitera DP.addInstance(dpN2); \textcolor{comment}{# INSTANCES} -iCM = Instance(\textcolor{stringliteral}{"CM"}, \textcolor{stringliteral}{"currentMirrorPMOS"}); +iCM = \mbox{\hyperlink{class_instance}{Instance}}(\textcolor{stringliteral}{"CM"}, \textcolor{stringliteral}{"currentMirrorPMOS"}); iCM.addConnector(\textcolor{stringliteral}{"1"}); iCM.addConnector(\textcolor{stringliteral}{"2"}); iCM.addConnector(\textcolor{stringliteral}{"vdd"}); @@ -587,7 +587,7 @@ iCM.addParameter(\textcolor{stringliteral}{"w\_val"} , \textcolor{stringliteral} iCM.addParameter(\textcolor{stringliteral}{"nf\_val"}, \textcolor{stringliteral}{"2"} ); circuit.addInstance(iCM); -iDP = Instance(\textcolor{stringliteral}{"DP"}, \textcolor{stringliteral}{"diffPairNMOS"}); +iDP = \mbox{\hyperlink{class_instance}{Instance}}(\textcolor{stringliteral}{"DP"}, \textcolor{stringliteral}{"diffPairNMOS"}); iDP.addConnector(\textcolor{stringliteral}{"1"}); iDP.addConnector(\textcolor{stringliteral}{"2"}); iDP.addConnector(\textcolor{stringliteral}{"vim"});