riscv
/
coriolis
mirror of https://gitlab.lip6.fr/vlsi-eda/coriolis.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Add DesignFlow to the doc generation. New snapshot of the doc.

This commit is contained in:
Jean-Paul Chaput 2023-01-07 13:01:23 +01:00
parent 30afe6036b
commit 0bc7b3203a
20 changed files with 68 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
documentation/build.py
View File

@ -348,6 +348,7 @@ if __name__ == '__main__':
documents = [ Document( conf, 'content/pages/users-guide/UsersGuide' )
, Document( conf, 'content/pages/python-tutorial/PythonTutorial' )
, Document( conf, 'content/pages/python-cpp/PythonCpp' )
, Document( conf, 'content/pages/design-flow/DesignFlow' )
, Document( conf, 'content/pages/stratus/Stratus' )
, Document( conf, 'content/pages/check-toolkit/CheckToolkit' )
, Document( conf, 'content/pages/rds/RDS' )

BIN
documentation/content/pdfs/CheckToolkit.pdf
View File

Binary file not shown.

BIN
documentation/content/pdfs/DesignFlow.pdf
View File

Binary file not shown.

BIN
documentation/content/pdfs/PythonCpp.pdf
View File

Binary file not shown.

BIN
documentation/content/pdfs/PythonTutorial.pdf
View File

Binary file not shown.

BIN
documentation/content/pdfs/RDS.pdf
View File

Binary file not shown.

BIN
documentation/content/pdfs/Stratus.pdf
View File

Binary file not shown.

BIN
documentation/content/pdfs/UsersGuide.pdf
View File

Binary file not shown.

0
documentation/examples/scripts/coriolis2/__init__.py Normal file
View File

54
documentation/output/pages/.html
View File

@ -118,7 +118,7 @@
<h2>1. Introduction</h2>
<p>The goal of the DesignFlow Python tool is to provide a replacement for
Makefiles, especially the complex system that has been developped for
alliance-check-toolkit. It is build upon <a href="#id1"><span class="problematic" id="id2">|DoIt|</span></a> (<a href="#id91"><span class="problematic" id="id92">DoIt_</span></a>).</p>
alliance-check-toolkit. It is build upon <a href="#id1"><span class="problematic" id="id2">|DoIt|</span></a> (<a href="#id111"><span class="problematic" id="id112">DoIt_</span></a>).</p>
<div class="section" id="task-vs-rules">
<h3>1.1 Task vs. Rules</h3>
<p>Both as a tribute to <a href="#id3"><span class="problematic" id="id4">|Makefile|</span></a>, to avoid ambiguties with <a href="#id5"><span class="problematic" id="id6">|DoIt|</span></a> and to remember
@ -373,10 +373,22 @@ ego&#64;home:sky130_c4m&gt; ../../../bin/crlenv.py -- doit clean_flow --extras
</div>
<div class="section" id="rule-sets">
<h3>3.4 Rule Sets</h3>
<ol class="arabic simple">
<li>alliancesynth</li>
<li>pnrcheck</li>
<li>routecheck</li>
<p>For commonly used sequences of rules, some predefined sets are defined.</p>
<ol class="arabic">
<li><p class="first"><tt class="docutils literal">alliancesynth</tt>, to apply the logical <a href="#id91"><span class="problematic" id="id92">|Alliance|</span></a> logical synthesis
set of tools. From <a href="#id93"><span class="problematic" id="id94">|VHDL|</span></a> to optimized <a href="#id95"><span class="problematic" id="id96">|vst|</span></a>. The set is as follow:</p>
<pre class="literal-block">
x.vbe =&gt; boom =&gt; x_boom.vbe =&gt; boog =&gt; x_boog.vst =&gt; loon =&gt; x.vst
</pre>
<p>An additional rule using <tt class="docutils literal">vasy</tt> is triggered if the input format
is standard <a href="#id97"><span class="problematic" id="id98">|VHDL|</span></a>.</p>
</li>
<li><p class="first"><tt class="docutils literal">pnrcheck</tt>, complete flow from <a href="#id99"><span class="problematic" id="id100">|Verilog|</span></a> to symbolic layout, with
<a href="#id101"><span class="problematic" id="id102">|DRC|</span></a> and <a href="#id103"><span class="problematic" id="id104">|LVX|</span></a> checks. Uses <a href="#id105"><span class="problematic" id="id106">|Yosys|</span></a> for synthesis.</p>
</li>
<li><p class="first"><tt class="docutils literal">routecheck</tt>, perform the routing, the <a href="#id107"><span class="problematic" id="id108">|DRC|</span></a> and <a href="#id109"><span class="problematic" id="id110">|LVX|</span></a> check on an
already placed design. Use symbolic layout.</p>
</li>
</ol>
</div>
</div>
@ -518,7 +530,37 @@ Undefined substitution referenced: &quot;Coriolis&quot;.</div>
<p class="system-message-title">System Message: ERROR/3 (<tt class="docutils">/dsk/l1/jpc/coriolis-2.x/src/coriolis/documentation/content/pages/design-flow/QuickStart.rst</tt>, line 272); <em><a href="#id90">backlink</a></em></p>
Undefined substitution referenced: &quot;Yosys&quot;.</div>
<div class="system-message" id="id91">
<p class="system-message-title">System Message: ERROR/3 (<tt class="docutils">/dsk/l1/jpc/coriolis-2.x/src/coriolis/documentation/content/pages/design-flow/QuickStart.rst</tt>, line 7); <em><a href="#id92">backlink</a></em></p>
<p class="system-message-title">System Message: ERROR/3 (<tt class="docutils">/dsk/l1/jpc/coriolis-2.x/src/coriolis/documentation/content/pages/design-flow/QuickStart.rst</tt>, line 299); <em><a href="#id92">backlink</a></em></p>
Undefined substitution referenced: &quot;Alliance&quot;.</div>
<div class="system-message" id="id93">
<p class="system-message-title">System Message: ERROR/3 (<tt class="docutils">/dsk/l1/jpc/coriolis-2.x/src/coriolis/documentation/content/pages/design-flow/QuickStart.rst</tt>, line 299); <em><a href="#id94">backlink</a></em></p>
Undefined substitution referenced: &quot;VHDL&quot;.</div>
<div class="system-message" id="id95">
<p class="system-message-title">System Message: ERROR/3 (<tt class="docutils">/dsk/l1/jpc/coriolis-2.x/src/coriolis/documentation/content/pages/design-flow/QuickStart.rst</tt>, line 299); <em><a href="#id96">backlink</a></em></p>
Undefined substitution referenced: &quot;vst&quot;.</div>
<div class="system-message" id="id97">
<p class="system-message-title">System Message: ERROR/3 (<tt class="docutils">/dsk/l1/jpc/coriolis-2.x/src/coriolis/documentation/content/pages/design-flow/QuickStart.rst</tt>, line 304); <em><a href="#id98">backlink</a></em></p>
Undefined substitution referenced: &quot;VHDL&quot;.</div>
<div class="system-message" id="id99">
<p class="system-message-title">System Message: ERROR/3 (<tt class="docutils">/dsk/l1/jpc/coriolis-2.x/src/coriolis/documentation/content/pages/design-flow/QuickStart.rst</tt>, line 307); <em><a href="#id100">backlink</a></em></p>
Undefined substitution referenced: &quot;Verilog&quot;.</div>
<div class="system-message" id="id101">
<p class="system-message-title">System Message: ERROR/3 (<tt class="docutils">/dsk/l1/jpc/coriolis-2.x/src/coriolis/documentation/content/pages/design-flow/QuickStart.rst</tt>, line 307); <em><a href="#id102">backlink</a></em></p>
Undefined substitution referenced: &quot;DRC&quot;.</div>
<div class="system-message" id="id103">
<p class="system-message-title">System Message: ERROR/3 (<tt class="docutils">/dsk/l1/jpc/coriolis-2.x/src/coriolis/documentation/content/pages/design-flow/QuickStart.rst</tt>, line 307); <em><a href="#id104">backlink</a></em></p>
Undefined substitution referenced: &quot;LVX&quot;.</div>
<div class="system-message" id="id105">
<p class="system-message-title">System Message: ERROR/3 (<tt class="docutils">/dsk/l1/jpc/coriolis-2.x/src/coriolis/documentation/content/pages/design-flow/QuickStart.rst</tt>, line 307); <em><a href="#id106">backlink</a></em></p>
Undefined substitution referenced: &quot;Yosys&quot;.</div>
<div class="system-message" id="id107">
<p class="system-message-title">System Message: ERROR/3 (<tt class="docutils">/dsk/l1/jpc/coriolis-2.x/src/coriolis/documentation/content/pages/design-flow/QuickStart.rst</tt>, line 310); <em><a href="#id108">backlink</a></em></p>
Undefined substitution referenced: &quot;DRC&quot;.</div>
<div class="system-message" id="id109">
<p class="system-message-title">System Message: ERROR/3 (<tt class="docutils">/dsk/l1/jpc/coriolis-2.x/src/coriolis/documentation/content/pages/design-flow/QuickStart.rst</tt>, line 310); <em><a href="#id110">backlink</a></em></p>
Undefined substitution referenced: &quot;LVX&quot;.</div>
<div class="system-message" id="id111">
<p class="system-message-title">System Message: ERROR/3 (<tt class="docutils">/dsk/l1/jpc/coriolis-2.x/src/coriolis/documentation/content/pages/design-flow/QuickStart.rst</tt>, line 7); <em><a href="#id112">backlink</a></em></p>
Unknown target name: &quot;doit&quot;.</div>
</div>

22
documentation/output/pages/design-flow.html
View File

@ -368,7 +368,7 @@ cell library (works with <tt class="docutils literal">boom</tt> &amp; <tt class=
<li><tt class="docutils literal">Boom</tt>, behavioral description optimizer (works with <tt class="docutils literal">boog</tt> &amp; <tt class="docutils literal">loon</tt>).</li>
<li><tt class="docutils literal">Cougar</tt>, symbolic layout extractor.</li>
<li><tt class="docutils literal">Dreal</tt>, real layout (<span class="sc">gds</span>, <span class="sc">cif</span>) editor.</li>
<li><tt class="docutils literal">Druc</tt>, symbolic layout <span class="sc">DRC</span>.</li>
<li><tt class="docutils literal">Druc</tt>, symbolic layout <span class="sc">drc</span>.</li>
<li><tt class="docutils literal">Flatph</tt>, flatten a layout, fully or in part.</li>
<li><tt class="docutils literal">Genpat</tt>, pattern generator (for use with <tt class="docutils literal">Asimut</tt>).</li>
<li><tt class="docutils literal">Graal</tt>, symbolic layout editor.</li>
@ -409,10 +409,22 @@ ego&#64;home:sky130_c4m&gt; ../../../bin/crlenv.py -- doit clean_flow --extras
</div>
<div class="section" id="rule-sets">
<h3><a class="toc-backref" href="#id13">3.4 Rule Sets</a></h3>
<ol class="arabic simple">
<li>alliancesynth</li>
<li>pnrcheck</li>
<li>routecheck</li>
<p>For commonly used sequences of rules, some predefined sets are defined.</p>
<ol class="arabic">
<li><p class="first"><tt class="docutils literal">alliancesynth</tt>, to apply the logical <span class="sc">Alliance</span> logical synthesis
set of tools. From <span class="sc">vhdl</span> to optimized <span class="cb">vst</span>. The set is as follow:</p>
<pre class="literal-block">
x.vbe =&gt; boom =&gt; x_boom.vbe =&gt; boog =&gt; x_boog.vst =&gt; loon =&gt; x.vst
</pre>
<p>An additional rule using <tt class="docutils literal">vasy</tt> is triggered if the input format
is standard <span class="sc">vhdl</span>.</p>
</li>
<li><p class="first"><tt class="docutils literal">pnrcheck</tt>, complete flow from <span class="sc">Verilog</span> to symbolic layout, with
<span class="sc">drc</span> and <span class="sc">lvx</span> checks. Uses <span class="sc">Yosys</span> for synthesis.</p>
</li>
<li><p class="first"><tt class="docutils literal">routecheck</tt>, perform the routing, the <span class="sc">drc</span> and <span class="sc">lvx</span> check on an
already placed design. Use symbolic layout.</p>
</li>
</ol>
</div>
</div>

BIN
documentation/output/pdfs/CheckToolkit.pdf
View File

Binary file not shown.

BIN
documentation/output/pdfs/DesignFlow.pdf
View File

Binary file not shown.

BIN
documentation/output/pdfs/PythonCpp.pdf
View File

Binary file not shown.

BIN
documentation/output/pdfs/PythonTutorial.pdf
View File

Binary file not shown.

BIN
documentation/output/pdfs/RDS.pdf
View File

Binary file not shown.

BIN
documentation/output/pdfs/Stratus.pdf
View File

Binary file not shown.

BIN
documentation/output/pdfs/UsersGuide.pdf
View File

Binary file not shown.

2
documentation/output/theme/css/nest.css
View File

@ -86,7 +86,7 @@ a.more{
pre, code {
background: #f8f7fa;
padding: 10px;
font-size: 16px;
font-size: 14px;
line-height: 24px;
font-family: Consolas, monaco, monospace;
border-radius: 0px;

2
documentation/themes/nest-coriolis/static/css/nest.css
View File

@ -86,7 +86,7 @@ a.more{
pre, code {
background: #f8f7fa;
padding: 10px;
font-size: 16px;
font-size: 14px;
line-height: 24px;
font-family: Consolas, monaco, monospace;
border-radius: 0px;