In CRL::VstDriver, name-mangle file names too with option UniquifyUpperCase.
* Bug: In CRL::vstDriver(), when upper case names are uniquified, including components, the associated model filename must also be mangled.
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03a52977d3
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0640586cbc
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@ -39,11 +39,15 @@ namespace CRL {
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void vstDriver ( const string cellPath, Cell *cell, unsigned int& saveState )
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void vstDriver ( const string cellPath, Cell *cell, unsigned int& saveState )
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{
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{
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NamingScheme ns (NamingScheme::FromVerilog);
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unsigned int entityFlags = Vhdl::Entity::EntityMode /* | Vhdl::Entity::IeeeMode */;
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unsigned int entityFlags = Vhdl::Entity::EntityMode /* | Vhdl::Entity::IeeeMode */;
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if (saveState & Catalog::State::VstUseConcat ) entityFlags |= Vhdl::Entity::VstUseConcat;
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if (saveState & Catalog::State::VstUseConcat ) entityFlags |= Vhdl::Entity::VstUseConcat;
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if (saveState & Catalog::State::VstNoLowerCase ) entityFlags |= Vhdl::Entity::VstNoLowerCase;
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if (saveState & Catalog::State::VstNoLowerCase ) entityFlags |= Vhdl::Entity::VstNoLowerCase;
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if (saveState & Catalog::State::VstUniquifyUpperCase) entityFlags |= Vhdl::Entity::VstUniquifyUpperCase;
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if (saveState & Catalog::State::VstNoLinkage ) entityFlags |= Vhdl::Entity::VstNoLinkage;
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if (saveState & Catalog::State::VstNoLinkage ) entityFlags |= Vhdl::Entity::VstNoLinkage;
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if (saveState & Catalog::State::VstUniquifyUpperCase) {
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entityFlags |= Vhdl::Entity::VstUniquifyUpperCase;
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ns.setUniquifyUpperCase( true );
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}
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//NamingScheme::toVhdl( cell, NamingScheme::FromVerilog );
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//NamingScheme::toVhdl( cell, NamingScheme::FromVerilog );
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Vhdl::Entity* vhdlEntity = Vhdl::EntityExtension::create( cell, entityFlags );
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Vhdl::Entity* vhdlEntity = Vhdl::EntityExtension::create( cell, entityFlags );
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@ -61,7 +65,6 @@ namespace CRL {
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} else {
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} else {
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file = cellPath;
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file = cellPath;
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}
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}
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NamingScheme ns (NamingScheme::FromVerilog);
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file = getString( ns.convert(file) );
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file = getString( ns.convert(file) );
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celltest = path + '/' + file + '.' + ext;
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celltest = path + '/' + file + '.' + ext;
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