coriolis/crlcore/etc/vsc200/technology.conf

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# -*- Mode:Python; explicit-buffer-name: "technology.conf<vsc200>" -*-
import helpers
# The informations here are extracted from the Alliance ".rds" file,
ExtensionCap support and source/target terminal flags in Katabatic & Kite. Placement management: * Change: In <metis>, always disable the hMetis support regardless of it being detected or not as the placer is still unable manage the final bin contents. Routing gauge management: * Bug: In CRL Core, <vsclib/alliance.conf>, set the correct pitches and size for the routing layers and the cell gauge. * Change: In Katabatic & Kite, extract the correct extension cap for each routing layer from the layers characteristics (cache then in Katabatic::Configuration). * Change: In Katabatic, <AutoSegment>, create segment with the wire width defined in the gauge. For AutoSegment created on already existing Segment from the global routing, adjust the width. * Change: In Katabatic, <AutoSegment>, more accurate information about how a segment is connected to terminal via source and/or target. The flag SegStrongTerminal is splitted into SegSourceTerminal and SegSourceTarget (but still used as a mask). So now we can know by which end an AutoSegment is connected to a terminal. * Change: In Katabatic, ::doRp_Access(), create constraint freeing segments not only when HSmall but also when VSmall (more critical for <vsclib>). Otherwise we may see AutoSegments with incompatible source/target constraints. * Change: In Kite, BuildPowerRails, do not create blockage on PinOnly layers *but* still create power rails planes. This is a temporary workaround for <vsclib> where the METAL1 blockages overlaps the terminals (it was fine for Nero, but they shouldn't for Kite). * Change: In Kite, <RoutingEvent>, if a TrackSegment is overconstrained, directly bybass it's slackening state to DataNegociate::Slacken. Also rename the flag "_canHandleConstraints" to "_overConstrained", seems clearer to me. Miscellaneous: * Change: In CRL Core, <Utilities>, add a "pass-though" capability on the mstream to temporarily make them print everything.
2014-05-25 08:00:35 -05:00
# and must be consistent with it.
#
# Provides standard settings for:
# - <viewerConfig>
# - <realLayersTable>
# - <symbolicLayersTable>
# - <workingLayersTable>
execfile( helpers.sysConfDir+'/common/technology.conf' )
# Format of <symbolicRulesTable>:
# Each entry is a pair of (string, value).
# * string: a synthetic way to designate the symbolic layer on which
# it applies, an optional real layer in case where there is
# more than one, and the dimension name.
# * value : the rule (dimension) value expressed in lambda.
symbolicRulesTable = \
( ('NWELL.nWell.extention.cap' , 4.0)
, ('PWELL.pWell.extention.cap' , 4.0)
, ('NTIE.minimum.width' , 3.0)
, ('NTIE.nWell.extention.cap' , 3.0)
, ('NTIE.nWell.extention.width' , 1.0)
, ('NTIE.nImplant.extention.cap' , 3.0)
, ('NTIE.nImplant.extention.width' , 1.0)
, ('NTIE.active.extention.cap' , 2.0)
, ('NTIE.active.extention.width' , 0.0)
, ('PTIE.minimum.width' , 3.0)
, ('PTIE.pWell.extention.cap' , 3.0)
, ('PTIE.pWell.extention.width' , 1.0)
, ('PTIE.pImplant.extention.cap' , 1.0)
, ('PTIE.pImplant.extention.width' , 1.0)
, ('PTIE.active.extention.cap' , 2.0)
, ('PTIE.active.extention.width' , 0.0)
, ('NDIF.minimum.width' , 3.0)
, ('NDIF.nImplant.extention.cap' , 5.0)
, ('NDIF.nImplant.extention.width' , 3.0)
, ('NDIF.active.extention.cap' , 2.0)
, ('NDIF.active.extention.width' , 0.0)
, ('PDIF.minimum.width' , 3.0)
, ('PDIF.pImplant.extention.cap' , 5.0)
, ('PDIF.pImplant.extention.width' , 3.0)
, ('PDIF.active.extention.cap' , 2.0)
, ('PDIF.active.extention.width' , 0.0)
, ('GATE.minimum.width' , 1.0)
, ('GATE.poly.extention.cap' , 1.5)
, ('NTRANS.minimum.width' , 2.0)
, ('NTRANS.nImplant.extention.cap' , 3.0)
, ('NTRANS.nImplant.extention.width' , 8.0)
, ('NTRANS.active.extention.cap' , 0.0)
, ('NTRANS.active.extention.width' , 5.0)
, ('NTRANS.poly.extention.cap' , 4.0)
, ('NTRANS.poly.extention.width' , 0.0)
, ('PTRANS.minimum.width' , 1.0)
, ('PTRANS.nWell.extention.cap' , 3.0)
, ('PTRANS.nWell.extention.width' , 8.0)
, ('PTRANS.pImplant.extention.cap' , 3.0)
, ('PTRANS.pImplant.extention.width' , 8.0)
, ('PTRANS.active.extention.cap' , 0.0)
, ('PTRANS.active.extention.width' , 5.0)
, ('PTRANS.poly.extention.cap' , 4.0)
, ('PTRANS.poly.extention.width' , 0.0)
, ('POLY.minimum.width' , 2.0)
, ('POLY.poly.extention.cap' , 1.0)
, ('POLY2.minimum.width' , 2.0)
, ('POLY2.poly2.extention.cap' , 2.0)
# Routing Layers.
, ('METAL1.minimum.width' , 1.0)
, ('METAL1.metal1.extention.cap' , 2.0)
, ('METAL2.minimum.width' , 1.0)
, ('METAL2.metal2.extention.cap' , 2.0)
, ('METAL3.minimum.width' , 1.0)
, ('METAL3.metal3.extention.cap' , 2.0)
, ('METAL4.minimum.width' , 1.0)
, ('METAL4.metal4.extention.cap' , 2.0)
, ('METAL5.minimum.width' , 2.0)
, ('METAL5.metal5.extention.cap' , 2.0)
, ('METAL6.minimum.width' , 2.0)
, ('METAL6.metal6.extention.cap' , 4.0)
, ('METAL7.minimum.width' , 2.0)
, ('METAL7.metal6.extention.cap' , 4.0)
, ('METAL8.minimum.width' , 2.0)
, ('METAL8.metal6.extention.cap' , 4.0)
# Contacts (i.e. Active <--> Metal).
, ('CONT_BODY_N.minimum.side' , 2.0)
, ('CONT_BODY_N.nWell.enclosure' , 3.0)
, ('CONT_BODY_N.nImplant.enclosure' , 3.0)
, ('CONT_BODY_N.active.enclosure' , 2.0)
, ('CONT_BODY_N.metal1.enclosure' , 1.0)
, ('CONT_BODY_P.minimum.side' , 2.0)
, ('CONT_BODY_P.pWell.enclosure' , 3.0)
, ('CONT_BODY_P.pImplant.enclosure' , 3.0)
, ('CONT_BODY_P.active.enclosure' , 2.0)
, ('CONT_BODY_P.metal1.enclosure' , 1.0)
, ('CONT_DIF_N.minimum.side' , 2.0)
, ('CONT_DIF_N.nImplant.enclosure' , 2.0)
, ('CONT_DIF_N.active.enclosure' , 2.0)
, ('CONT_DIF_N.metal1.enclosure' , 1.0)
, ('CONT_DIF_P.minimum.side' , 2.0)
, ('CONT_DIF_P.pImplant.enclosure' , 2.0)
, ('CONT_DIF_P.active.enclosure' , 2.0)
, ('CONT_DIF_P.metal1.enclosure' , 1.0)
, ('CONT_POLY.minimum.width' , 2.0)
, ('CONT_POLY.poly.enclosure' , 2.0)
, ('CONT_POLY.metal1.enclosure' , 1.0)
# VIAs (i.e. Metal <--> Metal).
, ('VIA12.minimum.side' , 2.0)
, ('VIA12.metal1.enclosure' , 1.0)
, ('VIA12.metal2.enclosure' , 1.0)
, ('VIA23.minimum.side' , 2.0)
, ('VIA23.metal2.enclosure' , 1.0)
, ('VIA23.metal3.enclosure' , 1.0)
, ('VIA34.minimum.side' , 2.0)
, ('VIA34.metal3.enclosure' , 1.0)
, ('VIA34.metal4.enclosure' , 1.0)
, ('VIA45.minimum.side' , 2.0)
, ('VIA45.metal4.enclosure' , 1.0)
, ('VIA45.metal5.enclosure' , 1.0)
, ('VIA56.minimum.side' , 2.0)
, ('VIA56.metal5.enclosure' , 3.0)
, ('VIA56.metal6.enclosure' , 3.0)
, ('VIA67.minimum.side' , 2.0)
, ('VIA67.metal6.enclosure' , 3.0)
, ('VIA67.metal7.enclosure' , 3.0)
, ('VIA78.minimum.side' , 2.0)
, ('VIA78.metal7.enclosure' , 3.0)
, ('VIA78.metal8.enclosure' , 3.0)
# Blockages.
, ('BLOCKAGE1.minimum.width' , 1.0)
, ('BLOCKAGE1.blockage1.extention.cap' , 2.0)
, ('BLOCKAGE2.minimum.width' , 2.0)
, ('BLOCKAGE2.blockage2.extention.cap' , 2.0)
, ('BLOCKAGE3.minimum.width' , 2.0)
, ('BLOCKAGE3.blockage3.extention.cap' , 2.0)
, ('BLOCKAGE4.minimum.width' , 2.0)
, ('BLOCKAGE4.blockage4.extention.cap' , 2.0)
, ('BLOCKAGE5.minimum.width' , 2.0)
, ('BLOCKAGE5.blockage5.extention.cap' , 2.0)
, ('BLOCKAGE6.minimum.width' , 2.0)
, ('BLOCKAGE6.blockage6.extention.cap' , 4.0)
, ('BLOCKAGE7.minimum.width' , 2.0)
, ('BLOCKAGE7.blockage6.extention.cap' , 4.0)
, ('BLOCKAGE8.minimum.width' , 2.0)
, ('BLOCKAGE8.blockage6.extention.cap' , 4.0)
)