866 lines
29 KiB
Python
866 lines
29 KiB
Python
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#!/usr/bin/python
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# This file is part of the Coriolis Project.
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# Copyright (C) Laboratoire LIP6 - Departement ASIM
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# Universite Pierre et Marie Curie
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#
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# Main contributors :
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# Christophe Alexandre <Christophe.Alexandre@lip6.fr>
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# Sophie Belloeil <Sophie.Belloeil@lip6.fr>
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# Hugo Clement <Hugo.Clement@lip6.fr>
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# Jean-Paul Chaput <Jean-Paul.Chaput@lip6.fr>
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# Damien Dupuis <Damien.Dupuis@lip6.fr>
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# Christian Masson <Christian.Masson@lip6.fr>
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# Marek Sroka <Marek.Sroka@lip6.fr>
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#
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# The Coriolis Project is free software; you can redistribute it
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# and/or modify it under the terms of the GNU General Public License
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# as published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# The Coriolis Project is distributed in the hope that it will be
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# useful, but WITHOUT ANY WARRANTY; without even the implied warranty
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# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with the Coriolis Project; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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# USA
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#
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# License-Tag
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# Authors-Tag
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# ===================================================================
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#
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# x-----------------------------------------------------------------x
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# | |
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# | C O R I O L I S |
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# | S t r a t u s - Netlists/Layouts Description |
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# | |
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# | Author : Sophie BELLOEIL |
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# | E-mail : Sophie.Belloeil@asim.lip6.fr |
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# | =============================================================== |
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# | Py Module : "./dpgen_ROM.py" |
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# | *************************************************************** |
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# | U p d a t e s |
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# | |
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# x-----------------------------------------------------------------x
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from stratus import *
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# Le nombre de mots peut prendre cinq valeurs : 64, 128, 256, 512, 1024
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# Le nombre de bits est un multiple de 4 et doit etre inferieur ou egal a 64
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# On peut avoir une sortie tri-state en option (pour construire des ROMs
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# de capacite superieure a 1024 mots.
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# La largeur est egale a ( nmot / 64 * 50) + 150 (+ 20 si option tristate)
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# La hauteur est egale a ( nbit + 8) * 50 pour 64 ou 128 mots
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# ( nbit + 9) * 50 pour 256, 512 ou 1024 mots
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#
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# Les valeurs a encoder dans la ROM sont recuperees dans le tableau data[2048]
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# qui contient des "mots" de 32 bits : une valeur est stockee dans deux cases
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# consecutives de ce tableau, ce qui permet d'avoir des mots de 64 bits.
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# Les poids faibles de la valeur i sont a l'adresse data[2*i]
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# Les poids forts de la valeur i sont a l'adresse data[2*i+1]
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#
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# Les lignes de bit horizontales en ALU2 sont hors grilles et pre-routees
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# la ROM respecte le gabarit SXLIB pour ce qui concerne les caissons et les
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# alimentations en ALU1 sur les faces est et ouest, mais il n'y a pas
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# de continuite des alimentations en ALU1 dans la zone data.
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# Pour la partie "donnees", on utilise les cellules suivantes :
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# - rom_data_invss
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# - rom_data_insel
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# - rom_data_midvss
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# - rom_data_midsel
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# - rom_data_outvss
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# - rom_data_outsel
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# - rom_data_outvss_ts
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# - rom_data_outsel_ts
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#
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# Pour le decodeur, on utilise les cellules suivantes :
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# - rom_dec_adbuf
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# - rom_dec_nop
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# - rom_dec_prech
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# - rom_dec_col2
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# - rom_dec_col3
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# - rom_dec_col4
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# - rom_dec_colbuf
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# - rom_dec_line01
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# - rom_dec_line23
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# - rom_dec_line45
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# - rom_dec_line67
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# - rom_dec_selmux01
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# - rom_dec_selmux23
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# - rom_dec_selmux45
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# - rom_dec_selmux67
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# - rom_dec_selmux67_128
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# - rom_dec_selmux01_ts
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# - rom_dec_selmux23_ts
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# - rom_dec_selmux45_ts
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# - rom_dec_selmux67_ts
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# - rom_dec_selmux67_128_ts
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class dpgen_ROM ( Model ) :
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## Interface ##
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###############
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def Interface ( self, nbit, nword ) :
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if nword == 64 : adrange = 6
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elif nword == 128 : adrange = 7
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elif nword == 256 : adrange = 8
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elif nword == 512 : adrange = 9
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elif nword == 1024 : adrange = 10
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else :
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print "Error : DPGEN_ROM"
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print "The word number (nword := %d) ", nword, "can only takes values : 64, 128, 256, 512 or 1024.\n"
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sys.exit ( 3 )
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if nbit % 4 != 0 or nbit > 64 or nbit < 4 :
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print "Error : DPGEN_ROM\n"
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print "The bus width (nbit := %d) ", nbit, "must be multiple of 4 and no larger than 64.\n"
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sys.exit ( 3 )
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ck = LogicIn ( "ck", 1 )
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selrom = LogicIn ( "selrom", 1 )
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ad = LogicIn ( "ad", adrange )
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data = LogicOut ( "data", nbit )
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vdd = VddIn ( "vdd" )
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vss = VssIn ( "vss" )
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## Architecture ##
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##################
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def architecture ( self, nbit, nword ) :
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# // Acquisition du tableau des valeurs a encoder
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#
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# /* ICI IL FAUT APPELER LE PARSER DE FICHIER .vbe */
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# /*
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# for(i=0 ; i<1024 ; i++) {
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# data[2*i] = i;
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# data[2*i+1] = 1024 - i;
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# }
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# */
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#
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# dpgen_ROM_code ( LV_name, nbit, nword, 0, 0, data ) # !!!
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for i in range ( nbit ) :
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if i % 4 == 0 :
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cellin = "rom_data_invss"
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cellmid = "rom_data_midvss"
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cellout = "rom_data_outvss"
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elif i % 4 == 1 :
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cellin = "rom_data_insel"
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cellmid = "rom_data_midsel"
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cellout = "rom_data_outsel"
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elif i % 4 == 2:
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cellin = "rom_data_insel"
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cellmid = "rom_data_midsel"
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cellout = "rom_data_outsel"
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elif i % 4 == 3 :
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cellin = "rom_data_invss"
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cellmid = "rom_data_midvss"
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cellout = "rom_data_outvss"
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instanciate ( cellin
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, "in%d" % i
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, map = { 'prech' : prech
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, 'bit0' : bit0[i]
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, 'bit1' : bit1[i]
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, 'bit2' : bit2[i]
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, 'bit3' : bit3[i]
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, 'bit4' : bit4[i]
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, 'bit5' : bit5[i]
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, 'bit6' : bit6[i]
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, 'bit7' : bit7[i]
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}
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)
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for j in range ( 0, nword, 64 ) :
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instanciate ( cellmid
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, "bit%d_%d" % ( i, j )
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, map = { 'sela' : line0[j]
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, 'selb' : line2[j]
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, 'selc' : line4[j]
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, 'seld' : line6[j]
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, 'bit0' : bit0 [i]
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, 'bit1' : bit1 [i]
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, 'bit2' : bit2 [i]
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, 'bit3' : bit3 [i]
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, 'bit4' : bit4 [i]
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, 'bit5' : bit5 [i]
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, 'bit6' : bit6 [i]
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, 'bit7' : bit7 [i]
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}
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)
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instanciate ( cellmid
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, "bit%d_%d" % ( i, j + 32 )
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, map = { 'sela' : line1[j]
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, 'selb' : line3[j]
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, 'selc' : line5[j]
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, 'seld' : line7[j]
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, 'bit0' : bit0 [i]
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, 'bit1' : bit1 [i]
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, 'bit2' : bit2 [i]
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, 'bit3' : bit3 [i]
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, 'bit4' : bit4 [i]
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, 'bit5' : bit5 [i]
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, 'bit6' : bit6 [i]
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, 'bit7' : bit7 [i]
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}
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)
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instanciate ( cellout
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, "out%d" % i
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, map = { 'nprech' : nprech
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, 'mux0' : mux0
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, 'mux1' : mux1
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, 'mux2' : mux2
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, 'mux3' : mux3
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, 'mux4' : mux4
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, 'mux5' : mux5
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, 'mux6' : mux6
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, 'mux7' : mux7
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, 'bit0' : bit0[i]
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, 'bit1' : bit1[i]
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, 'bit2' : bit2[i]
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, 'bit3' : bit3[i]
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, 'bit4' : bit4[i]
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, 'bit5' : bit5[i]
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, 'bit6' : bit6[i]
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, 'bit7' : bit7[i]
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, 'q' : data[i]
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}
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)
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## Placement des cellules decodeur ##
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# Lignes 0 et 1
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instanciate ( "rom_dec_prech"
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, "prech"
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, map = { 'nck' : nck
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, 'prech' : prech
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, 'nprech' : nprech
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}
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)
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for j in range ( 0, nword, 64 ) :
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thisMap = { 'nck0' : nck
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, 'nck1' : nck
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, 'sel0' : sel0
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, 'sel1' : sel1
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, 'line0' : line0[j]
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, 'line1' : line1[j]
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}
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if nword != 64 : thisMap['col'] = col[j]
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else : thisMap['col'] = vdd
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instanciate ( "rom_dec_line01"
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, "and01_%d" % j
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, map = thisMap
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)
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instanciate ( "rom_dec_selmux01"
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, "selmux01"
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, map = { 'a0' : a0
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, 'na0' : na0
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, 'a1' : a1
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, 'na1' : na1
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, 'a2' : a2
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, 'na2' : na2
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, 'a3' : a3
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, 'na3' : na3
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, 'a4' : a4
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, 'na4' : na4
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, 'a5' : a5
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, 'na5' : na5
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, 'ck' : ck
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, 'selrom' : selrom
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, 'nck' : nck
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, 'mux0' : mux0
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, 'sel0' : sel0
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, 'mux1' : mux1
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, 'sel1' : sel1
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}
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)
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# Lignes 2 et 3
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instanciate ( "rom_dec_adbuf"
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, "ad4"
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, map = { 'ad' : ad[4]
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, 'adx' : a4
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, 'nadx' : na4
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}
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)
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instanciate ( "rom_dec_adbuf"
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, "ad5"
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, map = { 'ad' : ad[5]
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, 'adx' : a5
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, 'nadx' : na5
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}
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)
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for j in range ( 0, nword, 64 ) :
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thisMap = { 'nck2' : nck
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, 'nck3' : nck
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, 'sel2' : sel2
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, 'sel3' : sel3
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, 'line2' : line2[j]
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, 'line3' : line3[j]
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}
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if nword != 64 : thisMap['col'] = col[j]
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else : thisMap['col'] = vdd
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instanciate ( "rom_dec_line23"
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, "and23_%d" % j
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, map = thisMap
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)
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LV_name.PLACE_RIGHT ( "rom_dec_selmux23"
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, "selmux23"
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, map = { 'a0' : a0
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, 'na0' : na0
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, 'a1' : a1
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, 'na1' : na1
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, 'a2' : a2
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, 'na2' : na2
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, 'a3' : a3
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, 'na3' : na3
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, 'a4' : a4
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, 'na4' : na4
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, 'a5' : a5
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, 'na5' : na5
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, 'ck' : ck
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, 'selrom' : selrom
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, 'nck' : nck
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, 'mux2' : mux2
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, 'sel2' : sel2
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, 'mux3' : mux3
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, 'sel3' : sel3
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}
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)
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# Lignes 4 et 5
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instanciate ( "rom_dec_adbuf"
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, "ad2"
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, map = { 'ad' : ad[2]
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, 'adx' : a2
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, 'nadx' : na2
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}
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)
|
||
|
|
|
||
|
|
nstanciate ( "rom_dec_adbuf"
|
||
|
|
, "ad3"
|
||
|
|
, map = { 'ad' : ad[3]
|
||
|
|
, 'adx' : a3
|
||
|
|
, 'nadx' : na3
|
||
|
|
}
|
||
|
|
)
|
||
|
|
|
||
|
|
for j in range ( 0, nword, 64 ) :
|
||
|
|
thisMap = { 'nck4' : nck
|
||
|
|
, 'nck5' : nck
|
||
|
|
, 'sel4' : sel4
|
||
|
|
, 'sel5' : sel5
|
||
|
|
, 'line4' : line4[j]
|
||
|
|
, 'line5' : line5[j]
|
||
|
|
}
|
||
|
|
|
||
|
|
if nword != 64 : thisMap['col'] = col[j]
|
||
|
|
else : thisMap['col'] = vdd
|
||
|
|
|
||
|
|
instanciate ( "rom_dec_line45"
|
||
|
|
, "and45_%d" % j
|
||
|
|
, map = thisMap
|
||
|
|
)
|
||
|
|
|
||
|
|
instanciate ( "rom_dec_selmux45"
|
||
|
|
, "selmux45"
|
||
|
|
, map = { 'a0' : a0
|
||
|
|
, 'na0' : na0
|
||
|
|
, 'a1' : a1
|
||
|
|
, 'na1' : na1
|
||
|
|
, 'a2' : a2
|
||
|
|
, 'na2' : na2
|
||
|
|
, 'a3' : a3
|
||
|
|
, 'na3' : na3
|
||
|
|
, 'a4' : a4
|
||
|
|
, 'na4' : na4
|
||
|
|
, 'a5' : a5
|
||
|
|
, 'na5' : na5
|
||
|
|
, 'ck' : ck
|
||
|
|
, 'selrom' : selrom
|
||
|
|
, 'nck' : nck
|
||
|
|
, 'mux4' : mux4
|
||
|
|
, 'sel5' : sel4
|
||
|
|
, 'mux5' : mux5
|
||
|
|
, 'sek5' : sel5
|
||
|
|
}
|
||
|
|
)
|
||
|
|
|
||
|
|
# Lignes 6 et 7
|
||
|
|
instanciate ( "rom_dec_adbuf"
|
||
|
|
, "ad0"
|
||
|
|
, map = { 'ad' : ad[0]
|
||
|
|
, 'adx' : a0
|
||
|
|
, 'nadx' : na0
|
||
|
|
}
|
||
|
|
)
|
||
|
|
|
||
|
|
instanciate ( "rom_dec_adbuf"
|
||
|
|
, "ad1"
|
||
|
|
, map = { "ad => ad[1]"
|
||
|
|
, "adx => a1"
|
||
|
|
, "nadx => na1"
|
||
|
|
}
|
||
|
|
)
|
||
|
|
|
||
|
|
for j in range ( 0, nword, 64 ) :
|
||
|
|
thisMap = { 'nck6' : nck
|
||
|
|
, 'nck7' : nck
|
||
|
|
, 'sel6' : sel6
|
||
|
|
, 'sel7' : sel7
|
||
|
|
, 'line6' : line6[j]
|
||
|
|
, 'line7' : line7[j]
|
||
|
|
}
|
||
|
|
|
||
|
|
if nword != 64 : thisMap['col'] = col[j]
|
||
|
|
else : thisMap['col'] = vdd
|
||
|
|
|
||
|
|
instanciate ( "rom_dec_line67"
|
||
|
|
, "and67_%d" % j
|
||
|
|
, map = thisMap
|
||
|
|
)
|
||
|
|
|
||
|
|
if nword != 128 : # pas de sortie tristate
|
||
|
|
instanciate ( "rom_dec_selmux67"
|
||
|
|
, "selmux67"
|
||
|
|
, map = { 'a0' : a0
|
||
|
|
, 'na0' : na0
|
||
|
|
, 'a1' : a1
|
||
|
|
, 'na1' : na1
|
||
|
|
, 'a2' : a2
|
||
|
|
, 'na2' : na2
|
||
|
|
, 'a3' : a3
|
||
|
|
, 'na3' : na3
|
||
|
|
, 'a4' : a4
|
||
|
|
, 'na4' : na4
|
||
|
|
, 'a5' : a5
|
||
|
|
, 'na5' : na5
|
||
|
|
, 'ck' : ck
|
||
|
|
, 'selrom' : selrom
|
||
|
|
, 'nck' : nck
|
||
|
|
, 'mux6' : mux6
|
||
|
|
, 'sel6' : sel6
|
||
|
|
, 'mux7' : mux7
|
||
|
|
, 'sel7' : sel7
|
||
|
|
}
|
||
|
|
)
|
||
|
|
|
||
|
|
else : # pas de sortie tristate - 128 mots
|
||
|
|
instanciate ( "rom_dec_selmux67_128"
|
||
|
|
, "selmux67"
|
||
|
|
, map = { 'a0' : a0
|
||
|
|
, 'na0' : na0
|
||
|
|
, 'a1' : a1
|
||
|
|
, 'na1' : na1
|
||
|
|
, 'a2' : a2
|
||
|
|
, 'na2' : na2
|
||
|
|
, 'a3' : a3
|
||
|
|
, 'na3' : na3
|
||
|
|
, 'a4' : a4
|
||
|
|
, 'na4' : na4
|
||
|
|
, 'a5' : a5
|
||
|
|
, 'na5' : na5
|
||
|
|
, 'a6' : ad[6]
|
||
|
|
, 'selrom' : selrom
|
||
|
|
, 'a6x' : col_64
|
||
|
|
, 'na6x' : col_0
|
||
|
|
, 'mux6' : mux6
|
||
|
|
, 'sel6' : sel6
|
||
|
|
, 'mux7' : mux7
|
||
|
|
, 'sel7' : sel7
|
||
|
|
}
|
||
|
|
)
|
||
|
|
|
||
|
|
# Ligne 9 dans le cas 1024 mots
|
||
|
|
if nword == 1024 :
|
||
|
|
instanciate ( "rom_dec_nop"
|
||
|
|
, "nop"
|
||
|
|
)
|
||
|
|
|
||
|
|
for j in range ( 0, nword, 64 ) :
|
||
|
|
thisMap = { 'q' : col[j] }
|
||
|
|
|
||
|
|
if ( j >> 6 ) % 2 == 0 : thisMap['i0'] = na6x
|
||
|
|
else : thisMap['i0'] = a6x
|
||
|
|
|
||
|
|
if ( j >> 7 ) % 2 == 0 : thisMap['i1'] = na7x
|
||
|
|
else : thisMap['i1'] = a7x
|
||
|
|
|
||
|
|
if ( j >> 8 ) % 2 == 0 : thisMap['i2'] = na8x
|
||
|
|
else : thisMap['i2'] = a8x
|
||
|
|
|
||
|
|
if ( j >> 9 ) % 2 == 0 : thisMap['i3'] = na9x
|
||
|
|
else : thisMap['i3'] = a9x
|
||
|
|
|
||
|
|
instanciate ( "rom_dec_col4"
|
||
|
|
, "col_%d" % j
|
||
|
|
, map = thisMap
|
||
|
|
)
|
||
|
|
|
||
|
|
instanciate ( "rom_dec_colbuf"
|
||
|
|
, "colbuf6"
|
||
|
|
, map = { " => ad[6]"
|
||
|
|
, " => a6x"
|
||
|
|
, " => na6x"
|
||
|
|
)
|
||
|
|
|
||
|
|
instanciate ( "rom_dec_colbuf"
|
||
|
|
, "colbuf7"
|
||
|
|
, NOSYM
|
||
|
|
, FIXED
|
||
|
|
, "a => ad[7]"
|
||
|
|
, "ax => a7x"
|
||
|
|
, "nax => na7x"
|
||
|
|
, vdd
|
||
|
|
, vss
|
||
|
|
)
|
||
|
|
|
||
|
|
LV_name.PLACE_RIGHT ( "rom_dec_colbuf"
|
||
|
|
, "colbuf8"
|
||
|
|
, NOSYM
|
||
|
|
, FIXED
|
||
|
|
, "a => ad[8]"
|
||
|
|
, "ax => a8x"
|
||
|
|
, "nax => na8x"
|
||
|
|
, vdd
|
||
|
|
, vss
|
||
|
|
)
|
||
|
|
|
||
|
|
LV_name.PLACE_RIGHT ( "rom_dec_colbuf"
|
||
|
|
, "colbuf9"
|
||
|
|
, NOSYM
|
||
|
|
, FIXED
|
||
|
|
, "a => ad[9]"
|
||
|
|
, "ax => a9x"
|
||
|
|
, "nax => na9x"
|
||
|
|
, vdd
|
||
|
|
, vss
|
||
|
|
)
|
||
|
|
|
||
|
|
# Ligne 9 dans le cas 512 mots
|
||
|
|
if nword == 512 :
|
||
|
|
LV_name.PLACE ( "rom_dec_nop"
|
||
|
|
, "nop"
|
||
|
|
, NOSYM
|
||
|
|
, 0
|
||
|
|
, ( nbit + 8 ) * HCELL
|
||
|
|
, FIXED
|
||
|
|
, vdd
|
||
|
|
, vss
|
||
|
|
)
|
||
|
|
|
||
|
|
for j in range ( 0, nword, 64 ) :
|
||
|
|
if ( j >> 6 ) % 2 == 0 : x6 = "i0 => na6x"
|
||
|
|
else : x6 = "i0 => a6x"
|
||
|
|
|
||
|
|
if ( j >> 7 ) % 2 == 0 : x7 = "i1 => na7x"
|
||
|
|
else : x7 = "i1 => a7x"
|
||
|
|
|
||
|
|
if ( j >> 8 ) % 2 == 0 : x8 = "i2 => na8x"
|
||
|
|
else : x8 = "i2 => a8x"
|
||
|
|
|
||
|
|
LV_name.PLACE_RIGHT ( "rom_dec_col3"
|
||
|
|
, "col_%d" % j
|
||
|
|
, NOSYM
|
||
|
|
, FIXED
|
||
|
|
, x6
|
||
|
|
, x7
|
||
|
|
, x8
|
||
|
|
, "q => col_%d" % j
|
||
|
|
, vdd
|
||
|
|
, vss
|
||
|
|
)
|
||
|
|
|
||
|
|
LV_name.PLACE_RIGHT ( "rom_dec_colbuf"
|
||
|
|
, "colbuf6"
|
||
|
|
, NOSYM
|
||
|
|
, FIXED
|
||
|
|
, "a => ad[6]"
|
||
|
|
, "ax => a6x"
|
||
|
|
, "nax => na6x"
|
||
|
|
, vdd
|
||
|
|
, vss
|
||
|
|
)
|
||
|
|
|
||
|
|
LV_name.PLACE_RIGHT ( "rom_dec_colbuf"
|
||
|
|
, "colbuf7"
|
||
|
|
, NOSYM
|
||
|
|
, FIXED
|
||
|
|
, "a => ad[7]"
|
||
|
|
, "ax => a7x"
|
||
|
|
, "nax => na7x"
|
||
|
|
, vdd
|
||
|
|
, vss
|
||
|
|
)
|
||
|
|
|
||
|
|
LV_name.PLACE_RIGHT ( "rom_dec_colbuf"
|
||
|
|
, "colbuf8"
|
||
|
|
, NOSYM
|
||
|
|
, FIXED
|
||
|
|
, "a => ad[8]"
|
||
|
|
, "ax => a8x"
|
||
|
|
, "nax => na8x"
|
||
|
|
, vdd
|
||
|
|
, vss
|
||
|
|
)
|
||
|
|
|
||
|
|
# Ligne 9 dans le cas 256 mots
|
||
|
|
if nword == 256 :
|
||
|
|
LV_name.PLACE ( "rom_dec_nop"
|
||
|
|
, "nop"
|
||
|
|
, NOSYM
|
||
|
|
, 0
|
||
|
|
, ( nbit + 8 ) * HCELL
|
||
|
|
, FIXED
|
||
|
|
, vdd
|
||
|
|
, vss
|
||
|
|
)
|
||
|
|
|
||
|
|
for j in range ( 0, nword, 64 ) :
|
||
|
|
if ( j >> 6 ) % 2 == 0 : x6 = "i0 => na6x"
|
||
|
|
else : x6 = "i0 => a6x"
|
||
|
|
|
||
|
|
if ( j >> 7 ) % 2 == 0 : x7 = "i1 => na7x"
|
||
|
|
else : x7 = "i1 => a7x"
|
||
|
|
|
||
|
|
LV_name.PLACE_RIGHT ( "rom_dec_col2"
|
||
|
|
, "col_%d" % j
|
||
|
|
, NOSYM
|
||
|
|
, FIXED
|
||
|
|
, x6
|
||
|
|
, x7
|
||
|
|
, "q => col_%d" % j
|
||
|
|
, vdd
|
||
|
|
, vss
|
||
|
|
)
|
||
|
|
|
||
|
|
LV_name.PLACE_RIGHT ( "rom_dec_colbuf"
|
||
|
|
, "colbuf6"
|
||
|
|
, NOSYM
|
||
|
|
, FIXED
|
||
|
|
, "a => ad[6]"
|
||
|
|
, "ax => a6x"
|
||
|
|
, "nax => na6x"
|
||
|
|
, vdd
|
||
|
|
, vss
|
||
|
|
)
|
||
|
|
|
||
|
|
LV_name.PLACE_RIGHT ( "rom_dec_colbuf"
|
||
|
|
, "colbuf7"
|
||
|
|
, NOSYM
|
||
|
|
, FIXED
|
||
|
|
, "a => ad[7]"
|
||
|
|
, "ax => a7x"
|
||
|
|
, "nax => na7x"
|
||
|
|
, vdd
|
||
|
|
, vss
|
||
|
|
)
|
||
|
|
|
||
|
|
# ## Routage des rappels d'alimentation et des signaux hors grille ##
|
||
|
|
# y1 = nbit * HCELL
|
||
|
|
#
|
||
|
|
# if nword > 128 : y2 = ( nbit + 9 ) * HCELL
|
||
|
|
# else : y2 = ( nbit + 8 ) * HCELL
|
||
|
|
#
|
||
|
|
# if type == 0 : x2 = ( nword / 64 * 50 ) + 150
|
||
|
|
# else : x2 = ( nword / 64 * 50 ) + 170
|
||
|
|
#
|
||
|
|
# # alimentations verticales ALU3
|
||
|
|
# LV_name.PHSEG ( CALU3,12, "vdd", 10, 0, 10, y2)
|
||
|
|
# LV_name.PHSEG ( CALU3, 2, "vss", 20, 0, 20, y2)
|
||
|
|
# LV_name.PHSEG ( CALU3, 2, "vss", 30, 0, 30, y2)
|
||
|
|
#
|
||
|
|
# for j in range ( 0, nword, 64 ) :
|
||
|
|
# LV_name.PHSEG ( CALU3, 2, "vss", 55 + ( 50 * j / 64 ), 0, 55 + ( 50 * j / 64 ), y2 )
|
||
|
|
# LV_name.PHSEG ( CALU3, 2, "vss", 80 + ( 50 * j / 64 ), 0, 80 + ( 50 * j / 64 ), y2 )
|
||
|
|
#
|
||
|
|
# if type == 0 :
|
||
|
|
# LV_name.PHSEG ( CALU3, 2, "vss", 125 + ( nword / 64 * 50 ), 0, 125 + ( nword / 64 * 50 ), y1 )
|
||
|
|
# LV_name.PHSEG ( CALU3, 2, "vdd", 135 + ( nword / 64 * 50 ), 0, 135 + ( nword / 64 * 50 ), y1 )
|
||
|
|
# LV_name.PHSEG ( CALU3, 2, "vdd", 145 + ( nword / 64 * 50 ), 0, 145 + ( nword / 64 * 50 ), y1 )
|
||
|
|
#
|
||
|
|
# else :
|
||
|
|
# LV_name.PHSEG ( CALU3, 2, "vss", 135 + ( nword / 64 * 50 ), 0, 135 + ( nword / 64 * 50 ), y1 )
|
||
|
|
# LV_name.PHSEG ( CALU3, 2, "vdd", 145 + ( nword / 64 * 50 ), 0, 145 + ( nword / 64 * 50 ), y1 )
|
||
|
|
# LV_name.PHSEG ( CALU3, 2, "vss", 155 + ( nword / 64 * 50 ), 0, 155 + ( nword / 64 * 50 ), y2 )
|
||
|
|
# LV_name.PHSEG ( CALU3, 2, "vdd", 165 + ( nword / 64 * 50 ), 0, 165 + ( nword / 64 * 50 ), y2 )
|
||
|
|
#
|
||
|
|
# # alimemtations horizontales ALU2
|
||
|
|
# for i in range ( 0, nbit, 4 ) :
|
||
|
|
# LV_name.PHSEG ( CALU2, 2, "vss", 0, i * HCELL, x2, i * HCELL )
|
||
|
|
#
|
||
|
|
# for l in range ( 0, 8, 2 ) :
|
||
|
|
# LV_name.PHSEG ( CALU2, 2, "vss", 0, ( nbit + l ) * HCELL, x2, ( nbit + l ) * HCELL )
|
||
|
|
# LV_name.PHSEG ( CALU2, 2, "vdd", 0, ( nbit + l + 1 ) * HCELL, x2, ( nbit + l + 1 ) * HCELL )
|
||
|
|
#
|
||
|
|
# LV_name.PHSEG ( CALU2, 2, "vss", 0, ( nbit + 8 ) * HCELL, x2, ( nbit + 8 ) * HCELL )
|
||
|
|
#
|
||
|
|
# if nword > 128 : LV_name.PHSEG ( CALU2, 2, "vdd", 0, ( nbit + 9 ) * HCELL, x2, ( nbit + 9 ) * HCELL )
|
||
|
|
#
|
||
|
|
# # alimentations horizontales ALU1
|
||
|
|
# for i in range ( 0, nbit, 2 ) :
|
||
|
|
# LV_name.PHSEG ( CALU1, 6, "vss", 0 , HCELL * i + 3, 5, HCELL * i + 3 )
|
||
|
|
# LV_name.PHSEG ( CALU1, 6, "vss", x2 - 5, HCELL * i + 3, x2, HCELL * i + 3 )
|
||
|
|
# LV_name.PHSEG ( CALU1, 6, "vdd", 0 , HCELL * i + 47, 5, HCELL * i + 47 )
|
||
|
|
# LV_name.PHSEG ( CALU1, 6, "vdd", x2 - 5, HCELL * i + 47, x2, HCELL * i + 47 )
|
||
|
|
# LV_name.PHSEG ( CALU1, 6, "vdd", 0 , HCELL * i + 53, 5, HCELL * i + 53 )
|
||
|
|
# LV_name.PHSEG ( CALU1, 6, "vdd", x2 - 5, HCELL * i + 53, x2, HCELL * i + 53 )
|
||
|
|
# LV_name.PHSEG ( CALU1, 6, "vss", 0 , HCELL * i + 97, 5, HCELL * i + 97 )
|
||
|
|
# LV_name.PHSEG ( CALU1, 6, "vss", x2 - 5, HCELL * i + 97, x2, HCELL * i + 97 )
|
||
|
|
#
|
||
|
|
# for l in range ( 0, 8, 2 ) :
|
||
|
|
# LV_name.PHSEG ( CALU1, 6, "vss", 0, y1 + HCELL * l + 3, x2, y1 + HCELL * l + 3 )
|
||
|
|
# LV_name.PHSEG ( CALU1, 6, "vdd", 0, y1 + HCELL * l + 47, x2, y1 + HCELL * l + 47 )
|
||
|
|
# LV_name.PHSEG ( CALU1, 6, "vdd", 0, y1 + HCELL * l + 53, x2, y1 + HCELL * l + 53 )
|
||
|
|
# LV_name.PHSEG ( CALU1, 6, "vss", 0, y1 + HCELL * l + 97, x2, y1 + HCELL * l + 97 )
|
||
|
|
#
|
||
|
|
# if nword > 128 :
|
||
|
|
# LV_name.PHSEG ( CALU1, 6, "vss", 0, y1 + 403, x2, y1 + 403 )
|
||
|
|
# LV_name.PHSEG ( CALU1, 6, "vdd", 0, y1 + 447, x2, y1 + 447 )
|
||
|
|
#
|
||
|
|
# # routage des lignes de bit horizontales hors grille
|
||
|
|
# for i in range ( nbit ) :
|
||
|
|
# for l inr ange ( 8 ) :
|
||
|
|
# x1 = GET_REF_X ( "in%d" % i), "bit%d" % ,l ) )
|
||
|
|
# y1 = GET_REF_Y ( "in%d" % i), "bit%d" % ,l ) )
|
||
|
|
# x2 = GET_REF_X ( "out%d" % i), "bit%d" % ,l ) )
|
||
|
|
# y2 = GET_REF_Y ( "out%d" % i), "bit%d" % ,l ) )
|
||
|
|
#
|
||
|
|
# LV_name.PHSEG ( ALU2, 2, "bit%d_%d" % ( l, i ), x1, y1, x2, y2 )
|
||
|
|
#
|
||
|
|
# # cablage a 1 de l'entree col dans le cas 64 mots
|
||
|
|
# if nword == 64 :
|
||
|
|
# x1 = GET_REF_X ( "and01_0", "refcol" )
|
||
|
|
# y1 = GET_REF_Y ( "and01_0", "refcol" )
|
||
|
|
# PHBIGVIA ( CONT_VIA2, x1, y1, 0, 0, "vdd" )
|
||
|
|
#
|
||
|
|
# x1 = GET_REF_X ( "and23_0", "refcol" )
|
||
|
|
# y1 = GET_REF_Y ( "and23_0", "refcol" )
|
||
|
|
# PHBIGVIA ( CONT_VIA2, x1, y1, 0, 0, "vdd" )
|
||
|
|
#
|
||
|
|
# x1 = GET_REF_X ( "and45_0", "refcol" )
|
||
|
|
# y1 = GET_REF_Y ( "and45_0", "refcol" )
|
||
|
|
# PHBIGVIA ( CONT_VIA2, x1, y1, 0, 0, "vdd" )
|
||
|
|
#
|
||
|
|
# x1 = GET_REF_X ( "and67_0", "refcol" )
|
||
|
|
# y1 = GET_REF_Y ( "and67_0", "refcol" )
|
||
|
|
# PHBIGVIA ( CONT_VIA2, x1, y1, 0, 0, "vdd" )
|
||
|
|
#
|
||
|
|
# # Codage Plan Memoire (codage diffusion)
|
||
|
|
# a modifier pour creer ces segments dans une figure separee
|
||
|
|
# for j in range ( 0, nword ; j+=32) : # boucle sur les cellules
|
||
|
|
# for k in range ( 4 ) : # boucle sur les colonnes
|
||
|
|
# for l in range ( 8 ) : # boucle sur le multiplexeur de sortie
|
||
|
|
# for i in range ( nbit ) : # boucle sur les bits du mot
|
||
|
|
# x1 = GET_REF_X ( "bit%d_%d" % ( i, j ), "ref%d%d" % ( k, l ) )
|
||
|
|
# y1 = GET_REF_Y ( "bit%d_%d" % ( i, j ), "ref%d%d" % ( k, l ) )
|
||
|
|
#
|
||
|
|
# if i < 32 :
|
||
|
|
# value = data[2*(j + 8*k + l)]
|
||
|
|
#
|
||
|
|
# if (value>>i ) % 2 == 0 : LV_name.PHSEG ( NTRANS, 1, "", x1, y1 - 3, x1, y1 + 3 )
|
||
|
|
# else : LV_name.PHSEG ( POLY , 1, "", x1, y1 - 3, x1, y1 + 3 )
|
||
|
|
#
|
||
|
|
# else :
|
||
|
|
# value = data[2*(j + 8*k + l)+1]
|
||
|
|
#
|
||
|
|
# if ( value>>(i-32) ) % 2 == 0 : LV_name.PHSEG ( NTRANS, 1, "", x1, y1 - 3, x1, y1 + 3 )
|
||
|
|
# else : LV_name.PHSEG ( POLY , 1, "", x1, y1 - 3, x1, y1 + 3 )
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
########## ROM_VHDL ##########
|
||
|
|
##############################
|
||
|
|
def ROM_VHDL () :
|
||
|
|
global nbit
|
||
|
|
global LV_flags
|
||
|
|
global LV_ModelName
|
||
|
|
global nword
|
||
|
|
|
||
|
|
print "ROM behavior not yet implemented"
|
||
|
|
|
||
|
|
# fileName = LV_ModelName + ".vbe"
|
||
|
|
#
|
||
|
|
# file = open ( fileName, "w+" )
|
||
|
|
#
|
||
|
|
# if nword == 64 : adrange = 6
|
||
|
|
# elif nword == 128 : adrange = 7
|
||
|
|
# elif nword == 256 : adrange = 8
|
||
|
|
# elif nword == 512 : adrange = 9
|
||
|
|
# elif nword == 1024 : adrange = 10
|
||
|
|
#
|
||
|
|
# sBusWide0 = VHDL_BUS_WIDE ( nbit - 1, 0, nbit, LV_flags )
|
||
|
|
# sBusWide1 = VHDL_BUS_WIDE ( adrange - 1, 0, nbit, LV_flags )
|
||
|
|
#
|
||
|
|
# ## Entity description ##
|
||
|
|
# file.write ( "\nENTITY %s IS\n PORT (\n" % LV_ModelName )
|
||
|
|
#
|
||
|
|
# file.write ( "%14s : in BIT;\n" % "ck" )
|
||
|
|
# file.write ( "%14s : in BIT;\n" % "selrom" )
|
||
|
|
# file.write ( "%14s : in BIT_VECTOR %s;\n" % ( "ad", sBusWide1 ) )
|
||
|
|
# file.write ( "%14s : out BIT_VECTOR %s;\n" % ( "data", sBusWide0 ) )
|
||
|
|
#
|
||
|
|
# ## Power supplies terminals ##
|
||
|
|
# file.write ( "%14s : in BIT;\n" % "vdd" )
|
||
|
|
# file.write ( "%14s : in BIT\n" % "vss" )
|
||
|
|
#
|
||
|
|
# ## End of entity description ##
|
||
|
|
# file.write ( " );\nEND %s;\n\n\n" % LV_ModelName )
|
||
|
|
#
|
||
|
|
# ## Architecture description ##
|
||
|
|
# file.write ( "ARCHITECTURE VBE OF %s IS\n\n" % LV_ModelName )
|
||
|
|
#
|
||
|
|
# ## Signals ##
|
||
|
|
#
|
||
|
|
#
|
||
|
|
#
|
||
|
|
# ## Behavior ##
|
||
|
|
# file.write ( "\nBEGIN\n\n" )
|
||
|
|
#
|
||
|
|
#
|
||
|
|
#
|
||
|
|
#
|
||
|
|
#
|
||
|
|
# ## Assert ##
|
||
|
|
# file.write ( " ASSERT (vdd = '1')\n" )
|
||
|
|
# file.write ( " REPORT \"Power supply is missing on vdd of Model %s.\"\n" % LV_modelName )
|
||
|
|
# file.write ( " SEVERITY WARNING;\n\n" )
|
||
|
|
#
|
||
|
|
#
|
||
|
|
# file.write ( " ASSERT (vss = '0')\n" )
|
||
|
|
# file.write ( " REPORT \"Power supply is missing on vss of Model %s.\"\n" % LV_modelName )
|
||
|
|
# file.write ( " SEVERITY WARNING;\n\n" )
|
||
|
|
#
|
||
|
|
# ## End of Architectural description ##
|
||
|
|
# file.write ( "END VBE;\n" )
|
||
|
|
#
|
||
|
|
# file.close ()
|