2015-02-27 11:16:03 -06:00
|
|
|
# -*- Mode:Python; explicit-buffer-name: "etesian.conf<common>" -*-
|
|
|
|
|
|
|
|
|
|
# Etesian parameters.
|
|
|
|
|
parametersTable = \
|
|
|
|
|
( ('etesian.aspectRatio' , TypePercentage, 100 , { 'min':10, 'max':1000 } )
|
|
|
|
|
, ('etesian.spaceMargin' , TypePercentage, 5 )
|
|
|
|
|
, ('etesian.uniformDensity' , TypeBool , False )
|
|
|
|
|
, ('etesian.routingDriven' , TypeBool , False )
|
In CRL, update real conf. files. Smarter management of pin in LEF parser.
* Change: In CRL Core, etc/, update the configuration files of real
technologies. Mostly for FreePDK 45. This work is also done for
AMS c35b4 (350nm) but in a private (SoC) git repository.
Added a new parameter 'lefImport.minTerminalwidth' for the
minimum size (width) of a metal1 terminal in standard cells.
Corrected bug of the minimum trace level which must be
initialized to a great value and *not* zero;
* Change: In CRL Core, BlifParser, detect when there is no tie low
or tie high defined, issue an error (connexion left open) but
continue.
* New: In CRL::RoutingLayerGauge, new overlad of getTrackPosition()
with the parameter set of getTrackIndex(). Used to know if a
terminal is on-grid or not.
* New: In CRL::LefImport, smarter management of metal1 pins. Adds a
_pinPostProcess() function to select the external components
among the various shapes. If the gauge is VH, all the pin rectangles
are translateds into vertical segments (even if the metal1 gauge
says the tracks are horizontals).
The _pinPostProcess() function adds as external components of
a net, only the segments of a sufficent width as given in
'lefImport.minTerminalWidth' and that are on-grid.
2018-01-06 09:18:33 -06:00
|
|
|
, ('etesian.feedNames' , TypeString , 'tie_x0,rowend_x0')
|
|
|
|
|
, ('etesian.cell.zero' , TypeString , 'zero_x0' )
|
Added core2chip support for Phenitec80.
This commit degrades the run success rate of ARMv2a to 87% (40 iters).
* New: In CRLcore/etc/.../kite.conf, add configuration parameters:
katana.termSatReservedlocal
katana.termSatthreshold
for the new edge capacity computation system.
* New: In CRLcore/etc/symbolic/phenitec06/, add support for N. Shimizu
small I/O pads (supplied in phlib80). Tune various parameters of
Anabatic/Katana to increase routing success.
* Change: In CRLcore/alliance/ap/ApParser, make Pin external components,
so RoutingPad will be build upon in global routing.
Do not complain when a I/O pad has a physical instance that did
not exists in the netlist. Just create it (appeared in phlib80).
When no netlist instance exists in a pad, the pad Cell is still
considered as terminal.
* New: In Etesian::BloatCells, new profile named "3metals" better suited
for two routing metals technologies (i.e. Phenitec).
* New: In Anabatic::RawGCellsUnder, new CTOR which take only source &
target points instead of a segment. Needed to manage wide segment for
which the axis to consider is not that of the segment (one axis for
each track it intersect).
* New: In Anabatic::GCell, add a RoutingPad count attribute, for Edge
reservation computation.
* New: In AnabaticEngine::computeEdgeCapacities(), instead of decreasing
all edges of a fixed amount (hTrackReservedLocal), guess the GCell
cluttering from the number of RoutingPads that it contains.
For non-saturated GCells, the four edges are decreased by the number
of RoutingPads. We use the maximum from the two neigboring GCells.
The hTrackReservedLocal parameter is now used only as a *maximum*
that the edge reservation can reach.
If a GCell is saturated (more than 8 RoutingPads, the saturation is
propagated horizontally to 2 neigboring GCells).
* Change: In AutoContactTerminal::getNativeConstraintBox(), use a more
flexible gauge name matching for terminal vertical extensions correction.
Namely, match all "msxlib*" kind of gauges.
* Change: In AutoSegment::setAxis(), add the ability to force the axis
position, even if it is a non-canonical segment. Maybe needed in the
initialisation steo, before the first canonisation is performed.
* New: In NetBuilder, added new methods _do_1G_1PinM1() and _do_2G_1PinM1(),
to manage coronas for Phenitec designs.
To avoid various side effects from segments being too close from
the north / east side of the routing area, make those segments fixeds.
* Change: In KatanaEngine::annotateGlobalGraph(), the management of wide
wires was wrong. The axis to use to find the underlying GCells is the
one of the track, not of the segment. This was creating bad edge
capacity computation under the power ring of a block and subsequently
routing failures.
* New: In Kanata::Manipulator, added method reprocessParallels(), not used
though, but keep it anyway, might be of use later...
* New: In Kanata::Manipulator, added method avoidBlockage() for terminal
METAL2 in non-preferred direction, restrict the terminal and turn
constraint box at the current position of the perpandicular, so it
doesn't create a deadlock in METAL2.
* Change: In SegmentFsm::conflictSolveByPlaceds(), if we cannot break
using the whole overlap, try the first atomic overlap.
* New: In SegmentFsm::_slackenStrap(), manage conflict between a non-prefered
segment and a blockage, this when to call avoidBlockage()...
* New: In Katana::Configuration, management of the new edge computation
parameters:
katana.termSatReservedlocal
katana.termSatthreshold
* New: In Cumulus/plugins/Core2Chip, support for Phenitec I/O pads.
2019-09-17 10:05:54 -05:00
|
|
|
, ('etesian.cell.one' , TypeString , 'one_x0' )
|
|
|
|
|
, ('etesian.bloat' , TypeString , 'default' )
|
In CRL, update real conf. files. Smarter management of pin in LEF parser.
* Change: In CRL Core, etc/, update the configuration files of real
technologies. Mostly for FreePDK 45. This work is also done for
AMS c35b4 (350nm) but in a private (SoC) git repository.
Added a new parameter 'lefImport.minTerminalwidth' for the
minimum size (width) of a metal1 terminal in standard cells.
Corrected bug of the minimum trace level which must be
initialized to a great value and *not* zero;
* Change: In CRL Core, BlifParser, detect when there is no tie low
or tie high defined, issue an error (connexion left open) but
continue.
* New: In CRL::RoutingLayerGauge, new overlad of getTrackPosition()
with the parameter set of getTrackIndex(). Used to know if a
terminal is on-grid or not.
* New: In CRL::LefImport, smarter management of metal1 pins. Adds a
_pinPostProcess() function to select the external components
among the various shapes. If the gauge is VH, all the pin rectangles
are translateds into vertical segments (even if the metal1 gauge
says the tracks are horizontals).
The _pinPostProcess() function adds as external components of
a net, only the segments of a sufficent width as given in
'lefImport.minTerminalWidth' and that are on-grid.
2018-01-06 09:18:33 -06:00
|
|
|
|
2015-02-27 11:16:03 -06:00
|
|
|
, ("etesian.effort" , TypeEnumerate , 2
|
|
|
|
|
, { 'values':( ("Fast" , 1)
|
|
|
|
|
, ("Standard" , 2)
|
|
|
|
|
, ("High" , 3)
|
|
|
|
|
, ("Extreme" , 4) ) }
|
|
|
|
|
)
|
|
|
|
|
, ("etesian.graphics" , TypeEnumerate , 2
|
|
|
|
|
, { 'values':( ("Show every step" , 1)
|
|
|
|
|
, ("Show lower bound" , 2)
|
|
|
|
|
, ("Show result only" , 3) ) }
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
layoutTable = \
|
|
|
|
|
( (TypeTab , 'Etesian', 'etesian')
|
|
|
|
|
|
|
|
|
|
, (TypeTitle , 'Placement area')
|
|
|
|
|
, (TypeOption, "etesian.aspectRatio" , "Aspect Ratio, X/Y (%)", 0 )
|
|
|
|
|
, (TypeOption, "etesian.spaceMargin" , "Space Margin" , 1 )
|
|
|
|
|
, (TypeRule ,)
|
|
|
|
|
|
|
|
|
|
, (TypeTitle , 'Etesian - Placer')
|
Python Script launcher extended to accomodate Chams.
* New: In VLSISAPD, in Configuration, add a new priority level UserFile
to distinguish between the system configuration files and the user's
configuration files (which take precedence).
* New: In Hurricane, in Script (Python), improve the API to be able
to support Chams (and remove the duplicate capability from it).
Add separate functions to perform the initialize/run(s)/finalize
cycle step by step.
* Change: In CRL Core, rename real technology <hcmos9> to <hcmos9gp>,
it's offcial name from CMP/ST. This is the 130nm.
Move the reading of the symbolic & real technologies names from
coriolisInit.py to helpers.__init__.py, to be shared with
chamsInit.py.
To avoid a clash of names inside of helpers, the two variables
of techno.py are renamed "symbolicTechnology" and "realTechnology".
Move python init system from crlcore/src/crlcore to crlcore/python.
* New: In CRL Core, In Utilities, add site-packages/pharos to the
PYTHONPATH.
* Change: In Kite, move python init system from kite/src/init to
kite/python.
2015-03-17 10:31:24 -05:00
|
|
|
, (TypeOption, "etesian.uniformDensity", "Uniform density" , 0 )
|
|
|
|
|
, (TypeOption, "etesian.routingDriven" , "Routing driven" , 0 )
|
|
|
|
|
, (TypeOption, "etesian.effort" , "Placement effort" , 1 )
|
|
|
|
|
, (TypeOption, "etesian.graphics" , "Placement view" , 1 )
|
2015-02-27 11:16:03 -06:00
|
|
|
, (TypeRule ,)
|
|
|
|
|
)
|