riscv
/
coriolis
mirror of https://gitlab.lip6.fr/vlsi-eda/coriolis.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
coriolis/crlcore/etc/45/ispd18/hMetis.conf

6 lines
137 B
Plaintext
Raw Normal View History

First step in supporting ISPD18 detailed routing benchmarks. * Change: In CRL::DefImport, added callback to read the DEF UNITS statement and perform a correct length conversion. Previously set to read pseudo lambdas in hundredth of microns. Added DefParser::getLefCell() to lookup master cells in the LEF libraries before looking in the Alliance ones (rooted under "LEF" library). * Change: In CRL::LefParser::_pinPostProcess(), when no segment suitable for terminal connexion is found, add all of them. This is a quick hack and an a correct policy that match all techno must be implemeneted. * New: In CRL::pyCRL, add a Python wrapper for DefImport. * New: In CRL/etc/45/ispd18/ added configuration files for the "real" technology used by the ISPD18 45nm design benchmarks.
2019-03-29 05:07:55 -05:00
# -*- Mode:Python; explicit-buffer-name: "hMetis.conf<ispd18>" -*-
import helpers
execfile( helpers.sysConfDir+'/common/hMetis.conf' )