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coriolis/crlcore/etc/symbolic/vsc200/plugins.conf

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Support for Net alias names. Blif parser enhancements. * New: In Hurricane, In Net & Cell, support for Net aliases names. Use a structure based on a simple ring of NetAliasHook. The Net holds a global map, sorted by names of all the aliases of all Nets. Elements NetAliasesHook of the map are slaves of ring whose master is an attribute of the Net (it is *not* in the map, as the primary name of the Net). In case of merge, the aliases of both Nets are merged and the name of the merged one become an alias. The Cell::getNet() looks in both the Net map and the aliases to find a Net by name. * Bug: In CRL Core, in coriolisInit.py, reoder the loading of the configuration files so the real technology is read as early as possible to set up the <gridsPerLambda> factor before any lambda is actually computed... * Bug: In CRL Core, in AcmSigda, do not try to fed the file when it has failed to be opened. Throw a clean exception instead. * New: In CRL Core, in Toolbox, add a NamingScheme object to convert a design into VHDL compliant names (mainly from Blif/Verilog). This is extensible in any case. * New: In CRL Core, in BlifParser, slightly more informative warning messages. Align the loading progress information on the other parsers. Add a capability to select which component of the design will be returned, if there are more than one. Use the "." as separator. For exemple you can request "Processor.Alu", which will load the "Alu" component from the design in "Processor.blif". To be able to save a Blif loaded design, systematically convert all the name for VHDL compliance, as it is the format used by the Coriolis native files (vst). Export the Blif parser to the Python interface. * New: In Kite, In NegociateWindow, add a counter of the number of remaining events. Gives an idea of the ETA... * New: In Unicorn, in cgt.by, add an option to load a Blif design from the command line. * New: In Cumulus, new RSave plugin to save both netlist & layout. Partly redundant with the previous one. Have to better organize that later.
2015-04-16 08:40:02 -05:00
# -*- Mode:Python; explicit-buffer-name: "plugins.conf<cmos>" -*-
#
# THIS SETTINGS ARE NOT CORRECT. MUST ADJUST THEM FOR VSC200.
import helpers
# Contains the layout (shared by all technologies).
#execfile( helpers.sysConfDir+'/common/plugins.conf' )
# Parameters for chip plugin.
parametersTable = \
( ("chip.block.rails.count" , TypeInt , 5 )
, ("chip.block.rails.hWidth" , TypeInt , 12 )
, ("chip.block.rails.vWidth" , TypeInt , 12 )
, ("chip.block.rails.hSpacing" , TypeInt , 6 )
, ("chip.block.rails.vSpacing" , TypeInt , 6 )
, ('chip.pad.pck' , TypeString, 'pck_px')
, ('chip.pad.pvddick' , TypeString, 'pvddick_px')
, ('chip.pad.pvssick' , TypeString, 'pvssick_px')
, ('chip.pad.pvddeck' , TypeString, 'pvddeck_px')
, ('chip.pad.pvsseck' , TypeString, 'pvsseck_px')
, ('clockTree.minimumSide' , TypeInt , 300)
, ('clockTree.buffer' , TypeString, 'buf_x2')
, ('clockTree.placerEngine' , TypeString, 'Etesian')
)