Stratus -- Procedural design language based upon \emph{Python}
\subsubsection{Description}
\emph{Stratus} is a set of \emph{Python} methods/functions dedicated to procedural generation purposes. From a user point of view, \emph{Stratus} is a circuit's description language that allows \emph{Python} programming flow control, variable use, and specialized functions in order to handle vlsi objects.\\
\indent Based upon the \emph{Hurricane} data structures, the \emph{Stratus} language gives the user the ability to describe netlist and layout views.
A configuration file can be used to direct the generation process of Stratus. With this file, the user can choose the output format (vst, vhdl...), the simulator (asimut, ghdl...), the standard cell library... This configuration file named \verb-.st_config.py- must be placed either in the HOME directory or in the current directory. This file contains a set of variables used in the process generation of Stratus, as for example :
\begin{verbatim}
format = 'vhdl'
simulator = 'ghdl'
\end{verbatim}
The default configuration of Stratus uses the Alliance CAD system, ie \verb-'vst'- as \verb-format- and \verb-'asimut'- as \verb-simulator-.
After the description of a cell as a sub-class of \verb-Model-, the cell has to be instantiated. The different methods described before have to be called.
\item Method \verb-Testbench- : Creates the testbench of the cell using the \verb-Stimuli- method to compute the stimuli. The output format depends of the \verb-format- variable given in the configuration file
\item Method \verb-Simul- : Runs the simulation using the simulator named in the configuration file
\indent In order to execute a \emph{Stratus} file (named \verb-file- for example), one has two choices :
\begin{verbatim}
python file.py
\end{verbatim}
\indent Or :
\begin{verbatim}
chmod u+x file.py
./file.py
\end{verbatim}
\indent The names used in \emph{Stratus}, as arguments to \emph{Stratus} functions, should be alphanumerical, including the underscore. The arguments of \emph{Stratus} are case sensitive, so \textsc{VDD} is not equivalent to \textsc{vdd}.\\
\indent Vectorized connectors or signal can be used using the \textsc{[n:m]} construct.\\