80 lines
2.7 KiB
Python
80 lines
2.7 KiB
Python
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#!/usr/bin/env python
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from stratus import *
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class addaccu ( Model ) :
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def Interface ( self ) :
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self.nbit = self._param['nbit']
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self.a = SignalIn ( "a", self.nbit )
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self.b = SignalIn ( "b", self.nbit )
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self.c = SignalIn ( "c", self.nbit )
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self.v = SignalIn ( "v", 1 )
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self.cmd = SignalIn ( "cmd", 1 )
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self.cout = SignalOut ( "cout", 1 )
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self.s = SignalOut ( "s", self.nbit )
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self.vdd = VddIn ( "vdd" )
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self.vss = VssIn ( "vss" )
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def Netlist ( self ) :
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d_aux = Signal ( "d_aux", self.nbit )
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e_aux = Signal ( "e_aux", self.nbit )
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ovr = Signal ( "ovr", 1 )
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Generate ( "DpgenNand2", "nand2%d" % self.nbit
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, param = { 'nbit' : self.nbit
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, 'physical' : True
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}
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)
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temp = Cat ( self.v, self.v, self.v, self.v )
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self.instNand2 = Inst ( "nand2%d" % self.nbit, "instance_nand2"
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, map = { 'i0' : temp
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, 'i1' : self.a
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, 'nq' : d_aux
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, 'vdd' : self.vdd
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, 'vss' : self.vss
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}
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)
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Generate ( "DpgenOr2", "or2%d" % self.nbit
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, param = { 'nbit' : self.nbit
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, 'physical' : True
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}
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)
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self.instOr2 = Inst ( "or2%d" % self.nbit, "instance_or2"
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, map = { 'i0' : d_aux
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, 'i1' : self.b
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, 'q' : e_aux
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, 'vdd' : self.vdd
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, 'vss' : self.vss
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}
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)
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Generate ( "DpgenAdsb2f", "adder%d" % self.nbit
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, param = { 'nbit' : self.nbit
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, 'physical' : True
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}
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)
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self.instAdd2 = Inst ( "adder%d" % self.nbit, "instance_add2"
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, map = { 'i0' : e_aux
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, 'i1' : self.c
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, 'q' : self.s
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, 'add_sub' : self.cmd
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, 'c31' : self.cout
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, 'c30' : ovr
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, 'vdd' : self.vdd
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, 'vss' : self.vss
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}
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)
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def Layout ( self ) :
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Place ( self.instNand2, NOSYM, XY ( 0, 0 ) )
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PlaceRight ( self.instOr2, NOSYM )
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PlaceRight ( self.instAdd2, NOSYM )
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