146 lines
5.1 KiB
Python
146 lines
5.1 KiB
Python
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#!/usr/bin/python
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# This file is part of the Coriolis Project.
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# Copyright (C) Laboratoire LIP6 - Departement ASIM
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# Universite Pierre et Marie Curie
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#
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# Main contributors :
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# Christophe Alexandre <Christophe.Alexandre@lip6.fr>
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# Sophie Belloeil <Sophie.Belloeil@lip6.fr>
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# Hugo Clement <Hugo.Clement@lip6.fr>
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# Jean-Paul Chaput <Jean-Paul.Chaput@lip6.fr>
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# Damien Dupuis <Damien.Dupuis@lip6.fr>
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# Christian Masson <Christian.Masson@lip6.fr>
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# Marek Sroka <Marek.Sroka@lip6.fr>
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#
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# The Coriolis Project is free software; you can redistribute it
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# and/or modify it under the terms of the GNU General Public License
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# as published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# The Coriolis Project is distributed in the hope that it will be
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# useful, but WITHOUT ANY WARRANTY; without even the implied warranty
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# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with the Coriolis Project; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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# USA
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#
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# License-Tag
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# Authors-Tag
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# ===================================================================
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#
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# x-----------------------------------------------------------------x
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# | |
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# | C O R I O L I S |
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# | S t r a t u s - Netlists/Layouts Description |
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# | |
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# | Author : Sophie BELLOEIL |
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# | E-mail : Sophie.Belloeil@asim.lip6.fr |
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# | =============================================================== |
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# | Py Module : "./st_mux.py" |
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# | *************************************************************** |
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# | U p d a t e s |
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# | |
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# x-----------------------------------------------------------------x
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from stratus import *
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class Smux ( Model ) :
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def Interface ( self ) :
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nbit_cmd = self._param['nbit_cmd']
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nbit = self._param['nbit']
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if nbit_cmd < 1 : raise "\n[Stratus ERROR] mux : the number of bits of the command must be greater than 0.\n"
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if nbit < 1 : raise "\n[Stratus ERROR] mux : the number of bits of the inputs must be greater than 0.\n"
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self._cmd = SignalIn ( "cmd", nbit_cmd )
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self._in_tab = []
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for i in range ( int(pow ( 2, nbit_cmd )) ) : self._in_tab += [SignalIn ( "i%d" % i, nbit )]
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self._q = SignalOut ( "q", nbit )
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self._vdd = VddIn ( "vdd" )
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self._vss = VssIn ( "vss" )
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def Netlist ( self ) :
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nbit_cmd = self._param['nbit_cmd']
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nbit = self._param['nbit']
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# If the command is a bus
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#########################
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if nbit_cmd > 1 :
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temp = {}
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# Input nets are renamed
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for i in range ( int(pow ( 2, nbit_cmd )) ) : temp[i] = self._in_tab[i]
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# Temporary nets
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for i in range ( int(pow ( 2, nbit_cmd )), int(pow ( 2, nbit_cmd + 1 ) - 1) ) : temp[i] = Signal ( "temp_%d" % i, nbit )
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bit_cmd = 0
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bit_entree = 0
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bit_sortie = pow ( 2, nbit_cmd )
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for i in range ( nbit_cmd - 1, -1, -1 ) :
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for j in range ( int(pow ( 2, i )) ) :
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Generate ( "Mx2", "mux_%dbits" % nbit, param = { 'nbit' : nbit } )
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Inst ( "mux_%dbits" % nbit
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, map = { 'i0' : temp[2*j+bit_entree]
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, 'i1' : temp[2*j+1+bit_entree]
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, 'cmd' : self._cmd[bit_cmd]
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, 'q' : temp[j+bit_sortie]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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bit_cmd += 1
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bit_entree += pow ( 2, i ) * 2
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bit_sortie += pow ( 2, i )
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self._q <= temp[pow ( 2, nbit_cmd + 1 ) - 2]
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# If the command is a 1 bit net
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###############################
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else :
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Generate ( "Mx2", "mux_%dbits" % nbit, param = { 'nbit' : nbit } )
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Inst ( "mux_%dbits" % nbit
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, map = { 'i0' : self._in_tab[0]
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, 'i1' : self._in_tab[1]
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, 'cmd' : self._cmd
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, 'q' : self._q
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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def GetModelName ( cls, param ) :
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modelName = "smux"
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modelName += "_"
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modelName += str(param['nbit'])
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modelName += "bits"
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modelName += "_"
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modelName += str(param['nbit_cmd'])
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modelName += "cmdbits"
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return modelName
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GetModelName = classmethod ( GetModelName )
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def GetParam ( cls ):
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return {'nbit' : 'integer', 'nbit_cmd' : 'integer'}
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GetParam = classmethod ( GetParam )
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