coriolis/documentation/examples/AM2901/accu.vst

entity accu is
   port (
      cke     : in      bit;
      i       : in      bit_vector(2 downto 0);
      alu_out : in      bit_vector(3 downto 0);
      q0_from : in      bit;
      q3_from : in      bit;
      q0_to   : out     mux_bit bus;
      q3_to   : out     mux_bit bus;
      accu    : inout   bit_vector(3 downto 0);
      vdd     : in      bit;
      vss     : in      bit
 );
end accu;

architecture structural of accu is
Component o2_x2
   port (
      i0  : in      bit;
      i1  : in      bit;
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component no2_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component inv_x2
   port (
      i   : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component ao22_x2
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component an12_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component nao22_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component na2_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component on12_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component na3_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component sff1_x4
   port (
      ck  : in      bit;
      i   : in      bit;
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component buf_x2
   port (
      i   : in      bit;
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component no3_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component ts_x8
   port (
      cmd : in      bit;
      i   : in      bit;
      q   : out     mux_bit bus;
      vdd : in      bit;
      vss : in      bit
 );
end component;

signal not_i          : bit_vector( 2 downto 1);
signal rtlalc_0       : bit_vector( 3 downto 0);
signal on12_x1_sig    : bit;
signal on12_x1_6_sig  : bit;
signal on12_x1_5_sig  : bit;
signal on12_x1_4_sig  : bit;
signal on12_x1_3_sig  : bit;
signal on12_x1_2_sig  : bit;
signal not_aux2       : bit;
signal no3_x1_sig     : bit;
signal no3_x1_2_sig   : bit;
signal nao22_x1_sig   : bit;
signal nao22_x1_4_sig : bit;
signal nao22_x1_3_sig : bit;
signal nao22_x1_2_sig : bit;
signal na3_x1_sig     : bit;
signal na3_x1_8_sig   : bit;
signal na3_x1_7_sig   : bit;
signal na3_x1_6_sig   : bit;
signal na3_x1_5_sig   : bit;
signal na3_x1_4_sig   : bit;
signal na3_x1_3_sig   : bit;
signal na3_x1_2_sig   : bit;
signal na2_x1_sig     : bit;
signal na2_x1_4_sig   : bit;
signal na2_x1_3_sig   : bit;
signal na2_x1_2_sig   : bit;
signal inv_x2_sig     : bit;
signal inv_x2_2_sig   : bit;
signal aux3           : bit;
signal aux1           : bit;
signal aux0           : bit;
signal ao22_x2_sig    : bit;
signal ao22_x2_2_sig  : bit;
signal an12_x1_sig    : bit;
signal an12_x1_2_sig  : bit;

begin

not_aux2_ins : o2_x2
   port map (
      i0  => i(0),
      i1  => not_i(1),
      q   => not_aux2,
      vdd => vdd,
      vss => vss
   );

not_i_2_ins : inv_x2
   port map (
      i   => i(2),
      nq  => not_i(2),
      vdd => vdd,
      vss => vss
   );

not_i_1_ins : inv_x2
   port map (
      i   => i(1),
      nq  => not_i(1),
      vdd => vdd,
      vss => vss
   );

aux3_ins : no2_x1
   port map (
      i0  => i(1),
      i1  => i(0),
      nq  => aux3,
      vdd => vdd,
      vss => vss
   );

aux1_ins : on12_x1
   port map (
      i0  => i(2),
      i1  => accu(2),
      q   => aux1,
      vdd => vdd,
      vss => vss
   );

aux0_ins : on12_x1
   port map (
      i0  => i(2),
      i1  => accu(1),
      q   => aux0,
      vdd => vdd,
      vss => vss
   );

inv_x2_ins : inv_x2
   port map (
      i   => not_aux2,
      nq  => inv_x2_sig,
      vdd => vdd,
      vss => vss
   );

ao22_x2_ins : ao22_x2
   port map (
      i0  => not_i(2),
      i1  => q0_from,
      i2  => inv_x2_sig,
      q   => ao22_x2_sig,
      vdd => vdd,
      vss => vss
   );

nao22_x1_ins : nao22_x1
   port map (
      i0  => rtlalc_0(0),
      i1  => i(2),
      i2  => ao22_x2_sig,
      nq  => nao22_x1_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_ins : na2_x1
   port map (
      i0  => i(0),
      i1  => rtlalc_0(0),
      nq  => na2_x1_sig,
      vdd => vdd,
      vss => vss
   );

on12_x1_ins : on12_x1
   port map (
      i0  => not_i(2),
      i1  => alu_out(0),
      q   => on12_x1_sig,
      vdd => vdd,
      vss => vss
   );

na3_x1_2_ins : na3_x1
   port map (
      i0  => aux3,
      i1  => on12_x1_sig,
      i2  => aux0,
      nq  => na3_x1_2_sig,
      vdd => vdd,
      vss => vss
   );

na3_x1_ins : na3_x1
   port map (
      i0  => na3_x1_2_sig,
      i1  => na2_x1_sig,
      i2  => nao22_x1_sig,
      nq  => na3_x1_sig,
      vdd => vdd,
      vss => vss
   );

rtlalc_0_0_ins : sff1_x4
   port map (
      ck  => cke,
      i   => na3_x1_sig,
      q   => rtlalc_0(0),
      vdd => vdd,
      vss => vss
   );

inv_x2_2_ins : inv_x2
   port map (
      i   => not_aux2,
      nq  => inv_x2_2_sig,
      vdd => vdd,
      vss => vss
   );

ao22_x2_2_ins : ao22_x2
   port map (
      i0  => not_i(2),
      i1  => accu(0),
      i2  => inv_x2_2_sig,
      q   => ao22_x2_2_sig,
      vdd => vdd,
      vss => vss
   );

nao22_x1_2_ins : nao22_x1
   port map (
      i0  => rtlalc_0(1),
      i1  => i(2),
      i2  => ao22_x2_2_sig,
      nq  => nao22_x1_2_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_2_ins : na2_x1
   port map (
      i0  => i(0),
      i1  => rtlalc_0(1),
      nq  => na2_x1_2_sig,
      vdd => vdd,
      vss => vss
   );

on12_x1_2_ins : on12_x1
   port map (
      i0  => not_i(2),
      i1  => alu_out(1),
      q   => on12_x1_2_sig,
      vdd => vdd,
      vss => vss
   );

na3_x1_4_ins : na3_x1
   port map (
      i0  => aux3,
      i1  => on12_x1_2_sig,
      i2  => aux1,
      nq  => na3_x1_4_sig,
      vdd => vdd,
      vss => vss
   );

na3_x1_3_ins : na3_x1
   port map (
      i0  => na3_x1_4_sig,
      i1  => na2_x1_2_sig,
      i2  => nao22_x1_2_sig,
      nq  => na3_x1_3_sig,
      vdd => vdd,
      vss => vss
   );

rtlalc_0_1_ins : sff1_x4
   port map (
      ck  => cke,
      i   => na3_x1_3_sig,
      q   => rtlalc_0(1),
      vdd => vdd,
      vss => vss
   );

an12_x1_ins : an12_x1
   port map (
      i0  => not_aux2,
      i1  => aux0,
      q   => an12_x1_sig,
      vdd => vdd,
      vss => vss
   );

nao22_x1_3_ins : nao22_x1
   port map (
      i0  => rtlalc_0(2),
      i1  => i(2),
      i2  => an12_x1_sig,
      nq  => nao22_x1_3_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_3_ins : na2_x1
   port map (
      i0  => i(0),
      i1  => rtlalc_0(2),
      nq  => na2_x1_3_sig,
      vdd => vdd,
      vss => vss
   );

on12_x1_3_ins : on12_x1
   port map (
      i0  => i(2),
      i1  => accu(3),
      q   => on12_x1_3_sig,
      vdd => vdd,
      vss => vss
   );

on12_x1_4_ins : on12_x1
   port map (
      i0  => not_i(2),
      i1  => alu_out(2),
      q   => on12_x1_4_sig,
      vdd => vdd,
      vss => vss
   );

na3_x1_6_ins : na3_x1
   port map (
      i0  => on12_x1_4_sig,
      i1  => on12_x1_3_sig,
      i2  => aux3,
      nq  => na3_x1_6_sig,
      vdd => vdd,
      vss => vss
   );

na3_x1_5_ins : na3_x1
   port map (
      i0  => na3_x1_6_sig,
      i1  => na2_x1_3_sig,
      i2  => nao22_x1_3_sig,
      nq  => na3_x1_5_sig,
      vdd => vdd,
      vss => vss
   );

rtlalc_0_2_ins : sff1_x4
   port map (
      ck  => cke,
      i   => na3_x1_5_sig,
      q   => rtlalc_0(2),
      vdd => vdd,
      vss => vss
   );

an12_x1_2_ins : an12_x1
   port map (
      i0  => not_aux2,
      i1  => aux1,
      q   => an12_x1_2_sig,
      vdd => vdd,
      vss => vss
   );

nao22_x1_4_ins : nao22_x1
   port map (
      i0  => rtlalc_0(3),
      i1  => i(2),
      i2  => an12_x1_2_sig,
      nq  => nao22_x1_4_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_4_ins : na2_x1
   port map (
      i0  => i(0),
      i1  => rtlalc_0(3),
      nq  => na2_x1_4_sig,
      vdd => vdd,
      vss => vss
   );

on12_x1_5_ins : on12_x1
   port map (
      i0  => i(2),
      i1  => q3_from,
      q   => on12_x1_5_sig,
      vdd => vdd,
      vss => vss
   );

on12_x1_6_ins : on12_x1
   port map (
      i0  => not_i(2),
      i1  => alu_out(3),
      q   => on12_x1_6_sig,
      vdd => vdd,
      vss => vss
   );

na3_x1_8_ins : na3_x1
   port map (
      i0  => on12_x1_6_sig,
      i1  => on12_x1_5_sig,
      i2  => aux3,
      nq  => na3_x1_8_sig,
      vdd => vdd,
      vss => vss
   );

na3_x1_7_ins : na3_x1
   port map (
      i0  => na3_x1_8_sig,
      i1  => na2_x1_4_sig,
      i2  => nao22_x1_4_sig,
      nq  => na3_x1_7_sig,
      vdd => vdd,
      vss => vss
   );

rtlalc_0_3_ins : sff1_x4
   port map (
      ck  => cke,
      i   => na3_x1_7_sig,
      q   => rtlalc_0(3),
      vdd => vdd,
      vss => vss
   );

accu_0_ins : buf_x2
   port map (
      i   => rtlalc_0(0),
      q   => accu(0),
      vdd => vdd,
      vss => vss
   );

accu_1_ins : buf_x2
   port map (
      i   => rtlalc_0(1),
      q   => accu(1),
      vdd => vdd,
      vss => vss
   );

accu_2_ins : buf_x2
   port map (
      i   => rtlalc_0(2),
      q   => accu(2),
      vdd => vdd,
      vss => vss
   );

accu_3_ins : buf_x2
   port map (
      i   => rtlalc_0(3),
      q   => accu(3),
      vdd => vdd,
      vss => vss
   );

no3_x1_ins : no3_x1
   port map (
      i0  => not_i(1),
      i1  => not_i(2),
      i2  => i(0),
      nq  => no3_x1_sig,
      vdd => vdd,
      vss => vss
   );

q3_to_ins : ts_x8
   port map (
      cmd => no3_x1_sig,
      i   => alu_out(3),
      q   => q3_to,
      vdd => vdd,
      vss => vss
   );

no3_x1_2_ins : no3_x1
   port map (
      i0  => i(1),
      i1  => not_i(2),
      i2  => i(0),
      nq  => no3_x1_2_sig,
      vdd => vdd,
      vss => vss
   );

q0_to_ins : ts_x8
   port map (
      cmd => no3_x1_2_sig,
      i   => alu_out(0),
      q   => q0_to,
      vdd => vdd,
      vss => vss
   );


end structural;