30 lines
673 B
Plaintext
30 lines
673 B
Plaintext
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-- =======================================================================
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-- Coriolis Structural VHDL Driver
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-- Generated on Dec 12, 2019, 11:42
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--
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-- To be interoperable with Alliance, it uses it's special VHDL subset.
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-- ("man vhdl" under Alliance for more informations)
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-- =======================================================================
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entity capacitor is
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port ( b0 : linkage bit
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; b1 : linkage bit
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; b2 : linkage bit
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; b3 : linkage bit
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; t0 : linkage bit
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; t1 : linkage bit
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; t2 : linkage bit
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; t3 : linkage bit
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);
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end capacitor;
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architecture structural of capacitor is
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begin
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end structural;
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