coriolis/documentation/examples/AM2901/alu.vst

entity alu is
   port (
      alu_out : inout   bit_vector(3 downto 0);
      cin     : in      bit;
      cout    : out     bit;
      i       : in      bit_vector(2 downto 0);
      ng      : out     bit;
      np      : out     bit;
      ovr     : out     bit;
      r       : in      bit_vector(3 downto 0);
      s       : in      bit_vector(3 downto 0);
      f3      : out     bit;
      vdd     : in      bit;
      vss     : in      bit;
      zero    : out     bit
 );
end alu;

architecture structural of alu is
Component oa2a2a23_x2
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      i3  : in      bit;
      i4  : in      bit;
      i5  : in      bit;
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component buf_x2
   port (
      i   : in      bit;
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component nmx2_x1
   port (
      cmd : in      bit;
      i0  : in      bit;
      i1  : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component noa2a2a2a24_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      i3  : in      bit;
      i4  : in      bit;
      i5  : in      bit;
      i6  : in      bit;
      i7  : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component an12_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component noa2ao222_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      i3  : in      bit;
      i4  : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component ao2o22_x2
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      i3  : in      bit;
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component a3_x2
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component noa2a2a23_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      i3  : in      bit;
      i4  : in      bit;
      i5  : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component oa22_x2
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component nxr2_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component a2_x2
   port (
      i0  : in      bit;
      i1  : in      bit;
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component o3_x2
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component noa22_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component na4_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      i3  : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component oa2a22_x2
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      i3  : in      bit;
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component xr2_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component oa2ao222_x2
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      i3  : in      bit;
      i4  : in      bit;
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component mx2_x2
   port (
      cmd : in      bit;
      i0  : in      bit;
      i1  : in      bit;
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component inv_x2
   port (
      i   : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component o2_x2
   port (
      i0  : in      bit;
      i1  : in      bit;
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component no4_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      i3  : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component on12_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component no2_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component no3_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component nao22_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component na2_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component ao22_x2
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component na3_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component a4_x2
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      i3  : in      bit;
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component nao2o22_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      i3  : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

Component mx3_x2
   port (
      cmd0 : in      bit;
      cmd1 : in      bit;
      i0   : in      bit;
      i1   : in      bit;
      i2   : in      bit;
      q    : out     bit;
      vdd  : in      bit;
      vss  : in      bit
 );
end component;

signal not_i              : bit_vector( 2 downto 0);
signal not_r              : bit_vector( 3 downto 0);
signal not_s              : bit_vector( 3 downto 0);
signal xr2_x1_sig         : bit;
signal xr2_x1_9_sig       : bit;
signal xr2_x1_8_sig       : bit;
signal xr2_x1_7_sig       : bit;
signal xr2_x1_6_sig       : bit;
signal xr2_x1_5_sig       : bit;
signal xr2_x1_4_sig       : bit;
signal xr2_x1_3_sig       : bit;
signal xr2_x1_2_sig       : bit;
signal xr2_x1_11_sig      : bit;
signal xr2_x1_10_sig      : bit;
signal on12_x1_sig        : bit;
signal on12_x1_7_sig      : bit;
signal on12_x1_6_sig      : bit;
signal on12_x1_5_sig      : bit;
signal on12_x1_4_sig      : bit;
signal on12_x1_3_sig      : bit;
signal on12_x1_2_sig      : bit;
signal oa2ao222_x2_sig    : bit;
signal oa2ao222_x2_2_sig  : bit;
signal oa2a2a23_x2_sig    : bit;
signal oa2a22_x2_sig      : bit;
signal oa2a22_x2_4_sig    : bit;
signal oa2a22_x2_3_sig    : bit;
signal oa2a22_x2_2_sig    : bit;
signal oa22_x2_sig        : bit;
signal oa22_x2_9_sig      : bit;
signal oa22_x2_8_sig      : bit;
signal oa22_x2_7_sig      : bit;
signal oa22_x2_6_sig      : bit;
signal oa22_x2_5_sig      : bit;
signal oa22_x2_4_sig      : bit;
signal oa22_x2_3_sig      : bit;
signal oa22_x2_2_sig      : bit;
signal o3_x2_sig          : bit;
signal o3_x2_9_sig        : bit;
signal o3_x2_8_sig        : bit;
signal o3_x2_7_sig        : bit;
signal o3_x2_6_sig        : bit;
signal o3_x2_5_sig        : bit;
signal o3_x2_4_sig        : bit;
signal o3_x2_3_sig        : bit;
signal o3_x2_2_sig        : bit;
signal o3_x2_11_sig       : bit;
signal o3_x2_10_sig       : bit;
signal o2_x2_sig          : bit;
signal o2_x2_9_sig        : bit;
signal o2_x2_8_sig        : bit;
signal o2_x2_7_sig        : bit;
signal o2_x2_6_sig        : bit;
signal o2_x2_5_sig        : bit;
signal o2_x2_4_sig        : bit;
signal o2_x2_3_sig        : bit;
signal o2_x2_2_sig        : bit;
signal o2_x2_17_sig       : bit;
signal o2_x2_16_sig       : bit;
signal o2_x2_15_sig       : bit;
signal o2_x2_14_sig       : bit;
signal o2_x2_13_sig       : bit;
signal o2_x2_12_sig       : bit;
signal o2_x2_11_sig       : bit;
signal o2_x2_10_sig       : bit;
signal nxr2_x1_sig        : bit;
signal nxr2_x1_2_sig      : bit;
signal not_cin            : bit;
signal not_aux99          : bit;
signal not_aux98          : bit;
signal not_aux97          : bit;
signal not_aux95          : bit;
signal not_aux92          : bit;
signal not_aux90          : bit;
signal not_aux86          : bit;
signal not_aux85          : bit;
signal not_aux84          : bit;
signal not_aux82          : bit;
signal not_aux80          : bit;
signal not_aux8           : bit;
signal not_aux79          : bit;
signal not_aux78          : bit;
signal not_aux75          : bit;
signal not_aux74          : bit;
signal not_aux73          : bit;
signal not_aux71          : bit;
signal not_aux70          : bit;
signal not_aux7           : bit;
signal not_aux68          : bit;
signal not_aux67          : bit;
signal not_aux66          : bit;
signal not_aux65          : bit;
signal not_aux64          : bit;
signal not_aux62          : bit;
signal not_aux61          : bit;
signal not_aux60          : bit;
signal not_aux58          : bit;
signal not_aux57          : bit;
signal not_aux55          : bit;
signal not_aux54          : bit;
signal not_aux53          : bit;
signal not_aux5           : bit;
signal not_aux47          : bit;
signal not_aux43          : bit;
signal not_aux40          : bit;
signal not_aux34          : bit;
signal not_aux30          : bit;
signal not_aux3           : bit;
signal not_aux28          : bit;
signal not_aux26          : bit;
signal not_aux22          : bit;
signal not_aux21          : bit;
signal not_aux2           : bit;
signal not_aux17          : bit;
signal not_aux16          : bit;
signal not_aux15          : bit;
signal not_aux134         : bit;
signal not_aux133         : bit;
signal not_aux132         : bit;
signal not_aux131         : bit;
signal not_aux130         : bit;
signal not_aux13          : bit;
signal not_aux129         : bit;
signal not_aux128         : bit;
signal not_aux127         : bit;
signal not_aux126         : bit;
signal not_aux124         : bit;
signal not_aux120         : bit;
signal not_aux117         : bit;
signal not_aux116         : bit;
signal not_aux115         : bit;
signal not_aux113         : bit;
signal not_aux112         : bit;
signal not_aux11          : bit;
signal not_aux109         : bit;
signal not_aux108         : bit;
signal not_aux107         : bit;
signal not_aux105         : bit;
signal not_aux104         : bit;
signal not_aux102         : bit;
signal not_aux101         : bit;
signal not_aux100         : bit;
signal not_aux10          : bit;
signal not_aux0           : bit;
signal noa2ao222_x1_sig   : bit;
signal noa2a2a2a24_x1_sig : bit;
signal noa2a2a23_x1_sig   : bit;
signal noa22_x1_sig       : bit;
signal noa22_x1_9_sig     : bit;
signal noa22_x1_8_sig     : bit;
signal noa22_x1_7_sig     : bit;
signal noa22_x1_6_sig     : bit;
signal noa22_x1_5_sig     : bit;
signal noa22_x1_4_sig     : bit;
signal noa22_x1_3_sig     : bit;
signal noa22_x1_2_sig     : bit;
signal noa22_x1_10_sig    : bit;
signal no4_x1_sig         : bit;
signal no4_x1_4_sig       : bit;
signal no4_x1_3_sig       : bit;
signal no4_x1_2_sig       : bit;
signal no3_x1_sig         : bit;
signal no3_x1_9_sig       : bit;
signal no3_x1_8_sig       : bit;
signal no3_x1_7_sig       : bit;
signal no3_x1_6_sig       : bit;
signal no3_x1_5_sig       : bit;
signal no3_x1_4_sig       : bit;
signal no3_x1_3_sig       : bit;
signal no3_x1_2_sig       : bit;
signal no3_x1_17_sig      : bit;
signal no3_x1_16_sig      : bit;
signal no3_x1_15_sig      : bit;
signal no3_x1_14_sig      : bit;
signal no3_x1_13_sig      : bit;
signal no3_x1_12_sig      : bit;
signal no3_x1_11_sig      : bit;
signal no3_x1_10_sig      : bit;
signal no2_x1_sig         : bit;
signal no2_x1_9_sig       : bit;
signal no2_x1_8_sig       : bit;
signal no2_x1_7_sig       : bit;
signal no2_x1_6_sig       : bit;
signal no2_x1_5_sig       : bit;
signal no2_x1_4_sig       : bit;
signal no2_x1_3_sig       : bit;
signal no2_x1_2_sig       : bit;
signal no2_x1_27_sig      : bit;
signal no2_x1_26_sig      : bit;
signal no2_x1_25_sig      : bit;
signal no2_x1_24_sig      : bit;
signal no2_x1_23_sig      : bit;
signal no2_x1_22_sig      : bit;
signal no2_x1_21_sig      : bit;
signal no2_x1_20_sig      : bit;
signal no2_x1_19_sig      : bit;
signal no2_x1_18_sig      : bit;
signal no2_x1_17_sig      : bit;
signal no2_x1_16_sig      : bit;
signal no2_x1_15_sig      : bit;
signal no2_x1_14_sig      : bit;
signal no2_x1_13_sig      : bit;
signal no2_x1_12_sig      : bit;
signal no2_x1_11_sig      : bit;
signal no2_x1_10_sig      : bit;
signal nmx2_x1_sig        : bit;
signal nao2o22_x1_sig     : bit;
signal nao2o22_x1_3_sig   : bit;
signal nao2o22_x1_2_sig   : bit;
signal nao22_x1_sig       : bit;
signal nao22_x1_9_sig     : bit;
signal nao22_x1_8_sig     : bit;
signal nao22_x1_7_sig     : bit;
signal nao22_x1_6_sig     : bit;
signal nao22_x1_5_sig     : bit;
signal nao22_x1_4_sig     : bit;
signal nao22_x1_3_sig     : bit;
signal nao22_x1_2_sig     : bit;
signal nao22_x1_25_sig    : bit;
signal nao22_x1_24_sig    : bit;
signal nao22_x1_23_sig    : bit;
signal nao22_x1_22_sig    : bit;
signal nao22_x1_21_sig    : bit;
signal nao22_x1_20_sig    : bit;
signal nao22_x1_19_sig    : bit;
signal nao22_x1_18_sig    : bit;
signal nao22_x1_17_sig    : bit;
signal nao22_x1_16_sig    : bit;
signal nao22_x1_15_sig    : bit;
signal nao22_x1_14_sig    : bit;
signal nao22_x1_13_sig    : bit;
signal nao22_x1_12_sig    : bit;
signal nao22_x1_11_sig    : bit;
signal nao22_x1_10_sig    : bit;
signal na4_x1_sig         : bit;
signal na4_x1_6_sig       : bit;
signal na4_x1_5_sig       : bit;
signal na4_x1_4_sig       : bit;
signal na4_x1_3_sig       : bit;
signal na4_x1_2_sig       : bit;
signal na3_x1_sig         : bit;
signal na3_x1_9_sig       : bit;
signal na3_x1_8_sig       : bit;
signal na3_x1_7_sig       : bit;
signal na3_x1_6_sig       : bit;
signal na3_x1_5_sig       : bit;
signal na3_x1_4_sig       : bit;
signal na3_x1_3_sig       : bit;
signal na3_x1_2_sig       : bit;
signal na3_x1_21_sig      : bit;
signal na3_x1_20_sig      : bit;
signal na3_x1_19_sig      : bit;
signal na3_x1_18_sig      : bit;
signal na3_x1_17_sig      : bit;
signal na3_x1_16_sig      : bit;
signal na3_x1_15_sig      : bit;
signal na3_x1_14_sig      : bit;
signal na3_x1_13_sig      : bit;
signal na3_x1_12_sig      : bit;
signal na3_x1_11_sig      : bit;
signal na3_x1_10_sig      : bit;
signal na2_x1_sig         : bit;
signal na2_x1_9_sig       : bit;
signal na2_x1_8_sig       : bit;
signal na2_x1_7_sig       : bit;
signal na2_x1_6_sig       : bit;
signal na2_x1_5_sig       : bit;
signal na2_x1_4_sig       : bit;
signal na2_x1_3_sig       : bit;
signal na2_x1_2_sig       : bit;
signal na2_x1_29_sig      : bit;
signal na2_x1_28_sig      : bit;
signal na2_x1_27_sig      : bit;
signal na2_x1_26_sig      : bit;
signal na2_x1_25_sig      : bit;
signal na2_x1_24_sig      : bit;
signal na2_x1_23_sig      : bit;
signal na2_x1_22_sig      : bit;
signal na2_x1_21_sig      : bit;
signal na2_x1_20_sig      : bit;
signal na2_x1_19_sig      : bit;
signal na2_x1_18_sig      : bit;
signal na2_x1_17_sig      : bit;
signal na2_x1_16_sig      : bit;
signal na2_x1_15_sig      : bit;
signal na2_x1_14_sig      : bit;
signal na2_x1_13_sig      : bit;
signal na2_x1_12_sig      : bit;
signal na2_x1_11_sig      : bit;
signal na2_x1_10_sig      : bit;
signal mx3_x2_sig         : bit;
signal mx3_x2_7_sig       : bit;
signal mx3_x2_6_sig       : bit;
signal mx3_x2_5_sig       : bit;
signal mx3_x2_4_sig       : bit;
signal mx3_x2_3_sig       : bit;
signal mx3_x2_2_sig       : bit;
signal mx2_x2_sig         : bit;
signal mx2_x2_2_sig       : bit;
signal inv_x2_sig         : bit;
signal inv_x2_9_sig       : bit;
signal inv_x2_8_sig       : bit;
signal inv_x2_7_sig       : bit;
signal inv_x2_6_sig       : bit;
signal inv_x2_5_sig       : bit;
signal inv_x2_4_sig       : bit;
signal inv_x2_3_sig       : bit;
signal inv_x2_2_sig       : bit;
signal inv_x2_18_sig      : bit;
signal inv_x2_17_sig      : bit;
signal inv_x2_16_sig      : bit;
signal inv_x2_15_sig      : bit;
signal inv_x2_14_sig      : bit;
signal inv_x2_13_sig      : bit;
signal inv_x2_12_sig      : bit;
signal inv_x2_11_sig      : bit;
signal inv_x2_10_sig      : bit;
signal aux97              : bit;
signal aux96              : bit;
signal aux90              : bit;
signal aux9               : bit;
signal aux87              : bit;
signal aux86              : bit;
signal aux83              : bit;
signal aux8               : bit;
signal aux76              : bit;
signal aux65              : bit;
signal aux58              : bit;
signal aux57              : bit;
signal aux56              : bit;
signal aux54              : bit;
signal aux49              : bit;
signal aux47              : bit;
signal aux43              : bit;
signal aux36              : bit;
signal aux30              : bit;
signal aux3               : bit;
signal aux28              : bit;
signal aux25              : bit;
signal aux21              : bit;
signal aux20              : bit;
signal aux2               : bit;
signal aux138             : bit;
signal aux137             : bit;
signal aux136             : bit;
signal aux135             : bit;
signal aux125             : bit;
signal aux122             : bit;
signal aux118             : bit;
signal aux11              : bit;
signal aux108             : bit;
signal aux106             : bit;
signal aux105             : bit;
signal aux10              : bit;
signal aux1               : bit;
signal ao2o22_x2_sig      : bit;
signal ao2o22_x2_3_sig    : bit;
signal ao2o22_x2_2_sig    : bit;
signal ao22_x2_sig        : bit;
signal ao22_x2_6_sig      : bit;
signal ao22_x2_5_sig      : bit;
signal ao22_x2_4_sig      : bit;
signal ao22_x2_3_sig      : bit;
signal ao22_x2_2_sig      : bit;
signal an12_x1_sig        : bit;
signal an12_x1_6_sig      : bit;
signal an12_x1_5_sig      : bit;
signal an12_x1_4_sig      : bit;
signal an12_x1_3_sig      : bit;
signal an12_x1_2_sig      : bit;
signal a4_x2_sig          : bit;
signal a4_x2_6_sig        : bit;
signal a4_x2_5_sig        : bit;
signal a4_x2_4_sig        : bit;
signal a4_x2_3_sig        : bit;
signal a4_x2_2_sig        : bit;
signal a3_x2_sig          : bit;
signal a3_x2_7_sig        : bit;
signal a3_x2_6_sig        : bit;
signal a3_x2_5_sig        : bit;
signal a3_x2_4_sig        : bit;
signal a3_x2_3_sig        : bit;
signal a3_x2_2_sig        : bit;
signal a2_x2_sig          : bit;
signal a2_x2_9_sig        : bit;
signal a2_x2_8_sig        : bit;
signal a2_x2_7_sig        : bit;
signal a2_x2_6_sig        : bit;
signal a2_x2_5_sig        : bit;
signal a2_x2_4_sig        : bit;
signal a2_x2_3_sig        : bit;
signal a2_x2_2_sig        : bit;
signal a2_x2_19_sig       : bit;
signal a2_x2_18_sig       : bit;
signal a2_x2_17_sig       : bit;
signal a2_x2_16_sig       : bit;
signal a2_x2_15_sig       : bit;
signal a2_x2_14_sig       : bit;
signal a2_x2_13_sig       : bit;
signal a2_x2_12_sig       : bit;
signal a2_x2_11_sig       : bit;
signal a2_x2_10_sig       : bit;

begin

not_aux126_ins : nxr2_x1
   port map (
      i0  => aux108,
      i1  => aux36,
      nq  => not_aux126,
      vdd => vdd,
      vss => vss
   );

not_aux128_ins : nxr2_x1
   port map (
      i0  => aux108,
      i1  => aux43,
      nq  => not_aux128,
      vdd => vdd,
      vss => vss
   );

not_aux129_ins : o2_x2
   port map (
      i0  => r(1),
      i1  => not_aux108,
      q   => not_aux129,
      vdd => vdd,
      vss => vss
   );

not_aux130_ins : na2_x1
   port map (
      i0  => r(1),
      i1  => not_aux108,
      nq  => not_aux130,
      vdd => vdd,
      vss => vss
   );

not_aux131_ins : nxr2_x1
   port map (
      i0  => aux49,
      i1  => aux108,
      nq  => not_aux131,
      vdd => vdd,
      vss => vss
   );

not_aux132_ins : nxr2_x1
   port map (
      i0  => aux108,
      i1  => aux30,
      nq  => not_aux132,
      vdd => vdd,
      vss => vss
   );

not_aux133_ins : a2_x2
   port map (
      i0  => not_aux22,
      i1  => not_aux60,
      q   => not_aux133,
      vdd => vdd,
      vss => vss
   );

not_aux127_ins : nxr2_x1
   port map (
      i0  => aux108,
      i1  => i(0),
      nq  => not_aux127,
      vdd => vdd,
      vss => vss
   );

nxr2_x1_ins : nxr2_x1
   port map (
      i0  => s(0),
      i1  => cin,
      nq  => nxr2_x1_sig,
      vdd => vdd,
      vss => vss
   );

not_aux124_ins : a2_x2
   port map (
      i0  => nxr2_x1_sig,
      i1  => not_i(0),
      q   => not_aux124,
      vdd => vdd,
      vss => vss
   );

not_aux115_ins : o2_x2
   port map (
      i0  => not_aux101,
      i1  => not_s(1),
      q   => not_aux115,
      vdd => vdd,
      vss => vss
   );

not_aux116_ins : o2_x2
   port map (
      i0  => not_aux102,
      i1  => not_s(2),
      q   => not_aux116,
      vdd => vdd,
      vss => vss
   );

not_aux117_ins : a2_x2
   port map (
      i0  => not_aux8,
      i1  => not_s(3),
      q   => not_aux117,
      vdd => vdd,
      vss => vss
   );

not_aux120_ins : a2_x2
   port map (
      i0  => not_aux64,
      i1  => not_aux57,
      q   => not_aux120,
      vdd => vdd,
      vss => vss
   );

not_aux104_ins : o2_x2
   port map (
      i0  => not_s(0),
      i1  => not_aux54,
      q   => not_aux104,
      vdd => vdd,
      vss => vss
   );

not_aux105_ins : inv_x2
   port map (
      i   => aux105,
      nq  => not_aux105,
      vdd => vdd,
      vss => vss
   );

not_aux107_ins : a2_x2
   port map (
      i0  => not_aux8,
      i1  => not_aux57,
      q   => not_aux107,
      vdd => vdd,
      vss => vss
   );

not_aux108_ins : inv_x2
   port map (
      i   => aux108,
      nq  => not_aux108,
      vdd => vdd,
      vss => vss
   );

not_aux109_ins : a2_x2
   port map (
      i0  => not_aux2,
      i1  => not_aux57,
      q   => not_aux109,
      vdd => vdd,
      vss => vss
   );

o2_x2_ins : o2_x2
   port map (
      i0  => not_aux10,
      i1  => not_i(0),
      q   => o2_x2_sig,
      vdd => vdd,
      vss => vss
   );

not_aux112_ins : oa22_x2
   port map (
      i0  => o2_x2_sig,
      i1  => not_s(3),
      i2  => aux8,
      q   => not_aux112,
      vdd => vdd,
      vss => vss
   );

not_aux113_ins : o2_x2
   port map (
      i0  => not_aux80,
      i1  => not_i(0),
      q   => not_aux113,
      vdd => vdd,
      vss => vss
   );

not_aux100_ins : na2_x1
   port map (
      i0  => not_aux55,
      i1  => not_s(3),
      nq  => not_aux100,
      vdd => vdd,
      vss => vss
   );

not_aux101_ins : nxr2_x1
   port map (
      i0  => i(0),
      i1  => r(1),
      nq  => not_aux101,
      vdd => vdd,
      vss => vss
   );

not_aux102_ins : nxr2_x1
   port map (
      i0  => i(0),
      i1  => r(2),
      nq  => not_aux102,
      vdd => vdd,
      vss => vss
   );

not_aux15_ins : nao22_x1
   port map (
      i0  => not_aux13,
      i1  => not_r(1),
      i2  => aux9,
      nq  => not_aux15,
      vdd => vdd,
      vss => vss
   );

not_aux7_ins : nao22_x1
   port map (
      i0  => not_aux5,
      i1  => r(1),
      i2  => aux1,
      nq  => not_aux7,
      vdd => vdd,
      vss => vss
   );

not_aux13_ins : nao22_x1
   port map (
      i0  => not_aux11,
      i1  => cin,
      i2  => aux10,
      nq  => not_aux13,
      vdd => vdd,
      vss => vss
   );

not_aux5_ins : nao22_x1
   port map (
      i0  => not_aux3,
      i1  => cin,
      i2  => aux2,
      nq  => not_aux5,
      vdd => vdd,
      vss => vss
   );

inv_x2_ins : inv_x2
   port map (
      i   => aux49,
      nq  => inv_x2_sig,
      vdd => vdd,
      vss => vss
   );

no4_x1_ins : no4_x1
   port map (
      i0  => not_r(1),
      i1  => r(3),
      i2  => inv_x2_sig,
      i3  => s(3),
      nq  => no4_x1_sig,
      vdd => vdd,
      vss => vss
   );

a4_x2_ins : a4_x2
   port map (
      i0  => not_r(1),
      i1  => r(3),
      i2  => s(3),
      i3  => not_aux43,
      q   => a4_x2_sig,
      vdd => vdd,
      vss => vss
   );

not_aux53_ins : no2_x1
   port map (
      i0  => a4_x2_sig,
      i1  => no4_x1_sig,
      nq  => not_aux53,
      vdd => vdd,
      vss => vss
   );

not_aux43_ins : inv_x2
   port map (
      i   => aux43,
      nq  => not_aux43,
      vdd => vdd,
      vss => vss
   );

not_aux47_ins : inv_x2
   port map (
      i   => aux47,
      nq  => not_aux47,
      vdd => vdd,
      vss => vss
   );

not_aux17_ins : o2_x2
   port map (
      i0  => s(3),
      i1  => not_aux16,
      q   => not_aux17,
      vdd => vdd,
      vss => vss
   );

inv_x2_2_ins : inv_x2
   port map (
      i   => aux36,
      nq  => inv_x2_2_sig,
      vdd => vdd,
      vss => vss
   );

no4_x1_2_ins : no4_x1
   port map (
      i0  => not_r(1),
      i1  => r(3),
      i2  => inv_x2_2_sig,
      i3  => not_s(3),
      nq  => no4_x1_2_sig,
      vdd => vdd,
      vss => vss
   );

a4_x2_2_ins : a4_x2
   port map (
      i0  => not_s(3),
      i1  => r(3),
      i2  => not_aux30,
      i3  => not_r(1),
      q   => a4_x2_2_sig,
      vdd => vdd,
      vss => vss
   );

not_aux40_ins : no2_x1
   port map (
      i0  => a4_x2_2_sig,
      i1  => no4_x1_2_sig,
      nq  => not_aux40,
      vdd => vdd,
      vss => vss
   );

not_aux30_ins : inv_x2
   port map (
      i   => aux30,
      nq  => not_aux30,
      vdd => vdd,
      vss => vss
   );

not_aux34_ins : o2_x2
   port map (
      i0  => not_aux28,
      i1  => not_i(0),
      q   => not_aux34,
      vdd => vdd,
      vss => vss
   );

not_aux26_ins : o2_x2
   port map (
      i0  => s(0),
      i1  => cin,
      q   => not_aux26,
      vdd => vdd,
      vss => vss
   );

not_aux22_ins : o2_x2
   port map (
      i0  => s(3),
      i1  => not_aux21,
      q   => not_aux22,
      vdd => vdd,
      vss => vss
   );

not_aux54_ins : inv_x2
   port map (
      i   => aux54,
      nq  => not_aux54,
      vdd => vdd,
      vss => vss
   );

not_aux28_ins : inv_x2
   port map (
      i   => aux28,
      nq  => not_aux28,
      vdd => vdd,
      vss => vss
   );

not_aux58_ins : inv_x2
   port map (
      i   => aux58,
      nq  => not_aux58,
      vdd => vdd,
      vss => vss
   );

not_aux62_ins : o2_x2
   port map (
      i0  => not_aux61,
      i1  => not_s(1),
      q   => not_aux62,
      vdd => vdd,
      vss => vss
   );

not_aux61_ins : xr2_x1
   port map (
      i0  => r(1),
      i1  => r(2),
      q   => not_aux61,
      vdd => vdd,
      vss => vss
   );

not_aux67_ins : o2_x2
   port map (
      i0  => not_aux66,
      i1  => not_r(2),
      q   => not_aux67,
      vdd => vdd,
      vss => vss
   );

not_aux134_ins : o2_x2
   port map (
      i0  => r(2),
      i1  => not_s(1),
      q   => not_aux134,
      vdd => vdd,
      vss => vss
   );

not_aux70_ins : no2_x1
   port map (
      i0  => not_aux64,
      i1  => not_r(1),
      nq  => not_aux70,
      vdd => vdd,
      vss => vss
   );

not_aux71_ins : na2_x1
   port map (
      i0  => r(3),
      i1  => not_aux64,
      nq  => not_aux71,
      vdd => vdd,
      vss => vss
   );

not_aux68_ins : o2_x2
   port map (
      i0  => s(3),
      i1  => not_r(3),
      q   => not_aux68,
      vdd => vdd,
      vss => vss
   );

not_aux79_ins : a2_x2
   port map (
      i0  => i(0),
      i1  => r(1),
      q   => not_aux79,
      vdd => vdd,
      vss => vss
   );

not_aux73_ins : o3_x2
   port map (
      i0  => r(3),
      i1  => not_aux64,
      i2  => not_s(3),
      q   => not_aux73,
      vdd => vdd,
      vss => vss
   );

not_aux74_ins : o2_x2
   port map (
      i0  => not_aux21,
      i1  => not_s(3),
      q   => not_aux74,
      vdd => vdd,
      vss => vss
   );

not_aux80_ins : no2_x1
   port map (
      i0  => r(3),
      i1  => s(3),
      nq  => not_aux80,
      vdd => vdd,
      vss => vss
   );

not_aux85_ins : na2_x1
   port map (
      i0  => i(0),
      i1  => s(3),
      nq  => not_aux85,
      vdd => vdd,
      vss => vss
   );

not_aux86_ins : inv_x2
   port map (
      i   => aux86,
      nq  => not_aux86,
      vdd => vdd,
      vss => vss
   );

not_aux78_ins : nao22_x1
   port map (
      i0  => not_r(0),
      i1  => cin,
      i2  => aux76,
      nq  => not_aux78,
      vdd => vdd,
      vss => vss
   );

not_aux90_ins : inv_x2
   port map (
      i   => aux90,
      nq  => not_aux90,
      vdd => vdd,
      vss => vss
   );

a3_x2_ins : a3_x2
   port map (
      i0  => not_r(1),
      i1  => not_aux95,
      i2  => aux96,
      q   => a3_x2_sig,
      vdd => vdd,
      vss => vss
   );

oa22_x2_ins : oa22_x2
   port map (
      i0  => not_aux57,
      i1  => not_aux16,
      i2  => a3_x2_sig,
      q   => oa22_x2_sig,
      vdd => vdd,
      vss => vss
   );

o2_x2_3_ins : o2_x2
   port map (
      i0  => not_aux95,
      i1  => not_r(1),
      q   => o2_x2_3_sig,
      vdd => vdd,
      vss => vss
   );

a3_x2_2_ins : a3_x2
   port map (
      i0  => r(2),
      i1  => aux96,
      i2  => o2_x2_3_sig,
      q   => a3_x2_2_sig,
      vdd => vdd,
      vss => vss
   );

no3_x1_ins : no3_x1
   port map (
      i0  => not_aux92,
      i1  => not_aux65,
      i2  => r(2),
      nq  => no3_x1_sig,
      vdd => vdd,
      vss => vss
   );

o2_x2_2_ins : o2_x2
   port map (
      i0  => no3_x1_sig,
      i1  => a3_x2_2_sig,
      q   => o2_x2_2_sig,
      vdd => vdd,
      vss => vss
   );

no3_x1_2_ins : no3_x1
   port map (
      i0  => not_r(1),
      i1  => not_aux92,
      i2  => not_aux64,
      nq  => no3_x1_2_sig,
      vdd => vdd,
      vss => vss
   );

oa22_x2_2_ins : oa22_x2
   port map (
      i0  => not_aux60,
      i1  => not_aux21,
      i2  => no3_x1_2_sig,
      q   => oa22_x2_2_sig,
      vdd => vdd,
      vss => vss
   );

oa2a2a23_x2_ins : oa2a2a23_x2
   port map (
      i0  => oa22_x2_2_sig,
      i1  => not_r(2),
      i2  => not_s(1),
      i3  => o2_x2_2_sig,
      i4  => oa22_x2_sig,
      i5  => r(2),
      q   => oa2a2a23_x2_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_ins : na2_x1
   port map (
      i0  => not_aux97,
      i1  => not_aux66,
      nq  => na2_x1_sig,
      vdd => vdd,
      vss => vss
   );

ao22_x2_2_ins : ao22_x2
   port map (
      i0  => not_aux82,
      i1  => not_r(0),
      i2  => aux76,
      q   => ao22_x2_2_sig,
      vdd => vdd,
      vss => vss
   );

ao22_x2_ins : ao22_x2
   port map (
      i0  => ao22_x2_2_sig,
      i1  => na2_x1_sig,
      i2  => not_r(2),
      q   => ao22_x2_sig,
      vdd => vdd,
      vss => vss
   );

inv_x2_3_ins : inv_x2
   port map (
      i   => aux87,
      nq  => inv_x2_3_sig,
      vdd => vdd,
      vss => vss
   );

na3_x1_2_ins : na3_x1
   port map (
      i0  => not_aux98,
      i1  => not_aux97,
      i2  => inv_x2_3_sig,
      nq  => na3_x1_2_sig,
      vdd => vdd,
      vss => vss
   );

a2_x2_ins : a2_x2
   port map (
      i0  => na3_x1_2_sig,
      i1  => r(2),
      q   => a2_x2_sig,
      vdd => vdd,
      vss => vss
   );

nao22_x1_ins : nao22_x1
   port map (
      i0  => a2_x2_sig,
      i1  => ao22_x2_sig,
      i2  => not_s(1),
      nq  => nao22_x1_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_3_ins : na2_x1
   port map (
      i0  => r(1),
      i1  => r(2),
      nq  => na2_x1_3_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_4_ins : na2_x1
   port map (
      i0  => i(0),
      i1  => not_s(3),
      nq  => na2_x1_4_sig,
      vdd => vdd,
      vss => vss
   );

oa22_x2_3_ins : oa22_x2
   port map (
      i0  => na2_x1_4_sig,
      i1  => not_aux64,
      i2  => na2_x1_3_sig,
      q   => oa22_x2_3_sig,
      vdd => vdd,
      vss => vss
   );

nao22_x1_2_ins : nao22_x1
   port map (
      i0  => not_aux95,
      i1  => aux56,
      i2  => aux137,
      nq  => nao22_x1_2_sig,
      vdd => vdd,
      vss => vss
   );

na3_x1_3_ins : na3_x1
   port map (
      i0  => not_aux97,
      i1  => nao22_x1_2_sig,
      i2  => oa22_x2_3_sig,
      nq  => na3_x1_3_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_2_ins : na2_x1
   port map (
      i0  => s(1),
      i1  => na3_x1_3_sig,
      nq  => na2_x1_2_sig,
      vdd => vdd,
      vss => vss
   );

na3_x1_ins : na3_x1
   port map (
      i0  => s(2),
      i1  => na2_x1_2_sig,
      i2  => nao22_x1_sig,
      nq  => na3_x1_sig,
      vdd => vdd,
      vss => vss
   );

not_aux99_ins : a2_x2
   port map (
      i0  => na3_x1_sig,
      i1  => oa2a2a23_x2_sig,
      q   => not_aux99,
      vdd => vdd,
      vss => vss
   );

not_aux21_ins : inv_x2
   port map (
      i   => aux21,
      nq  => not_aux21,
      vdd => vdd,
      vss => vss
   );

not_aux60_ins : na2_x1
   port map (
      i0  => r(3),
      i1  => s(3),
      nq  => not_aux60,
      vdd => vdd,
      vss => vss
   );

not_aux16_ins : na2_x1
   port map (
      i0  => i(0),
      i1  => r(3),
      nq  => not_aux16,
      vdd => vdd,
      vss => vss
   );

not_aux57_ins : inv_x2
   port map (
      i   => aux57,
      nq  => not_aux57,
      vdd => vdd,
      vss => vss
   );

not_aux92_ins : a2_x2
   port map (
      i0  => s(3),
      i1  => not_aux8,
      q   => not_aux92,
      vdd => vdd,
      vss => vss
   );

not_aux8_ins : inv_x2
   port map (
      i   => aux8,
      nq  => not_aux8,
      vdd => vdd,
      vss => vss
   );

not_aux65_ins : inv_x2
   port map (
      i   => aux65,
      nq  => not_aux65,
      vdd => vdd,
      vss => vss
   );

not_aux0_ins : o2_x2
   port map (
      i0  => r(3),
      i1  => not_i(0),
      q   => not_aux0,
      vdd => vdd,
      vss => vss
   );

not_aux66_ins : o2_x2
   port map (
      i0  => r(1),
      i1  => not_i(0),
      q   => not_aux66,
      vdd => vdd,
      vss => vss
   );

not_aux84_ins : na2_x1
   port map (
      i0  => not_aux75,
      i1  => not_i(0),
      nq  => not_aux84,
      vdd => vdd,
      vss => vss
   );

not_aux75_ins : o2_x2
   port map (
      i0  => cin,
      i1  => not_s(0),
      q   => not_aux75,
      vdd => vdd,
      vss => vss
   );

not_aux82_ins : a2_x2
   port map (
      i0  => cin,
      i1  => not_s(0),
      q   => not_aux82,
      vdd => vdd,
      vss => vss
   );

not_aux98_ins : o2_x2
   port map (
      i0  => i(0),
      i1  => not_r(1),
      q   => not_aux98,
      vdd => vdd,
      vss => vss
   );

not_aux95_ins : nao22_x1
   port map (
      i0  => not_aux11,
      i1  => not_cin,
      i2  => aux10,
      nq  => not_aux95,
      vdd => vdd,
      vss => vss
   );

not_aux10_ins : inv_x2
   port map (
      i   => aux10,
      nq  => not_aux10,
      vdd => vdd,
      vss => vss
   );

not_aux11_ins : inv_x2
   port map (
      i   => aux11,
      nq  => not_aux11,
      vdd => vdd,
      vss => vss
   );

not_aux64_ins : ao22_x2
   port map (
      i0  => not_aux3,
      i1  => not_cin,
      i2  => aux2,
      q   => not_aux64,
      vdd => vdd,
      vss => vss
   );

not_aux2_ins : inv_x2
   port map (
      i   => aux2,
      nq  => not_aux2,
      vdd => vdd,
      vss => vss
   );

not_aux3_ins : inv_x2
   port map (
      i   => aux3,
      nq  => not_aux3,
      vdd => vdd,
      vss => vss
   );

not_aux97_ins : inv_x2
   port map (
      i   => aux97,
      nq  => not_aux97,
      vdd => vdd,
      vss => vss
   );

not_aux55_ins : nxr2_x1
   port map (
      i0  => i(0),
      i1  => r(3),
      nq  => not_aux55,
      vdd => vdd,
      vss => vss
   );

not_cin_ins : inv_x2
   port map (
      i   => cin,
      nq  => not_cin,
      vdd => vdd,
      vss => vss
   );

not_i_2_ins : inv_x2
   port map (
      i   => i(2),
      nq  => not_i(2),
      vdd => vdd,
      vss => vss
   );

not_i_1_ins : inv_x2
   port map (
      i   => i(1),
      nq  => not_i(1),
      vdd => vdd,
      vss => vss
   );

not_i_0_ins : inv_x2
   port map (
      i   => i(0),
      nq  => not_i(0),
      vdd => vdd,
      vss => vss
   );

not_r_3_ins : inv_x2
   port map (
      i   => r(3),
      nq  => not_r(3),
      vdd => vdd,
      vss => vss
   );

not_r_2_ins : inv_x2
   port map (
      i   => r(2),
      nq  => not_r(2),
      vdd => vdd,
      vss => vss
   );

not_r_1_ins : inv_x2
   port map (
      i   => r(1),
      nq  => not_r(1),
      vdd => vdd,
      vss => vss
   );

not_r_0_ins : inv_x2
   port map (
      i   => r(0),
      nq  => not_r(0),
      vdd => vdd,
      vss => vss
   );

not_s_3_ins : inv_x2
   port map (
      i   => s(3),
      nq  => not_s(3),
      vdd => vdd,
      vss => vss
   );

not_s_2_ins : inv_x2
   port map (
      i   => s(2),
      nq  => not_s(2),
      vdd => vdd,
      vss => vss
   );

not_s_1_ins : inv_x2
   port map (
      i   => s(1),
      nq  => not_s(1),
      vdd => vdd,
      vss => vss
   );

not_s_0_ins : inv_x2
   port map (
      i   => s(0),
      nq  => not_s(0),
      vdd => vdd,
      vss => vss
   );

aux138_ins : na2_x1
   port map (
      i0  => r(2),
      i1  => not_s(1),
      nq  => aux138,
      vdd => vdd,
      vss => vss
   );

aux137_ins : no2_x1
   port map (
      i0  => r(1),
      i1  => r(2),
      nq  => aux137,
      vdd => vdd,
      vss => vss
   );

aux136_ins : no2_x1
   port map (
      i0  => r(2),
      i1  => not_r(1),
      nq  => aux136,
      vdd => vdd,
      vss => vss
   );

aux135_ins : a2_x2
   port map (
      i0  => r(2),
      i1  => not_r(1),
      q   => aux135,
      vdd => vdd,
      vss => vss
   );

aux125_ins : xr2_x1
   port map (
      i0  => r(1),
      i1  => s(1),
      q   => aux125,
      vdd => vdd,
      vss => vss
   );

aux122_ins : xr2_x1
   port map (
      i0  => aux54,
      i1  => s(0),
      q   => aux122,
      vdd => vdd,
      vss => vss
   );

aux118_ins : na2_x1
   port map (
      i0  => not_aux0,
      i1  => not_s(3),
      nq  => aux118,
      vdd => vdd,
      vss => vss
   );

aux108_ins : na2_x1
   port map (
      i0  => not_aux68,
      i1  => not_aux57,
      nq  => aux108,
      vdd => vdd,
      vss => vss
   );

aux106_ins : na2_x1
   port map (
      i0  => not_aux60,
      i1  => not_aux0,
      nq  => aux106,
      vdd => vdd,
      vss => vss
   );

aux105_ins : no2_x1
   port map (
      i0  => not_aux55,
      i1  => not_s(3),
      nq  => aux105,
      vdd => vdd,
      vss => vss
   );

aux97_ins : no2_x1
   port map (
      i0  => s(3),
      i1  => not_aux55,
      nq  => aux97,
      vdd => vdd,
      vss => vss
   );

aux96_ins : na2_x1
   port map (
      i0  => s(3),
      i1  => not_aux0,
      nq  => aux96,
      vdd => vdd,
      vss => vss
   );

a2_x2_2_ins : a2_x2
   port map (
      i0  => r(0),
      i1  => not_aux75,
      q   => a2_x2_2_sig,
      vdd => vdd,
      vss => vss
   );

aux90_ins : no3_x1
   port map (
      i0  => i(0),
      i1  => a2_x2_2_sig,
      i2  => not_aux82,
      nq  => aux90,
      vdd => vdd,
      vss => vss
   );

aux87_ins : an12_x1
   port map (
      i0  => not_aux84,
      i1  => aux83,
      q   => aux87,
      vdd => vdd,
      vss => vss
   );

aux86_ins : na2_x1
   port map (
      i0  => r(1),
      i1  => r(2),
      nq  => aux86,
      vdd => vdd,
      vss => vss
   );

aux83_ins : o2_x2
   port map (
      i0  => r(0),
      i1  => not_aux82,
      q   => aux83,
      vdd => vdd,
      vss => vss
   );

aux76_ins : a2_x2
   port map (
      i0  => i(0),
      i1  => not_aux75,
      q   => aux76,
      vdd => vdd,
      vss => vss
   );

aux65_ins : na2_x1
   port map (
      i0  => not_aux64,
      i1  => not_r(1),
      nq  => aux65,
      vdd => vdd,
      vss => vss
   );

aux58_ins : on12_x1
   port map (
      i0  => not_aux57,
      i1  => aux56,
      q   => aux58,
      vdd => vdd,
      vss => vss
   );

aux57_ins : no2_x1
   port map (
      i0  => r(3),
      i1  => not_s(3),
      nq  => aux57,
      vdd => vdd,
      vss => vss
   );

aux56_ins : no2_x1
   port map (
      i0  => i(0),
      i1  => s(3),
      nq  => aux56,
      vdd => vdd,
      vss => vss
   );

aux54_ins : xr2_x1
   port map (
      i0  => i(0),
      i1  => r(0),
      q   => aux54,
      vdd => vdd,
      vss => vss
   );

aux49_ins : ao22_x2
   port map (
      i0  => not_aux28,
      i1  => r(0),
      i2  => aux47,
      q   => aux49,
      vdd => vdd,
      vss => vss
   );

aux47_ins : a2_x2
   port map (
      i0  => not_aux26,
      i1  => not_i(0),
      q   => aux47,
      vdd => vdd,
      vss => vss
   );

na2_x1_5_ins : na2_x1
   port map (
      i0  => r(0),
      i1  => not_aux26,
      nq  => na2_x1_5_sig,
      vdd => vdd,
      vss => vss
   );

aux43_ins : na3_x1
   port map (
      i0  => not_i(0),
      i1  => na2_x1_5_sig,
      i2  => aux28,
      nq  => aux43,
      vdd => vdd,
      vss => vss
   );

aux36_ins : noa22_x1
   port map (
      i0  => not_r(0),
      i1  => not_aux26,
      i2  => not_aux34,
      nq  => aux36,
      vdd => vdd,
      vss => vss
   );

a2_x2_3_ins : a2_x2
   port map (
      i0  => i(0),
      i1  => not_aux26,
      q   => a2_x2_3_sig,
      vdd => vdd,
      vss => vss
   );

aux30_ins : nao22_x1
   port map (
      i0  => not_aux28,
      i1  => not_r(0),
      i2  => a2_x2_3_sig,
      nq  => aux30,
      vdd => vdd,
      vss => vss
   );

aux28_ins : na2_x1
   port map (
      i0  => s(0),
      i1  => cin,
      nq  => aux28,
      vdd => vdd,
      vss => vss
   );

aux25_ins : noa22_x1
   port map (
      i0  => not_r(1),
      i1  => not_aux13,
      i2  => not_aux22,
      nq  => aux25,
      vdd => vdd,
      vss => vss
   );

aux21_ins : no2_x1
   port map (
      i0  => i(0),
      i1  => r(3),
      nq  => aux21,
      vdd => vdd,
      vss => vss
   );

aux20_ins : noa22_x1
   port map (
      i0  => not_aux5,
      i1  => r(1),
      i2  => not_aux17,
      nq  => aux20,
      vdd => vdd,
      vss => vss
   );

aux11_ins : na2_x1
   port map (
      i0  => s(0),
      i1  => r(0),
      nq  => aux11,
      vdd => vdd,
      vss => vss
   );

aux10_ins : na2_x1
   port map (
      i0  => not_s(0),
      i1  => not_r(0),
      nq  => aux10,
      vdd => vdd,
      vss => vss
   );

aux9_ins : no2_x1
   port map (
      i0  => not_aux8,
      i1  => not_s(3),
      nq  => aux9,
      vdd => vdd,
      vss => vss
   );

aux8_ins : no2_x1
   port map (
      i0  => i(0),
      i1  => not_r(3),
      nq  => aux8,
      vdd => vdd,
      vss => vss
   );

aux3_ins : na2_x1
   port map (
      i0  => s(0),
      i1  => not_r(0),
      nq  => aux3,
      vdd => vdd,
      vss => vss
   );

aux2_ins : na2_x1
   port map (
      i0  => r(0),
      i1  => not_s(0),
      nq  => aux2,
      vdd => vdd,
      vss => vss
   );

aux1_ins : no2_x1
   port map (
      i0  => not_aux0,
      i1  => not_s(3),
      nq  => aux1,
      vdd => vdd,
      vss => vss
   );

zero_ins : no4_x1
   port map (
      i0  => alu_out(2),
      i1  => alu_out(3),
      i2  => alu_out(0),
      i3  => alu_out(1),
      nq  => zero,
      vdd => vdd,
      vss => vss
   );

f3_ins : buf_x2
   port map (
      i   => alu_out(3),
      q   => f3,
      vdd => vdd,
      vss => vss
   );

no3_x1_3_ins : no3_x1
   port map (
      i0  => not_r(3),
      i1  => s(3),
      i2  => not_aux86,
      nq  => no3_x1_3_sig,
      vdd => vdd,
      vss => vss
   );

a2_x2_4_ins : a2_x2
   port map (
      i0  => cin,
      i1  => not_r(0),
      q   => a2_x2_4_sig,
      vdd => vdd,
      vss => vss
   );

a2_x2_5_ins : a2_x2
   port map (
      i0  => r(0),
      i1  => not_i(0),
      q   => a2_x2_5_sig,
      vdd => vdd,
      vss => vss
   );

nao22_x1_3_ins : nao22_x1
   port map (
      i0  => a2_x2_5_sig,
      i1  => a2_x2_4_sig,
      i2  => no3_x1_3_sig,
      nq  => nao22_x1_3_sig,
      vdd => vdd,
      vss => vss
   );

no2_x1_ins : no2_x1
   port map (
      i0  => not_aux90,
      i1  => not_r(3),
      nq  => no2_x1_sig,
      vdd => vdd,
      vss => vss
   );

inv_x2_4_ins : inv_x2
   port map (
      i   => not_aux0,
      nq  => inv_x2_4_sig,
      vdd => vdd,
      vss => vss
   );

nao22_x1_4_ins : nao22_x1
   port map (
      i0  => inv_x2_4_sig,
      i1  => no2_x1_sig,
      i2  => not_s(3),
      nq  => nao22_x1_4_sig,
      vdd => vdd,
      vss => vss
   );

na4_x1_2_ins : na4_x1
   port map (
      i0  => s(3),
      i1  => not_r(3),
      i2  => not_aux86,
      i3  => aux87,
      nq  => na4_x1_2_sig,
      vdd => vdd,
      vss => vss
   );

na4_x1_ins : na4_x1
   port map (
      i0  => na4_x1_2_sig,
      i1  => not_aux78,
      i2  => nao22_x1_4_sig,
      i3  => nao22_x1_3_sig,
      nq  => na4_x1_sig,
      vdd => vdd,
      vss => vss
   );

o2_x2_4_ins : o2_x2
   port map (
      i0  => r(1),
      i1  => not_aux73,
      q   => o2_x2_4_sig,
      vdd => vdd,
      vss => vss
   );

o2_x2_5_ins : o2_x2
   port map (
      i0  => not_aux74,
      i1  => not_r(1),
      q   => o2_x2_5_sig,
      vdd => vdd,
      vss => vss
   );

oa22_x2_5_ins : oa22_x2
   port map (
      i0  => o2_x2_5_sig,
      i1  => o2_x2_4_sig,
      i2  => not_r(2),
      q   => oa22_x2_5_sig,
      vdd => vdd,
      vss => vss
   );

o3_x2_ins : o3_x2
   port map (
      i0  => cin,
      i1  => not_aux80,
      i2  => not_aux10,
      q   => o3_x2_sig,
      vdd => vdd,
      vss => vss
   );

on12_x1_ins : on12_x1
   port map (
      i0  => o3_x2_sig,
      i1  => not_i(0),
      q   => on12_x1_sig,
      vdd => vdd,
      vss => vss
   );

o3_x2_2_ins : o3_x2
   port map (
      i0  => not_aux68,
      i1  => r(2),
      i2  => not_aux79,
      q   => o3_x2_2_sig,
      vdd => vdd,
      vss => vss
   );

na3_x1_4_ins : na3_x1
   port map (
      i0  => o3_x2_2_sig,
      i1  => on12_x1_sig,
      i2  => oa22_x2_5_sig,
      nq  => na3_x1_4_sig,
      vdd => vdd,
      vss => vss
   );

inv_x2_5_ins : inv_x2
   port map (
      i   => aux83,
      nq  => inv_x2_5_sig,
      vdd => vdd,
      vss => vss
   );

noa22_x1_ins : noa22_x1
   port map (
      i0  => not_aux84,
      i1  => r(0),
      i2  => inv_x2_5_sig,
      nq  => noa22_x1_sig,
      vdd => vdd,
      vss => vss
   );

o2_x2_6_ins : o2_x2
   port map (
      i0  => s(3),
      i1  => not_r(3),
      q   => o2_x2_6_sig,
      vdd => vdd,
      vss => vss
   );

nao22_x1_5_ins : nao22_x1
   port map (
      i0  => o2_x2_6_sig,
      i1  => noa22_x1_sig,
      i2  => not_aux85,
      nq  => nao22_x1_5_sig,
      vdd => vdd,
      vss => vss
   );

oa22_x2_4_ins : oa22_x2
   port map (
      i0  => nao22_x1_5_sig,
      i1  => not_r(1),
      i2  => na3_x1_4_sig,
      q   => oa22_x2_4_sig,
      vdd => vdd,
      vss => vss
   );

o3_x2_3_ins : o3_x2
   port map (
      i0  => r(1),
      i1  => s(3),
      i2  => not_aux71,
      q   => o3_x2_3_sig,
      vdd => vdd,
      vss => vss
   );

o2_x2_7_ins : o2_x2
   port map (
      i0  => not_aux73,
      i1  => not_r(1),
      q   => o2_x2_7_sig,
      vdd => vdd,
      vss => vss
   );

na3_x1_5_ins : na3_x1
   port map (
      i0  => not_i(0),
      i1  => o2_x2_7_sig,
      i2  => o3_x2_3_sig,
      nq  => na3_x1_5_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_6_ins : na2_x1
   port map (
      i0  => not_r(2),
      i1  => na3_x1_5_sig,
      nq  => na2_x1_6_sig,
      vdd => vdd,
      vss => vss
   );

o2_x2_8_ins : o2_x2
   port map (
      i0  => s(3),
      i1  => not_aux0,
      q   => o2_x2_8_sig,
      vdd => vdd,
      vss => vss
   );

na3_x1_6_ins : na3_x1
   port map (
      i0  => not_aux74,
      i1  => not_aux78,
      i2  => o2_x2_8_sig,
      nq  => na3_x1_6_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_7_ins : na2_x1
   port map (
      i0  => r(2),
      i1  => na3_x1_6_sig,
      nq  => na2_x1_7_sig,
      vdd => vdd,
      vss => vss
   );

o3_x2_4_ins : o3_x2
   port map (
      i0  => not_aux134,
      i1  => not_aux68,
      i2  => not_aux70,
      q   => o3_x2_4_sig,
      vdd => vdd,
      vss => vss
   );

no3_x1_4_ins : no3_x1
   port map (
      i0  => not_aux65,
      i1  => not_aux57,
      i2  => r(2),
      nq  => no3_x1_4_sig,
      vdd => vdd,
      vss => vss
   );

inv_x2_6_ins : inv_x2
   port map (
      i   => not_aux67,
      nq  => inv_x2_6_sig,
      vdd => vdd,
      vss => vss
   );

nao22_x1_6_ins : nao22_x1
   port map (
      i0  => inv_x2_6_sig,
      i1  => no3_x1_4_sig,
      i2  => not_s(1),
      nq  => nao22_x1_6_sig,
      vdd => vdd,
      vss => vss
   );

na4_x1_3_ins : na4_x1
   port map (
      i0  => nao22_x1_6_sig,
      i1  => o3_x2_4_sig,
      i2  => na2_x1_7_sig,
      i3  => na2_x1_6_sig,
      nq  => na4_x1_3_sig,
      vdd => vdd,
      vss => vss
   );

mx3_x2_ins : mx3_x2
   port map (
      cmd0 => s(2),
      cmd1 => not_s(1),
      i0   => na4_x1_3_sig,
      i1   => oa22_x2_4_sig,
      i2   => na4_x1_sig,
      q    => mx3_x2_sig,
      vdd  => vdd,
      vss  => vss
   );

an12_x1_ins : an12_x1
   port map (
      i0  => r(2),
      i1  => aux25,
      q   => an12_x1_sig,
      vdd => vdd,
      vss => vss
   );

a2_x2_7_ins : a2_x2
   port map (
      i0  => r(2),
      i1  => aux20,
      q   => a2_x2_7_sig,
      vdd => vdd,
      vss => vss
   );

nao22_x1_7_ins : nao22_x1
   port map (
      i0  => a2_x2_7_sig,
      i1  => an12_x1_sig,
      i2  => s(1),
      nq  => nao22_x1_7_sig,
      vdd => vdd,
      vss => vss
   );

no2_x1_2_ins : no2_x1
   port map (
      i0  => not_aux7,
      i1  => not_r(2),
      nq  => no2_x1_2_sig,
      vdd => vdd,
      vss => vss
   );

no2_x1_3_ins : no2_x1
   port map (
      i0  => r(2),
      i1  => not_aux15,
      nq  => no2_x1_3_sig,
      vdd => vdd,
      vss => vss
   );

nao22_x1_8_ins : nao22_x1
   port map (
      i0  => no2_x1_3_sig,
      i1  => no2_x1_2_sig,
      i2  => not_s(1),
      nq  => nao22_x1_8_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_8_ins : na2_x1
   port map (
      i0  => not_aux22,
      i1  => not_aux40,
      nq  => na2_x1_8_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_9_ins : na2_x1
   port map (
      i0  => not_aux17,
      i1  => not_aux53,
      nq  => na2_x1_9_sig,
      vdd => vdd,
      vss => vss
   );

nmx2_x1_ins : nmx2_x1
   port map (
      cmd => r(2),
      i0  => na2_x1_9_sig,
      i1  => na2_x1_8_sig,
      nq  => nmx2_x1_sig,
      vdd => vdd,
      vss => vss
   );

na3_x1_7_ins : na3_x1
   port map (
      i0  => nmx2_x1_sig,
      i1  => nao22_x1_8_sig,
      i2  => nao22_x1_7_sig,
      nq  => na3_x1_7_sig,
      vdd => vdd,
      vss => vss
   );

a2_x2_6_ins : a2_x2
   port map (
      i0  => na3_x1_7_sig,
      i1  => s(2),
      q   => a2_x2_6_sig,
      vdd => vdd,
      vss => vss
   );

an12_x1_2_ins : an12_x1
   port map (
      i0  => aux9,
      i1  => not_aux40,
      q   => an12_x1_2_sig,
      vdd => vdd,
      vss => vss
   );

an12_x1_3_ins : an12_x1
   port map (
      i0  => aux1,
      i1  => not_aux53,
      q   => an12_x1_3_sig,
      vdd => vdd,
      vss => vss
   );

ao2o22_x2_ins : ao2o22_x2
   port map (
      i0  => not_r(2),
      i1  => an12_x1_3_sig,
      i2  => an12_x1_2_sig,
      i3  => r(2),
      q   => ao2o22_x2_sig,
      vdd => vdd,
      vss => vss
   );

no2_x1_4_ins : no2_x1
   port map (
      i0  => not_aux15,
      i1  => not_r(2),
      nq  => no2_x1_4_sig,
      vdd => vdd,
      vss => vss
   );

no2_x1_5_ins : no2_x1
   port map (
      i0  => r(2),
      i1  => not_aux7,
      nq  => no2_x1_5_sig,
      vdd => vdd,
      vss => vss
   );

nao22_x1_9_ins : nao22_x1
   port map (
      i0  => no2_x1_5_sig,
      i1  => no2_x1_4_sig,
      i2  => not_s(1),
      nq  => nao22_x1_9_sig,
      vdd => vdd,
      vss => vss
   );

a2_x2_9_ins : a2_x2
   port map (
      i0  => r(2),
      i1  => aux25,
      q   => a2_x2_9_sig,
      vdd => vdd,
      vss => vss
   );

an12_x1_4_ins : an12_x1
   port map (
      i0  => r(2),
      i1  => aux20,
      q   => an12_x1_4_sig,
      vdd => vdd,
      vss => vss
   );

nao22_x1_10_ins : nao22_x1
   port map (
      i0  => an12_x1_4_sig,
      i1  => a2_x2_9_sig,
      i2  => s(1),
      nq  => nao22_x1_10_sig,
      vdd => vdd,
      vss => vss
   );

na3_x1_8_ins : na3_x1
   port map (
      i0  => nao22_x1_10_sig,
      i1  => nao22_x1_9_sig,
      i2  => ao2o22_x2_sig,
      nq  => na3_x1_8_sig,
      vdd => vdd,
      vss => vss
   );

a2_x2_8_ins : a2_x2
   port map (
      i0  => na3_x1_8_sig,
      i1  => not_s(2),
      q   => a2_x2_8_sig,
      vdd => vdd,
      vss => vss
   );

no2_x1_6_ins : no2_x1
   port map (
      i0  => not_aux54,
      i1  => aux28,
      nq  => no2_x1_6_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_10_ins : na2_x1
   port map (
      i0  => cin,
      i1  => s(1),
      nq  => na2_x1_10_sig,
      vdd => vdd,
      vss => vss
   );

no2_x1_7_ins : no2_x1
   port map (
      i0  => r(1),
      i1  => not_aux58,
      nq  => no2_x1_7_sig,
      vdd => vdd,
      vss => vss
   );

a2_x2_10_ins : a2_x2
   port map (
      i0  => r(1),
      i1  => not_aux58,
      q   => a2_x2_10_sig,
      vdd => vdd,
      vss => vss
   );

no3_x1_5_ins : no3_x1
   port map (
      i0  => a2_x2_10_sig,
      i1  => no2_x1_7_sig,
      i2  => na2_x1_10_sig,
      nq  => no3_x1_5_sig,
      vdd => vdd,
      vss => vss
   );

no3_x1_6_ins : no3_x1
   port map (
      i0  => not_s(3),
      i1  => not_aux55,
      i2  => not_cin,
      nq  => no3_x1_6_sig,
      vdd => vdd,
      vss => vss
   );

no4_x1_3_ins : no4_x1
   port map (
      i0  => no3_x1_6_sig,
      i1  => not_i(2),
      i2  => no3_x1_5_sig,
      i3  => no2_x1_6_sig,
      nq  => no4_x1_3_sig,
      vdd => vdd,
      vss => vss
   );

na3_x1_9_ins : na3_x1
   port map (
      i0  => cin,
      i1  => s(2),
      i2  => not_aux62,
      nq  => na3_x1_9_sig,
      vdd => vdd,
      vss => vss
   );

xr2_x1_ins : xr2_x1
   port map (
      i0  => aux58,
      i1  => r(2),
      q   => xr2_x1_sig,
      vdd => vdd,
      vss => vss
   );

oa22_x2_6_ins : oa22_x2
   port map (
      i0  => xr2_x1_sig,
      i1  => not_s(1),
      i2  => na3_x1_9_sig,
      q   => oa22_x2_6_sig,
      vdd => vdd,
      vss => vss
   );

oa2ao222_x2_ins : oa2ao222_x2
   port map (
      i0  => oa22_x2_6_sig,
      i1  => no4_x1_3_sig,
      i2  => a2_x2_8_sig,
      i3  => a2_x2_6_sig,
      i4  => not_i(2),
      q   => oa2ao222_x2_sig,
      vdd => vdd,
      vss => vss
   );

ovr_ins : mx3_x2
   port map (
      cmd0 => i(1),
      cmd1 => not_i(2),
      i0   => oa2ao222_x2_sig,
      i1   => mx3_x2_sig,
      i2   => not_aux99,
      q    => ovr,
      vdd  => vdd,
      vss  => vss
   );

noa2a2a2a24_x1_ins : noa2a2a2a24_x1
   port map (
      i0  => s(1),
      i1  => not_aux101,
      i2  => not_aux54,
      i3  => s(0),
      i4  => s(3),
      i5  => not_aux55,
      i6  => not_aux102,
      i7  => s(2),
      nq  => noa2a2a2a24_x1_sig,
      vdd => vdd,
      vss => vss
   );

an12_x1_5_ins : an12_x1
   port map (
      i0  => noa2a2a2a24_x1_sig,
      i1  => i(1),
      q   => an12_x1_5_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_11_ins : na2_x1
   port map (
      i0  => s(1),
      i1  => not_r(1),
      nq  => na2_x1_11_sig,
      vdd => vdd,
      vss => vss
   );

na3_x1_10_ins : na3_x1
   port map (
      i0  => not_s(0),
      i1  => not_aux57,
      i2  => na2_x1_11_sig,
      nq  => na3_x1_10_sig,
      vdd => vdd,
      vss => vss
   );

a2_x2_11_ins : a2_x2
   port map (
      i0  => na3_x1_10_sig,
      i1  => not_i(0),
      q   => a2_x2_11_sig,
      vdd => vdd,
      vss => vss
   );

o3_x2_5_ins : o3_x2
   port map (
      i0  => i(0),
      i1  => r(2),
      i2  => not_s(2),
      q   => o3_x2_5_sig,
      vdd => vdd,
      vss => vss
   );

on12_x1_2_ins : on12_x1
   port map (
      i0  => o3_x2_5_sig,
      i1  => i(2),
      q   => on12_x1_2_sig,
      vdd => vdd,
      vss => vss
   );

no2_x1_8_ins : no2_x1
   port map (
      i0  => i(1),
      i1  => i(2),
      nq  => no2_x1_8_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_12_ins : na2_x1
   port map (
      i0  => not_aux101,
      i1  => not_s(1),
      nq  => na2_x1_12_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_13_ins : na2_x1
   port map (
      i0  => not_aux102,
      i1  => not_s(2),
      nq  => na2_x1_13_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_14_ins : na2_x1
   port map (
      i0  => not_s(0),
      i1  => not_aux54,
      nq  => na2_x1_14_sig,
      vdd => vdd,
      vss => vss
   );

na4_x1_4_ins : na4_x1
   port map (
      i0  => na2_x1_14_sig,
      i1  => not_aux100,
      i2  => na2_x1_13_sig,
      i3  => na2_x1_12_sig,
      nq  => na4_x1_4_sig,
      vdd => vdd,
      vss => vss
   );

np_ins : oa2ao222_x2
   port map (
      i0  => na4_x1_4_sig,
      i1  => no2_x1_8_sig,
      i2  => on12_x1_2_sig,
      i3  => a2_x2_11_sig,
      i4  => an12_x1_5_sig,
      q   => np,
      vdd => vdd,
      vss => vss
   );

a2_x2_12_ins : a2_x2
   port map (
      i0  => not_aux62,
      i1  => not_s(2),
      q   => a2_x2_12_sig,
      vdd => vdd,
      vss => vss
   );

o2_x2_9_ins : o2_x2
   port map (
      i0  => not_aux16,
      i1  => not_s(3),
      q   => o2_x2_9_sig,
      vdd => vdd,
      vss => vss
   );

oa22_x2_7_ins : oa22_x2
   port map (
      i0  => o2_x2_9_sig,
      i1  => a2_x2_12_sig,
      i2  => not_i(2),
      q   => oa22_x2_7_sig,
      vdd => vdd,
      vss => vss
   );

ao2o22_x2_2_ins : ao2o22_x2
   port map (
      i0  => r(2),
      i1  => not_aux60,
      i2  => not_aux113,
      i3  => not_r(2),
      q   => ao2o22_x2_2_sig,
      vdd => vdd,
      vss => vss
   );

an12_x1_6_ins : an12_x1
   port map (
      i0  => not_s(3),
      i1  => aux135,
      q   => an12_x1_6_sig,
      vdd => vdd,
      vss => vss
   );

inv_x2_7_ins : inv_x2
   port map (
      i   => aux136,
      nq  => inv_x2_7_sig,
      vdd => vdd,
      vss => vss
   );

noa22_x1_3_ins : noa22_x1
   port map (
      i0  => not_aux16,
      i1  => not_s(3),
      i2  => inv_x2_7_sig,
      nq  => noa22_x1_3_sig,
      vdd => vdd,
      vss => vss
   );

nao22_x1_11_ins : nao22_x1
   port map (
      i0  => noa22_x1_3_sig,
      i1  => an12_x1_6_sig,
      i2  => s(1),
      nq  => nao22_x1_11_sig,
      vdd => vdd,
      vss => vss
   );

noa22_x1_2_ins : noa22_x1
   port map (
      i0  => nao22_x1_11_sig,
      i1  => ao2o22_x2_2_sig,
      i2  => oa22_x2_7_sig,
      nq  => noa22_x1_2_sig,
      vdd => vdd,
      vss => vss
   );

on12_x1_3_ins : on12_x1
   port map (
      i0  => aux137,
      i1  => not_aux2,
      q   => on12_x1_3_sig,
      vdd => vdd,
      vss => vss
   );

o2_x2_10_ins : o2_x2
   port map (
      i0  => not_aux79,
      i1  => not_aux57,
      q   => o2_x2_10_sig,
      vdd => vdd,
      vss => vss
   );

na3_x1_12_ins : na3_x1
   port map (
      i0  => aux86,
      i1  => o2_x2_10_sig,
      i2  => on12_x1_3_sig,
      nq  => na3_x1_12_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_15_ins : na2_x1
   port map (
      i0  => not_s(1),
      i1  => na3_x1_12_sig,
      nq  => na2_x1_15_sig,
      vdd => vdd,
      vss => vss
   );

no2_x1_9_ins : no2_x1
   port map (
      i0  => not_aux112,
      i1  => not_r(2),
      nq  => no2_x1_9_sig,
      vdd => vdd,
      vss => vss
   );

o2_x2_11_ins : o2_x2
   port map (
      i0  => i(0),
      i1  => r(2),
      q   => o2_x2_11_sig,
      vdd => vdd,
      vss => vss
   );

noa22_x1_4_ins : noa22_x1
   port map (
      i0  => not_aux109,
      i1  => r(1),
      i2  => o2_x2_11_sig,
      nq  => noa22_x1_4_sig,
      vdd => vdd,
      vss => vss
   );

nao22_x1_12_ins : nao22_x1
   port map (
      i0  => noa22_x1_4_sig,
      i1  => no2_x1_9_sig,
      i2  => s(1),
      nq  => nao22_x1_12_sig,
      vdd => vdd,
      vss => vss
   );

na3_x1_11_ins : na3_x1
   port map (
      i0  => not_s(2),
      i1  => nao22_x1_12_sig,
      i2  => na2_x1_15_sig,
      nq  => na3_x1_11_sig,
      vdd => vdd,
      vss => vss
   );

o2_x2_12_ins : o2_x2
   port map (
      i0  => not_aux112,
      i1  => not_r(1),
      q   => o2_x2_12_sig,
      vdd => vdd,
      vss => vss
   );

o2_x2_13_ins : o2_x2
   port map (
      i0  => r(1),
      i1  => not_aux109,
      q   => o2_x2_13_sig,
      vdd => vdd,
      vss => vss
   );

a3_x2_4_ins : a3_x2
   port map (
      i0  => r(2),
      i1  => o2_x2_13_sig,
      i2  => o2_x2_12_sig,
      q   => a3_x2_4_sig,
      vdd => vdd,
      vss => vss
   );

inv_x2_8_ins : inv_x2
   port map (
      i   => not_aux66,
      nq  => inv_x2_8_sig,
      vdd => vdd,
      vss => vss
   );

nao22_x1_13_ins : nao22_x1
   port map (
      i0  => inv_x2_8_sig,
      i1  => a3_x2_4_sig,
      i2  => not_s(1),
      nq  => nao22_x1_13_sig,
      vdd => vdd,
      vss => vss
   );

no3_x1_8_ins : no3_x1
   port map (
      i0  => not_i(0),
      i1  => r(0),
      i2  => s(0),
      nq  => no3_x1_8_sig,
      vdd => vdd,
      vss => vss
   );

a4_x2_3_ins : a4_x2
   port map (
      i0  => not_aux2,
      i1  => not_aux86,
      i2  => not_aux108,
      i3  => not_aux16,
      q   => a4_x2_3_sig,
      vdd => vdd,
      vss => vss
   );

no3_x1_7_ins : no3_x1
   port map (
      i0  => aux97,
      i1  => a4_x2_3_sig,
      i2  => no3_x1_8_sig,
      nq  => no3_x1_7_sig,
      vdd => vdd,
      vss => vss
   );

a3_x2_3_ins : a3_x2
   port map (
      i0  => no3_x1_7_sig,
      i1  => nao22_x1_13_sig,
      i2  => na3_x1_11_sig,
      q   => a3_x2_3_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_16_ins : na2_x1
   port map (
      i0  => s(1),
      i1  => not_aux61,
      nq  => na2_x1_16_sig,
      vdd => vdd,
      vss => vss
   );

a4_x2_4_ins : a4_x2
   port map (
      i0  => aux3,
      i1  => i(0),
      i2  => not_aux57,
      i3  => r(2),
      q   => a4_x2_4_sig,
      vdd => vdd,
      vss => vss
   );

a4_x2_5_ins : a4_x2
   port map (
      i0  => not_r(2),
      i1  => not_i(0),
      i2  => not_aux60,
      i3  => aux11,
      q   => a4_x2_5_sig,
      vdd => vdd,
      vss => vss
   );

a3_x2_5_ins : a3_x2
   port map (
      i0  => not_aux104,
      i1  => not_aux105,
      i2  => not_s(2),
      q   => a3_x2_5_sig,
      vdd => vdd,
      vss => vss
   );

no3_x1_9_ins : no3_x1
   port map (
      i0  => not_s(0),
      i1  => not_s(3),
      i2  => r(0),
      nq  => no3_x1_9_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_17_ins : na2_x1
   port map (
      i0  => i(0),
      i1  => r(1),
      nq  => na2_x1_17_sig,
      vdd => vdd,
      vss => vss
   );

no2_x1_10_ins : no2_x1
   port map (
      i0  => na2_x1_17_sig,
      i1  => no3_x1_9_sig,
      nq  => no2_x1_10_sig,
      vdd => vdd,
      vss => vss
   );

no2_x1_11_ins : no2_x1
   port map (
      i0  => i(0),
      i1  => r(1),
      nq  => no2_x1_11_sig,
      vdd => vdd,
      vss => vss
   );

na3_x1_13_ins : na3_x1
   port map (
      i0  => r(0),
      i1  => s(0),
      i2  => s(3),
      nq  => na3_x1_13_sig,
      vdd => vdd,
      vss => vss
   );

a2_x2_13_ins : a2_x2
   port map (
      i0  => na3_x1_13_sig,
      i1  => no2_x1_11_sig,
      q   => a2_x2_13_sig,
      vdd => vdd,
      vss => vss
   );

o3_x2_6_ins : o3_x2
   port map (
      i0  => not_s(1),
      i1  => a2_x2_13_sig,
      i2  => no2_x1_10_sig,
      q   => o3_x2_6_sig,
      vdd => vdd,
      vss => vss
   );

noa2ao222_x1_ins : noa2ao222_x1
   port map (
      i0  => o3_x2_6_sig,
      i1  => a3_x2_5_sig,
      i2  => a4_x2_5_sig,
      i3  => a4_x2_4_sig,
      i4  => na2_x1_16_sig,
      nq  => noa2ao222_x1_sig,
      vdd => vdd,
      vss => vss
   );

a2_x2_14_ins : a2_x2
   port map (
      i0  => s(2),
      i1  => not_aux100,
      q   => a2_x2_14_sig,
      vdd => vdd,
      vss => vss
   );

o2_x2_14_ins : o2_x2
   port map (
      i0  => s(1),
      i1  => not_aux61,
      q   => o2_x2_14_sig,
      vdd => vdd,
      vss => vss
   );

oa22_x2_8_ins : oa22_x2
   port map (
      i0  => o2_x2_14_sig,
      i1  => a2_x2_14_sig,
      i2  => i(2),
      q   => oa22_x2_8_sig,
      vdd => vdd,
      vss => vss
   );

inv_x2_9_ins : inv_x2
   port map (
      i   => aux106,
      nq  => inv_x2_9_sig,
      vdd => vdd,
      vss => vss
   );

mx2_x2_ins : mx2_x2
   port map (
      cmd => r(2),
      i0  => inv_x2_9_sig,
      i1  => not_aux107,
      q   => mx2_x2_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_18_ins : na2_x1
   port map (
      i0  => s(3),
      i1  => not_aux16,
      nq  => na2_x1_18_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_19_ins : na2_x1
   port map (
      i0  => s(3),
      i1  => not_aux21,
      nq  => na2_x1_19_sig,
      vdd => vdd,
      vss => vss
   );

oa2a22_x2_ins : oa2a22_x2
   port map (
      i0  => aux135,
      i1  => na2_x1_19_sig,
      i2  => na2_x1_18_sig,
      i3  => aux136,
      q   => oa2a22_x2_sig,
      vdd => vdd,
      vss => vss
   );

noa22_x1_5_ins : noa22_x1
   port map (
      i0  => oa2a22_x2_sig,
      i1  => not_s(1),
      i2  => mx2_x2_sig,
      nq  => noa22_x1_5_sig,
      vdd => vdd,
      vss => vss
   );

nao22_x1_14_ins : nao22_x1
   port map (
      i0  => noa22_x1_5_sig,
      i1  => oa22_x2_8_sig,
      i2  => noa2ao222_x1_sig,
      nq  => nao22_x1_14_sig,
      vdd => vdd,
      vss => vss
   );

ng_ins : oa2ao222_x2
   port map (
      i0  => nao22_x1_14_sig,
      i1  => not_i(1),
      i2  => a3_x2_3_sig,
      i3  => noa22_x1_2_sig,
      i4  => i(1),
      q   => ng,
      vdd => vdd,
      vss => vss
   );

no2_x1_12_ins : no2_x1
   port map (
      i0  => not_aux99,
      i1  => not_i(2),
      nq  => no2_x1_12_sig,
      vdd => vdd,
      vss => vss
   );

noa22_x1_7_ins : noa22_x1
   port map (
      i0  => not_aux120,
      i1  => not_r(1),
      i2  => not_r(2),
      nq  => noa22_x1_7_sig,
      vdd => vdd,
      vss => vss
   );

no2_x1_13_ins : no2_x1
   port map (
      i0  => r(2),
      i1  => not_aux66,
      nq  => no2_x1_13_sig,
      vdd => vdd,
      vss => vss
   );

nao22_x1_15_ins : nao22_x1
   port map (
      i0  => no2_x1_13_sig,
      i1  => noa22_x1_7_sig,
      i2  => not_s(1),
      nq  => nao22_x1_15_sig,
      vdd => vdd,
      vss => vss
   );

no2_x1_14_ins : no2_x1
   port map (
      i0  => not_aux120,
      i1  => not_r(1),
      nq  => no2_x1_14_sig,
      vdd => vdd,
      vss => vss
   );

nao22_x1_16_ins : nao22_x1
   port map (
      i0  => i(0),
      i1  => no2_x1_14_sig,
      i2  => r(2),
      nq  => nao22_x1_16_sig,
      vdd => vdd,
      vss => vss
   );

a3_x2_6_ins : a3_x2
   port map (
      i0  => not_aux97,
      i1  => s(2),
      i2  => not_aux78,
      q   => a3_x2_6_sig,
      vdd => vdd,
      vss => vss
   );

na3_x1_14_ins : na3_x1
   port map (
      i0  => a3_x2_6_sig,
      i1  => nao22_x1_16_sig,
      i2  => nao22_x1_15_sig,
      nq  => na3_x1_14_sig,
      vdd => vdd,
      vss => vss
   );

on12_x1_4_ins : on12_x1
   port map (
      i0  => na3_x1_14_sig,
      i1  => i(2),
      q   => on12_x1_4_sig,
      vdd => vdd,
      vss => vss
   );

no3_x1_10_ins : no3_x1
   port map (
      i0  => aux57,
      i1  => not_aux64,
      i2  => not_r(1),
      nq  => no3_x1_10_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_20_ins : na2_x1
   port map (
      i0  => not_aux68,
      i1  => not_i(0),
      nq  => na2_x1_20_sig,
      vdd => vdd,
      vss => vss
   );

nao22_x1_17_ins : nao22_x1
   port map (
      i0  => na2_x1_20_sig,
      i1  => no3_x1_10_sig,
      i2  => not_r(2),
      nq  => nao22_x1_17_sig,
      vdd => vdd,
      vss => vss
   );

o3_x2_7_ins : o3_x2
   port map (
      i0  => cin,
      i1  => not_aux10,
      i2  => not_i(0),
      q   => o3_x2_7_sig,
      vdd => vdd,
      vss => vss
   );

noa22_x1_8_ins : noa22_x1
   port map (
      i0  => o3_x2_7_sig,
      i1  => not_aux21,
      i2  => not_aux80,
      nq  => noa22_x1_8_sig,
      vdd => vdd,
      vss => vss
   );

na3_x1_15_ins : na3_x1
   port map (
      i0  => not_r(2),
      i1  => not_aux57,
      i2  => aux65,
      nq  => na3_x1_15_sig,
      vdd => vdd,
      vss => vss
   );

a2_x2_15_ins : a2_x2
   port map (
      i0  => na3_x1_15_sig,
      i1  => not_aux67,
      q   => a2_x2_15_sig,
      vdd => vdd,
      vss => vss
   );

ao2o22_x2_3_ins : ao2o22_x2
   port map (
      i0  => s(1),
      i1  => a2_x2_15_sig,
      i2  => noa22_x1_8_sig,
      i3  => not_r(2),
      q   => ao2o22_x2_3_sig,
      vdd => vdd,
      vss => vss
   );

noa22_x1_6_ins : noa22_x1
   port map (
      i0  => ao2o22_x2_3_sig,
      i1  => nao22_x1_17_sig,
      i2  => on12_x1_4_sig,
      nq  => noa22_x1_6_sig,
      vdd => vdd,
      vss => vss
   );

na4_x1_5_ins : na4_x1
   port map (
      i0  => not_aux116,
      i1  => not_aux104,
      i2  => not_aux115,
      i3  => not_cin,
      nq  => na4_x1_5_sig,
      vdd => vdd,
      vss => vss
   );

ao22_x2_3_ins : ao22_x2
   port map (
      i0  => aux105,
      i1  => na4_x1_5_sig,
      i2  => not_i(1),
      q   => ao22_x2_3_sig,
      vdd => vdd,
      vss => vss
   );

a2_x2_16_ins : a2_x2
   port map (
      i0  => s(3),
      i1  => not_i(0),
      q   => a2_x2_16_sig,
      vdd => vdd,
      vss => vss
   );

nao22_x1_19_ins : nao22_x1
   port map (
      i0  => a2_x2_16_sig,
      i1  => aux2,
      i2  => aux137,
      nq  => nao22_x1_19_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_22_ins : na2_x1
   port map (
      i0  => not_aux85,
      i1  => not_aux10,
      nq  => na2_x1_22_sig,
      vdd => vdd,
      vss => vss
   );

na3_x1_17_ins : na3_x1
   port map (
      i0  => r(1),
      i1  => r(2),
      i2  => na2_x1_22_sig,
      nq  => na3_x1_17_sig,
      vdd => vdd,
      vss => vss
   );

na3_x1_16_ins : na3_x1
   port map (
      i0  => not_aux105,
      i1  => na3_x1_17_sig,
      i2  => nao22_x1_19_sig,
      nq  => na3_x1_16_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_21_ins : na2_x1
   port map (
      i0  => not_s(1),
      i1  => na3_x1_16_sig,
      nq  => na2_x1_21_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_23_ins : na2_x1
   port map (
      i0  => not_aux105,
      i1  => not_aux66,
      nq  => na2_x1_23_sig,
      vdd => vdd,
      vss => vss
   );

no2_x1_15_ins : no2_x1
   port map (
      i0  => not_aux2,
      i1  => not_i(0),
      nq  => no2_x1_15_sig,
      vdd => vdd,
      vss => vss
   );

ao22_x2_4_ins : ao22_x2
   port map (
      i0  => no2_x1_15_sig,
      i1  => na2_x1_23_sig,
      i2  => not_r(2),
      q   => ao22_x2_4_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_24_ins : na2_x1
   port map (
      i0  => not_aux98,
      i1  => not_aux105,
      nq  => na2_x1_24_sig,
      vdd => vdd,
      vss => vss
   );

no2_x1_16_ins : no2_x1
   port map (
      i0  => i(0),
      i1  => not_aux10,
      nq  => no2_x1_16_sig,
      vdd => vdd,
      vss => vss
   );

ao22_x2_5_ins : ao22_x2
   port map (
      i0  => no2_x1_16_sig,
      i1  => na2_x1_24_sig,
      i2  => r(2),
      q   => ao22_x2_5_sig,
      vdd => vdd,
      vss => vss
   );

nao22_x1_20_ins : nao22_x1
   port map (
      i0  => ao22_x2_5_sig,
      i1  => ao22_x2_4_sig,
      i2  => s(1),
      nq  => nao22_x1_20_sig,
      vdd => vdd,
      vss => vss
   );

a3_x2_7_ins : a3_x2
   port map (
      i0  => not_s(2),
      i1  => nao22_x1_20_sig,
      i2  => na2_x1_21_sig,
      q   => a3_x2_7_sig,
      vdd => vdd,
      vss => vss
   );

inv_x2_10_ins : inv_x2
   port map (
      i   => aux118,
      nq  => inv_x2_10_sig,
      vdd => vdd,
      vss => vss
   );

o3_x2_8_ins : o3_x2
   port map (
      i0  => r(1),
      i1  => not_aux2,
      i2  => inv_x2_10_sig,
      q   => o3_x2_8_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_25_ins : na2_x1
   port map (
      i0  => not_aux107,
      i1  => o3_x2_8_sig,
      nq  => na2_x1_25_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_26_ins : na2_x1
   port map (
      i0  => r(1),
      i1  => not_aux2,
      nq  => na2_x1_26_sig,
      vdd => vdd,
      vss => vss
   );

na3_x1_18_ins : na3_x1
   port map (
      i0  => r(2),
      i1  => na2_x1_26_sig,
      i2  => aux118,
      nq  => na3_x1_18_sig,
      vdd => vdd,
      vss => vss
   );

o2_x2_15_ins : o2_x2
   port map (
      i0  => r(2),
      i1  => not_aux117,
      q   => o2_x2_15_sig,
      vdd => vdd,
      vss => vss
   );

a2_x2_17_ins : a2_x2
   port map (
      i0  => not_aux10,
      i1  => not_r(1),
      q   => a2_x2_17_sig,
      vdd => vdd,
      vss => vss
   );

nao22_x1_21_ins : nao22_x1
   port map (
      i0  => a2_x2_17_sig,
      i1  => o2_x2_15_sig,
      i2  => na3_x1_18_sig,
      nq  => nao22_x1_21_sig,
      vdd => vdd,
      vss => vss
   );

o3_x2_9_ins : o3_x2
   port map (
      i0  => not_aux117,
      i1  => not_aux10,
      i2  => not_r(1),
      q   => o3_x2_9_sig,
      vdd => vdd,
      vss => vss
   );

on12_x1_5_ins : on12_x1
   port map (
      i0  => o3_x2_9_sig,
      i1  => aux106,
      q   => on12_x1_5_sig,
      vdd => vdd,
      vss => vss
   );

noa2a2a23_x1_ins : noa2a2a23_x1
   port map (
      i0  => on12_x1_5_sig,
      i1  => not_r(2),
      i2  => s(1),
      i3  => nao22_x1_21_sig,
      i4  => na2_x1_25_sig,
      i5  => r(2),
      nq  => noa2a2a23_x1_sig,
      vdd => vdd,
      vss => vss
   );

nao22_x1_18_ins : nao22_x1
   port map (
      i0  => noa2a2a23_x1_sig,
      i1  => a3_x2_7_sig,
      i2  => not_i(2),
      nq  => nao22_x1_18_sig,
      vdd => vdd,
      vss => vss
   );

cout_ins : oa2ao222_x2
   port map (
      i0  => nao22_x1_18_sig,
      i1  => ao22_x2_3_sig,
      i2  => noa22_x1_6_sig,
      i3  => no2_x1_12_sig,
      i4  => i(1),
      q   => cout,
      vdd => vdd,
      vss => vss
   );

inv_x2_11_ins : inv_x2
   port map (
      i   => not_aux104,
      nq  => inv_x2_11_sig,
      vdd => vdd,
      vss => vss
   );

xr2_x1_2_ins : xr2_x1
   port map (
      i0  => aux122,
      i1  => cin,
      q   => xr2_x1_2_sig,
      vdd => vdd,
      vss => vss
   );

inv_x2_12_ins : inv_x2
   port map (
      i   => not_aux124,
      nq  => inv_x2_12_sig,
      vdd => vdd,
      vss => vss
   );

oa22_x2_9_ins : oa22_x2
   port map (
      i0  => i(0),
      i1  => s(0),
      i2  => not_aux124,
      q   => oa22_x2_9_sig,
      vdd => vdd,
      vss => vss
   );

mx3_x2_2_ins : mx3_x2
   port map (
      cmd0 => not_i(2),
      cmd1 => not_r(0),
      i0   => aux122,
      i1   => oa22_x2_9_sig,
      i2   => inv_x2_12_sig,
      q    => mx3_x2_2_sig,
      vdd  => vdd,
      vss  => vss
   );

alu_out_0_ins : mx3_x2
   port map (
      cmd0 => not_i(1),
      cmd1 => not_i(2),
      i0   => mx3_x2_2_sig,
      i1   => xr2_x1_2_sig,
      i2   => inv_x2_11_sig,
      q    => alu_out(0),
      vdd  => vdd,
      vss  => vss
   );

xr2_x1_3_ins : xr2_x1
   port map (
      i0  => aux125,
      i1  => i(0),
      q   => xr2_x1_3_sig,
      vdd => vdd,
      vss => vss
   );

o2_x2_16_ins : o2_x2
   port map (
      i0  => r(1),
      i1  => not_aux64,
      q   => o2_x2_16_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_27_ins : na2_x1
   port map (
      i0  => r(1),
      i1  => not_aux64,
      nq  => na2_x1_27_sig,
      vdd => vdd,
      vss => vss
   );

na3_x1_19_ins : na3_x1
   port map (
      i0  => not_i(0),
      i1  => na2_x1_27_sig,
      i2  => o2_x2_16_sig,
      nq  => na3_x1_19_sig,
      vdd => vdd,
      vss => vss
   );

xr2_x1_4_ins : xr2_x1
   port map (
      i0  => aux90,
      i1  => r(1),
      q   => xr2_x1_4_sig,
      vdd => vdd,
      vss => vss
   );

oa2a22_x2_2_ins : oa2a22_x2
   port map (
      i0  => not_s(1),
      i1  => xr2_x1_4_sig,
      i2  => na3_x1_19_sig,
      i3  => s(1),
      q   => oa2a22_x2_2_sig,
      vdd => vdd,
      vss => vss
   );

no2_x1_17_ins : no2_x1
   port map (
      i0  => not_aux26,
      i1  => not_i(0),
      nq  => no2_x1_17_sig,
      vdd => vdd,
      vss => vss
   );

a2_x2_18_ins : a2_x2
   port map (
      i0  => not_aux28,
      i1  => not_i(0),
      q   => a2_x2_18_sig,
      vdd => vdd,
      vss => vss
   );

no3_x1_11_ins : no3_x1
   port map (
      i0  => a2_x2_18_sig,
      i1  => no2_x1_17_sig,
      i2  => r(0),
      nq  => no3_x1_11_sig,
      vdd => vdd,
      vss => vss
   );

noa22_x1_9_ins : noa22_x1
   port map (
      i0  => not_aux47,
      i1  => not_aux34,
      i2  => no3_x1_11_sig,
      nq  => noa22_x1_9_sig,
      vdd => vdd,
      vss => vss
   );

nxr2_x1_2_ins : nxr2_x1
   port map (
      i0  => noa22_x1_9_sig,
      i1  => aux125,
      nq  => nxr2_x1_2_sig,
      vdd => vdd,
      vss => vss
   );

nao2o22_x1_ins : nao2o22_x1
   port map (
      i0  => i(2),
      i1  => nxr2_x1_2_sig,
      i2  => not_aux115,
      i3  => not_i(2),
      nq  => nao2o22_x1_sig,
      vdd => vdd,
      vss => vss
   );

alu_out_1_ins : mx3_x2
   port map (
      cmd0 => i(1),
      cmd1 => not_i(2),
      i0   => nao2o22_x1_sig,
      i1   => oa2a22_x2_2_sig,
      i2   => xr2_x1_3_sig,
      q    => alu_out(1),
      vdd  => vdd,
      vss  => vss
   );

inv_x2_13_ins : inv_x2
   port map (
      i   => not_aux116,
      nq  => inv_x2_13_sig,
      vdd => vdd,
      vss => vss
   );

no2_x1_19_ins : no2_x1
   port map (
      i0  => not_aux34,
      i1  => not_r(0),
      nq  => no2_x1_19_sig,
      vdd => vdd,
      vss => vss
   );

no2_x1_20_ins : no2_x1
   port map (
      i0  => r(0),
      i1  => not_aux26,
      nq  => no2_x1_20_sig,
      vdd => vdd,
      vss => vss
   );

no3_x1_12_ins : no3_x1
   port map (
      i0  => no2_x1_20_sig,
      i1  => no2_x1_19_sig,
      i2  => r(1),
      nq  => no3_x1_12_sig,
      vdd => vdd,
      vss => vss
   );

no2_x1_18_ins : no2_x1
   port map (
      i0  => not_aux43,
      i1  => no3_x1_12_sig,
      nq  => no2_x1_18_sig,
      vdd => vdd,
      vss => vss
   );

xr2_x1_6_ins : xr2_x1
   port map (
      i0  => no2_x1_18_sig,
      i1  => r(2),
      q   => xr2_x1_6_sig,
      vdd => vdd,
      vss => vss
   );

no2_x1_22_ins : no2_x1
   port map (
      i0  => not_aux47,
      i1  => not_r(0),
      nq  => no2_x1_22_sig,
      vdd => vdd,
      vss => vss
   );

a2_x2_19_ins : a2_x2
   port map (
      i0  => not_aux28,
      i1  => not_r(0),
      q   => a2_x2_19_sig,
      vdd => vdd,
      vss => vss
   );

no3_x1_13_ins : no3_x1
   port map (
      i0  => a2_x2_19_sig,
      i1  => no2_x1_22_sig,
      i2  => r(1),
      nq  => no3_x1_13_sig,
      vdd => vdd,
      vss => vss
   );

no2_x1_21_ins : no2_x1
   port map (
      i0  => not_aux30,
      i1  => no3_x1_13_sig,
      nq  => no2_x1_21_sig,
      vdd => vdd,
      vss => vss
   );

xr2_x1_7_ins : xr2_x1
   port map (
      i0  => no2_x1_21_sig,
      i1  => r(2),
      q   => xr2_x1_7_sig,
      vdd => vdd,
      vss => vss
   );

oa2a22_x2_3_ins : oa2a22_x2
   port map (
      i0  => s(1),
      i1  => xr2_x1_7_sig,
      i2  => xr2_x1_6_sig,
      i3  => not_s(1),
      q   => oa2a22_x2_3_sig,
      vdd => vdd,
      vss => vss
   );

xr2_x1_5_ins : xr2_x1
   port map (
      i0  => oa2a22_x2_3_sig,
      i1  => s(2),
      q   => xr2_x1_5_sig,
      vdd => vdd,
      vss => vss
   );

o3_x2_10_ins : o3_x2
   port map (
      i0  => not_s(1),
      i1  => not_aux70,
      i2  => not_r(2),
      q   => o3_x2_10_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_28_ins : na2_x1
   port map (
      i0  => not_aux70,
      i1  => not_r(2),
      nq  => na2_x1_28_sig,
      vdd => vdd,
      vss => vss
   );

o3_x2_11_ins : o3_x2
   port map (
      i0  => s(1),
      i1  => r(2),
      i2  => not_aux65,
      q   => o3_x2_11_sig,
      vdd => vdd,
      vss => vss
   );

noa22_x1_10_ins : noa22_x1
   port map (
      i0  => not_aux65,
      i1  => r(2),
      i2  => i(0),
      nq  => noa22_x1_10_sig,
      vdd => vdd,
      vss => vss
   );

na4_x1_6_ins : na4_x1
   port map (
      i0  => noa22_x1_10_sig,
      i1  => o3_x2_11_sig,
      i2  => na2_x1_28_sig,
      i3  => o3_x2_10_sig,
      nq  => na4_x1_6_sig,
      vdd => vdd,
      vss => vss
   );

no2_x1_23_ins : no2_x1
   port map (
      i0  => i(0),
      i1  => not_aux70,
      nq  => no2_x1_23_sig,
      vdd => vdd,
      vss => vss
   );

xr2_x1_8_ins : xr2_x1
   port map (
      i0  => no2_x1_23_sig,
      i1  => r(2),
      q   => xr2_x1_8_sig,
      vdd => vdd,
      vss => vss
   );

no2_x1_24_ins : no2_x1
   port map (
      i0  => r(1),
      i1  => not_aux90,
      nq  => no2_x1_24_sig,
      vdd => vdd,
      vss => vss
   );

xr2_x1_9_ins : xr2_x1
   port map (
      i0  => no2_x1_24_sig,
      i1  => r(2),
      q   => xr2_x1_9_sig,
      vdd => vdd,
      vss => vss
   );

oa2a22_x2_4_ins : oa2a22_x2
   port map (
      i0  => not_s(1),
      i1  => xr2_x1_9_sig,
      i2  => xr2_x1_8_sig,
      i3  => s(1),
      q   => oa2a22_x2_4_sig,
      vdd => vdd,
      vss => vss
   );

xr2_x1_11_ins : xr2_x1
   port map (
      i0  => i(0),
      i1  => s(2),
      q   => xr2_x1_11_sig,
      vdd => vdd,
      vss => vss
   );

xr2_x1_10_ins : xr2_x1
   port map (
      i0  => xr2_x1_11_sig,
      i1  => r(2),
      q   => xr2_x1_10_sig,
      vdd => vdd,
      vss => vss
   );

mx3_x2_3_ins : mx3_x2
   port map (
      cmd0 => not_i(2),
      cmd1 => not_s(2),
      i0   => xr2_x1_10_sig,
      i1   => oa2a22_x2_4_sig,
      i2   => na4_x1_6_sig,
      q    => mx3_x2_3_sig,
      vdd  => vdd,
      vss  => vss
   );

alu_out_2_ins : mx3_x2
   port map (
      cmd0 => not_i(1),
      cmd1 => not_i(2),
      i0   => mx3_x2_3_sig,
      i1   => xr2_x1_5_sig,
      i2   => inv_x2_13_sig,
      q    => alu_out(2),
      vdd  => vdd,
      vss  => vss
   );

inv_x2_14_ins : inv_x2
   port map (
      i   => not_aux129,
      nq  => inv_x2_14_sig,
      vdd => vdd,
      vss => vss
   );

no2_x1_25_ins : no2_x1
   port map (
      i0  => not_aux131,
      i1  => not_r(1),
      nq  => no2_x1_25_sig,
      vdd => vdd,
      vss => vss
   );

nao22_x1_22_ins : nao22_x1
   port map (
      i0  => r(1),
      i1  => not_aux132,
      i2  => not_aux130,
      nq  => nao22_x1_22_sig,
      vdd => vdd,
      vss => vss
   );

oa2ao222_x2_2_ins : oa2ao222_x2
   port map (
      i0  => nao22_x1_22_sig,
      i1  => r(2),
      i2  => no2_x1_25_sig,
      i3  => inv_x2_14_sig,
      i4  => not_r(2),
      q   => oa2ao222_x2_2_sig,
      vdd => vdd,
      vss => vss
   );

inv_x2_15_ins : inv_x2
   port map (
      i   => not_aux132,
      nq  => inv_x2_15_sig,
      vdd => vdd,
      vss => vss
   );

inv_x2_16_ins : inv_x2
   port map (
      i   => not_aux131,
      nq  => inv_x2_16_sig,
      vdd => vdd,
      vss => vss
   );

mx2_x2_2_ins : mx2_x2
   port map (
      cmd => r(1),
      i0  => inv_x2_16_sig,
      i1  => not_aux127,
      q   => mx2_x2_2_sig,
      vdd => vdd,
      vss => vss
   );

mx3_x2_5_ins : mx3_x2
   port map (
      cmd0 => r(2),
      cmd1 => not_r(1),
      i0   => mx2_x2_2_sig,
      i1   => not_aux127,
      i2   => inv_x2_15_sig,
      q    => mx3_x2_5_sig,
      vdd  => vdd,
      vss  => vss
   );

nao22_x1_23_ins : nao22_x1
   port map (
      i0  => r(1),
      i1  => not_aux128,
      i2  => not_aux130,
      nq  => nao22_x1_23_sig,
      vdd => vdd,
      vss => vss
   );

nao22_x1_24_ins : nao22_x1
   port map (
      i0  => not_aux126,
      i1  => not_r(1),
      i2  => not_aux129,
      nq  => nao22_x1_24_sig,
      vdd => vdd,
      vss => vss
   );

inv_x2_17_ins : inv_x2
   port map (
      i   => not_aux128,
      nq  => inv_x2_17_sig,
      vdd => vdd,
      vss => vss
   );

inv_x2_18_ins : inv_x2
   port map (
      i   => not_aux127,
      nq  => inv_x2_18_sig,
      vdd => vdd,
      vss => vss
   );

nao2o22_x1_2_ins : nao2o22_x1
   port map (
      i0  => not_r(1),
      i1  => not_aux127,
      i2  => not_aux126,
      i3  => r(1),
      nq  => nao2o22_x1_2_sig,
      vdd => vdd,
      vss => vss
   );

mx3_x2_7_ins : mx3_x2
   port map (
      cmd0 => r(2),
      cmd1 => not_r(1),
      i0   => nao2o22_x1_2_sig,
      i1   => inv_x2_18_sig,
      i2   => inv_x2_17_sig,
      q    => mx3_x2_7_sig,
      vdd  => vdd,
      vss  => vss
   );

mx3_x2_6_ins : mx3_x2
   port map (
      cmd0 => s(1),
      cmd1 => not_r(2),
      i0   => mx3_x2_7_sig,
      i1   => nao22_x1_24_sig,
      i2   => nao22_x1_23_sig,
      q    => mx3_x2_6_sig,
      vdd  => vdd,
      vss  => vss
   );

mx3_x2_4_ins : mx3_x2
   port map (
      cmd0 => s(2),
      cmd1 => s(1),
      i0   => mx3_x2_6_sig,
      i1   => mx3_x2_5_sig,
      i2   => oa2ao222_x2_2_sig,
      q    => mx3_x2_4_sig,
      vdd  => vdd,
      vss  => vss
   );

on12_x1_6_ins : on12_x1
   port map (
      i0  => aux65,
      i1  => aux138,
      q   => on12_x1_6_sig,
      vdd => vdd,
      vss => vss
   );

o2_x2_17_ins : o2_x2
   port map (
      i0  => not_aux64,
      i1  => aux86,
      q   => o2_x2_17_sig,
      vdd => vdd,
      vss => vss
   );

no2_x1_26_ins : no2_x1
   port map (
      i0  => not_aux133,
      i1  => not_s(2),
      nq  => no2_x1_26_sig,
      vdd => vdd,
      vss => vss
   );

na3_x1_20_ins : na3_x1
   port map (
      i0  => no2_x1_26_sig,
      i1  => o2_x2_17_sig,
      i2  => on12_x1_6_sig,
      nq  => na3_x1_20_sig,
      vdd => vdd,
      vss => vss
   );

no4_x1_4_ins : no4_x1
   port map (
      i0  => not_aux108,
      i1  => not_r(2),
      i2  => not_aux64,
      i3  => not_r(1),
      nq  => no4_x1_4_sig,
      vdd => vdd,
      vss => vss
   );

no3_x1_15_ins : no3_x1
   port map (
      i0  => aux138,
      i1  => not_aux65,
      i2  => not_aux108,
      nq  => no3_x1_15_sig,
      vdd => vdd,
      vss => vss
   );

no3_x1_16_ins : no3_x1
   port map (
      i0  => not_aux134,
      i1  => not_aux133,
      i2  => not_aux70,
      nq  => no3_x1_16_sig,
      vdd => vdd,
      vss => vss
   );

on12_x1_7_ins : on12_x1
   port map (
      i0  => not_aux113,
      i1  => no3_x1_16_sig,
      q   => on12_x1_7_sig,
      vdd => vdd,
      vss => vss
   );

no3_x1_14_ins : no3_x1
   port map (
      i0  => on12_x1_7_sig,
      i1  => no3_x1_15_sig,
      i2  => no4_x1_4_sig,
      nq  => no3_x1_14_sig,
      vdd => vdd,
      vss => vss
   );

no2_x1_27_ins : no2_x1
   port map (
      i0  => not_aux71,
      i1  => not_s(3),
      nq  => no2_x1_27_sig,
      vdd => vdd,
      vss => vss
   );

no3_x1_17_ins : no3_x1
   port map (
      i0  => r(3),
      i1  => not_aux90,
      i2  => s(3),
      nq  => no3_x1_17_sig,
      vdd => vdd,
      vss => vss
   );

nao22_x1_25_ins : nao22_x1
   port map (
      i0  => no3_x1_17_sig,
      i1  => no2_x1_27_sig,
      i2  => aux137,
      nq  => nao22_x1_25_sig,
      vdd => vdd,
      vss => vss
   );

na2_x1_29_ins : na2_x1
   port map (
      i0  => not_aux64,
      i1  => aux137,
      nq  => na2_x1_29_sig,
      vdd => vdd,
      vss => vss
   );

ao22_x2_6_ins : ao22_x2
   port map (
      i0  => not_aux70,
      i1  => not_aux134,
      i2  => not_s(2),
      q   => ao22_x2_6_sig,
      vdd => vdd,
      vss => vss
   );

na3_x1_21_ins : na3_x1
   port map (
      i0  => ao22_x2_6_sig,
      i1  => na2_x1_29_sig,
      i2  => aux108,
      nq  => na3_x1_21_sig,
      vdd => vdd,
      vss => vss
   );

a4_x2_6_ins : a4_x2
   port map (
      i0  => na3_x1_21_sig,
      i1  => nao22_x1_25_sig,
      i2  => no3_x1_14_sig,
      i3  => na3_x1_20_sig,
      q   => a4_x2_6_sig,
      vdd => vdd,
      vss => vss
   );

nao2o22_x1_3_ins : nao2o22_x1
   port map (
      i0  => i(2),
      i1  => a4_x2_6_sig,
      i2  => not_aux127,
      i3  => not_i(2),
      nq  => nao2o22_x1_3_sig,
      vdd => vdd,
      vss => vss
   );

alu_out_3_ins : mx3_x2
   port map (
      cmd0 => not_i(1),
      cmd1 => not_i(2),
      i0   => nao2o22_x1_3_sig,
      i1   => mx3_x2_4_sig,
      i2   => aux105,
      q    => alu_out(3),
      vdd  => vdd,
      vss  => vss
   );


end structural;