2010-03-09 09:24:55 -06:00
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// -*- C++ -*-
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//
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// This file is part of the Coriolis Software.
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// Copyright (c) UPMC/LIP6 2008-2010, All Rights Reserved
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//
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// ===================================================================
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//
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// $Id$
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//
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// x-----------------------------------------------------------------x
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// | |
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// | C O R I O L I S |
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// | K i t e - D e t a i l e d R o u t e r |
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// | |
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// | Author : Jean-Paul CHAPUT |
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// | E-mail : Jean-Paul.Chaput@asim.lip6.fr |
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// | =============================================================== |
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// | C++ Module : "./TrackFixedSegment.cpp" |
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// | *************************************************************** |
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// | U p d a t e s |
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// | |
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// x-----------------------------------------------------------------x
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#include <sstream>
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#include "hurricane/Bug.h"
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#include "hurricane/Warning.h"
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#include "hurricane/Net.h"
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#include "hurricane/Name.h"
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#include "hurricane/RegularLayer.h"
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#include "hurricane/Technology.h"
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#include "hurricane/DataBase.h"
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#include "hurricane/Horizontal.h"
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#include "hurricane/Vertical.h"
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#include "katabatic/AutoContact.h"
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2010-12-12 16:15:44 -06:00
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#include "katabatic/GCellGrid.h"
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2010-03-09 09:24:55 -06:00
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#include "crlcore/RoutingGauge.h"
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#include "kite/DataNegociate.h"
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#include "kite/TrackFixedSegment.h"
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#include "kite/TrackCost.h"
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#include "kite/Track.h"
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#include "kite/Session.h"
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#include "kite/RoutingEvent.h"
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#include "kite/NegociateWindow.h"
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#include "kite/KiteEngine.h"
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namespace Kite {
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using namespace std;
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using Hurricane::inltrace;
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using Hurricane::ltracein;
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using Hurricane::ltraceout;
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using Hurricane::tab;
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using Hurricane::Warning;
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using Hurricane::ForEachIterator;
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using Hurricane::Bug;
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using Hurricane::Error;
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using Hurricane::Net;
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using Hurricane::Name;
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using Hurricane::RegularLayer;
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using Hurricane::Technology;
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using Hurricane::DataBase;
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using Hurricane::Horizontal;
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using Hurricane::Vertical;
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// -------------------------------------------------------------------
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// Class : "TrackFixedSegment".
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* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
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Net* TrackFixedSegment::_blockageNet = NULL;
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2010-03-09 09:24:55 -06:00
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TrackFixedSegment::TrackFixedSegment ( Track* track, Segment* segment )
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: TrackElement (NULL)
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, _segment (segment)
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* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
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, _isBlockage (segment->getNet() == _blockageNet)
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2010-03-09 09:24:55 -06:00
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{
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Box boundingBox = segment->getBoundingBox();
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if ( track ) {
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unsigned int depth = track->getDepth();
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Technology* technology = DataBase::getDB()->getTechnology();
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const Layer* layer1 = track->getLayer()->getBlockageLayer();
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RegularLayer* layer2 = dynamic_cast<RegularLayer*>(technology->getLayer(layer1->getMask()));
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if ( layer2 ) {
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* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
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//DbU::Unit extention = layer2->getExtentionCap();
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2010-03-09 09:24:55 -06:00
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if ( track->getDirection() == Constant::Horizontal ) {
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2010-04-23 08:14:17 -05:00
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Interval uside = track->getKiteEngine()->getGCellGrid()->getUSide ( Constant::Horizontal );
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* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
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_sourceU = max ( boundingBox.getXMin(), uside.getVMin());
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_targetU = min ( boundingBox.getXMax(), uside.getVMax());
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2010-03-09 09:24:55 -06:00
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2010-12-12 15:42:57 -06:00
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Katabatic::GCell* gcell = track->getKiteEngine()->getGCellGrid()->getGCell ( Point(_sourceU,track->getAxis()) );
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Katabatic::GCell* end = track->getKiteEngine()->getGCellGrid()->getGCell ( Point(_targetU,track->getAxis()) );
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Katabatic::GCell* right = NULL;
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Interval guside = gcell->getUSide ( Constant::Horizontal /*, true*/ );
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Interval segside ( boundingBox.getXMin(), boundingBox.getXMax() );
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2010-04-23 08:14:17 -05:00
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2010-03-09 09:24:55 -06:00
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if ( gcell ) {
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while ( gcell and (gcell != end) ) {
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right = gcell->getRight();
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if ( right == NULL ) break;
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* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
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2010-12-12 15:42:57 -06:00
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guside = gcell->getUSide ( Constant::Horizontal /*, true*/ );
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* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
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Interval usedLength = guside.getIntersection ( segside );
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* ./kite:
- New: In RoutingEvent, while routing a full chip, transient full blockages
may happens due to the initial position of some perpandiculars on theirs
optimal positions. Check for it and perform a "ripupPerpandicular" with
the perpandiculars re-routed first (on normal operation, this is the
reverse).
- Change: In NegociateWindow::NegociateOverlapCost(), do not account terminals
if the layer is *above* METAL3 as it is unlikely that it's truly directly
connected to a terminal (true at least for our designs).
- Change: In RoutingEvent::State, add a "fullBlocked" flag to perform the
full blockage direction while building the state object.
- Change: In RoutingEvent::cacheAxisHint(), when the TrackSegment has parent,
uses the parent current axis position and not it's axis hint.
- Change: In Manipulator::insertInTrack(), when the overlapped segment is a
Local and is completly enclosed (shrinkLeft & shrinkRight), no longer
rip it up but force a shrink left/right instead.
- Bug: In RoutingEvent, the event sorting function was sorting in the *wrong*
order! The less prioritary first! With the correct sort, we won an
additionnal 30% in speed (total: 69%). From the "reference" time we have
a 3.2 speed-up. And we can successfully process denser designs...
2011-01-09 12:08:57 -06:00
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gcell->addBlockage ( depth, usedLength.getSize() );
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//gcell->addBlockedAxis ( depth, track->getAxis() );
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2010-03-09 09:24:55 -06:00
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gcell = right;
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}
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* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
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if ( end ) {
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2010-12-12 15:42:57 -06:00
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guside = gcell->getUSide ( Constant::Horizontal /*, true*/ );
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* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
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Interval usedLength = guside.getIntersection ( segside );
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* ./kite:
- New: In RoutingEvent, while routing a full chip, transient full blockages
may happens due to the initial position of some perpandiculars on theirs
optimal positions. Check for it and perform a "ripupPerpandicular" with
the perpandiculars re-routed first (on normal operation, this is the
reverse).
- Change: In NegociateWindow::NegociateOverlapCost(), do not account terminals
if the layer is *above* METAL3 as it is unlikely that it's truly directly
connected to a terminal (true at least for our designs).
- Change: In RoutingEvent::State, add a "fullBlocked" flag to perform the
full blockage direction while building the state object.
- Change: In RoutingEvent::cacheAxisHint(), when the TrackSegment has parent,
uses the parent current axis position and not it's axis hint.
- Change: In Manipulator::insertInTrack(), when the overlapped segment is a
Local and is completly enclosed (shrinkLeft & shrinkRight), no longer
rip it up but force a shrink left/right instead.
- Bug: In RoutingEvent, the event sorting function was sorting in the *wrong*
order! The less prioritary first! With the correct sort, we won an
additionnal 30% in speed (total: 69%). From the "reference" time we have
a 3.2 speed-up. And we can successfully process denser designs...
2011-01-09 12:08:57 -06:00
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end->addBlockage ( depth, usedLength.getSize() );
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//end->addBlockedAxis ( depth, track->getAxis() );
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* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
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}
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2010-03-09 09:24:55 -06:00
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} else
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cerr << Warning("TrackFixedSegment(): TrackFixedElement outside GCell grid.") << endl;
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} else {
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2010-04-23 08:14:17 -05:00
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Interval uside = track->getKiteEngine()->getGCellGrid()->getUSide ( Constant::Vertical );
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* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
_sourceU = max ( boundingBox.getYMin(), uside.getVMin());
|
|
|
|
_targetU = min ( boundingBox.getYMax(), uside.getVMax());
|
2010-03-09 09:24:55 -06:00
|
|
|
|
2010-12-12 15:42:57 -06:00
|
|
|
Katabatic::GCell* gcell = track->getKiteEngine()->getGCellGrid()->getGCell ( Point(track->getAxis(),_sourceU) );
|
|
|
|
Katabatic::GCell* end = track->getKiteEngine()->getGCellGrid()->getGCell ( Point(track->getAxis(),_targetU) );
|
|
|
|
Katabatic::GCell* up = NULL;
|
|
|
|
Interval guside = gcell->getUSide ( Constant::Vertical /*, true*/ );
|
|
|
|
Interval segside ( boundingBox.getYMin(), boundingBox.getYMax() );
|
2010-03-09 09:24:55 -06:00
|
|
|
if ( gcell ) {
|
|
|
|
while ( gcell and (gcell != end) ) {
|
|
|
|
up = gcell->getUp();
|
|
|
|
if ( up == NULL ) break;
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
|
2010-12-12 15:42:57 -06:00
|
|
|
guside = gcell->getUSide ( Constant::Vertical /*, true*/ );
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
Interval usedLength = guside.getIntersection ( segside );
|
|
|
|
|
* ./kite:
- New: In RoutingEvent, while routing a full chip, transient full blockages
may happens due to the initial position of some perpandiculars on theirs
optimal positions. Check for it and perform a "ripupPerpandicular" with
the perpandiculars re-routed first (on normal operation, this is the
reverse).
- Change: In NegociateWindow::NegociateOverlapCost(), do not account terminals
if the layer is *above* METAL3 as it is unlikely that it's truly directly
connected to a terminal (true at least for our designs).
- Change: In RoutingEvent::State, add a "fullBlocked" flag to perform the
full blockage direction while building the state object.
- Change: In RoutingEvent::cacheAxisHint(), when the TrackSegment has parent,
uses the parent current axis position and not it's axis hint.
- Change: In Manipulator::insertInTrack(), when the overlapped segment is a
Local and is completly enclosed (shrinkLeft & shrinkRight), no longer
rip it up but force a shrink left/right instead.
- Bug: In RoutingEvent, the event sorting function was sorting in the *wrong*
order! The less prioritary first! With the correct sort, we won an
additionnal 30% in speed (total: 69%). From the "reference" time we have
a 3.2 speed-up. And we can successfully process denser designs...
2011-01-09 12:08:57 -06:00
|
|
|
gcell->addBlockage ( depth, usedLength.getSize() );
|
|
|
|
//gcell->addBlockedAxis ( depth, track->getAxis() );
|
2010-03-09 09:24:55 -06:00
|
|
|
gcell = up;
|
|
|
|
}
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
if ( end ) {
|
2010-12-12 15:42:57 -06:00
|
|
|
guside = gcell->getUSide ( Constant::Vertical /*, true*/ );
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
Interval usedLength = guside.getIntersection ( segside );
|
|
|
|
|
* ./kite:
- New: In RoutingEvent, while routing a full chip, transient full blockages
may happens due to the initial position of some perpandiculars on theirs
optimal positions. Check for it and perform a "ripupPerpandicular" with
the perpandiculars re-routed first (on normal operation, this is the
reverse).
- Change: In NegociateWindow::NegociateOverlapCost(), do not account terminals
if the layer is *above* METAL3 as it is unlikely that it's truly directly
connected to a terminal (true at least for our designs).
- Change: In RoutingEvent::State, add a "fullBlocked" flag to perform the
full blockage direction while building the state object.
- Change: In RoutingEvent::cacheAxisHint(), when the TrackSegment has parent,
uses the parent current axis position and not it's axis hint.
- Change: In Manipulator::insertInTrack(), when the overlapped segment is a
Local and is completly enclosed (shrinkLeft & shrinkRight), no longer
rip it up but force a shrink left/right instead.
- Bug: In RoutingEvent, the event sorting function was sorting in the *wrong*
order! The less prioritary first! With the correct sort, we won an
additionnal 30% in speed (total: 69%). From the "reference" time we have
a 3.2 speed-up. And we can successfully process denser designs...
2011-01-09 12:08:57 -06:00
|
|
|
end->addBlockage ( depth, usedLength.getSize() );
|
|
|
|
//end->addBlockedAxis ( depth, track->getAxis() );
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
}
|
2010-03-09 09:24:55 -06:00
|
|
|
} else
|
|
|
|
cerr << Warning("TrackFixedSegment(): TrackFixedElement outside GCell grid.") << endl;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void TrackFixedSegment::_postCreate ()
|
|
|
|
{ TrackElement::_postCreate (); }
|
|
|
|
|
|
|
|
|
|
|
|
TrackFixedSegment::~TrackFixedSegment ()
|
|
|
|
{ }
|
|
|
|
|
|
|
|
|
|
|
|
void TrackFixedSegment::_preDestroy ()
|
|
|
|
{
|
|
|
|
ltrace(90) << "TrackFixedSegment::_preDestroy() - " << (void*)this << endl;
|
|
|
|
TrackElement::_preDestroy ();
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
TrackElement* TrackFixedSegment::create ( Track* track, Segment* segment )
|
|
|
|
{
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
if ( not _blockageNet ) _blockageNet = Session::getBlockageNet();
|
|
|
|
|
2010-03-09 09:24:55 -06:00
|
|
|
TrackFixedSegment* trackFixedSegment = NULL;
|
|
|
|
if ( track ) {
|
|
|
|
trackFixedSegment = new TrackFixedSegment ( track, segment );
|
|
|
|
trackFixedSegment->_postCreate ();
|
|
|
|
Session::addInsertEvent ( trackFixedSegment, track );
|
|
|
|
|
|
|
|
ltrace(190) << "Adding: " << segment << " on " << track << endl;
|
|
|
|
ltrace(200) << "TrackFixedSegment::create(): " << trackFixedSegment << endl;
|
|
|
|
}
|
|
|
|
return trackFixedSegment;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
AutoSegment* TrackFixedSegment::base () const { return NULL; }
|
|
|
|
bool TrackFixedSegment::isFixed () const { return true; }
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
bool TrackFixedSegment::isBlockage () const { return _isBlockage; }
|
2010-03-09 09:24:55 -06:00
|
|
|
DbU::Unit TrackFixedSegment::getAxis () const { return getTrack()->getAxis(); }
|
|
|
|
bool TrackFixedSegment::isHorizontal () const { return getTrack()->isHorizontal(); }
|
|
|
|
bool TrackFixedSegment::isVertical () const { return getTrack()->isVertical(); }
|
|
|
|
unsigned int TrackFixedSegment::getDirection () const { return getTrack()->getDirection(); }
|
|
|
|
const Layer* TrackFixedSegment::getLayer () const { return _segment->getLayer(); }
|
|
|
|
Interval TrackFixedSegment::getFreeInterval ( bool useOrder ) const { return Interval(); }
|
|
|
|
|
|
|
|
|
|
|
|
unsigned long TrackFixedSegment::getId () const
|
|
|
|
{
|
|
|
|
cerr << Error("::getId() called on %s.",_getString().c_str()) << endl;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
Net* TrackFixedSegment::getNet () const
|
|
|
|
{
|
|
|
|
Net* realNet = _segment->getNet();
|
|
|
|
if ( realNet->isSupply() or realNet->isClock() )
|
|
|
|
return _blockageNet;
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
return realNet;
|
* ./kite:
- New: In BuilPowerRails & BuildBlockage, specific support for chip-level
design. The Alliance "top chip" design hierarchical structure is
hard-coded. Top level POWER/GROUND/CLOCK nets must always have the
<vsse>, <vdde>, <ck>, <vssi>, <vddi>, <ckc>, <cki> names.
Specific method to get trans-hierarchical root nets, espcially in
case of global ones (POWER/GROUND). Clock is *not* global.
Some correction in the manner obscured tracks are computeds.
- New: ProtectRoutingPad module that perform a more clean work for protecting
unused RoutingPad.
- Bug: In BuildPowerRails, uses stable_sort<> instead of sort<>, which
causes unexplained core dumps (seems to try to perform a comparison
using the "end" pseudo element). Already occured in Knik, no explanation
other than a STL bug.
- Change: Slight changes in the weights to move up. Now needs a full empty
track instead of a half one.
2010-11-16 08:00:03 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2010-03-09 09:24:55 -06:00
|
|
|
TrackElement* TrackFixedSegment::getNext () const
|
|
|
|
{
|
|
|
|
size_t dummy = _index;
|
|
|
|
return _track->getNext ( dummy, getNet() );
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
TrackElement* TrackFixedSegment::getPrevious () const
|
|
|
|
{
|
|
|
|
size_t dummy = _index;
|
|
|
|
return _track->getPrevious ( dummy, getNet() );
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
string TrackFixedSegment::_getTypeName () const
|
|
|
|
{ return "TrackFixedSegment"; }
|
|
|
|
|
|
|
|
|
|
|
|
string TrackFixedSegment::_getString () const
|
|
|
|
{
|
|
|
|
string s1 = _segment->_getString();
|
|
|
|
string s2 = " [" + DbU::getValueString(_sourceU)
|
|
|
|
+ ":" + DbU::getValueString(_targetU) + "]"
|
|
|
|
+ " " + DbU::getValueString(_targetU-_sourceU)
|
* ./kite:
- Change: Propagate renaming "obstacle" -> "blockage".
- Bug/Change: In Configuration, the value of the extensionCap was too big
(1.5 lambda), reduce to 0.5 lambda. This is a problem, the extension
should be coupled to the layer as it is not the same for each METAL.
- Bug: When using TrackElement, always uses the virtual "->isFixed()" method
instead of trying to access to "->base()->isFixed()" as the base may be
NULL in case of blockage/fixed segment.
- Change: Merge PowerRails & Blockage trans-hierarchical construction (into
PowerRails). All blockages are groupeds under "blockagenet".
Allows to remove TrackBlockage & BuildBlockages.
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
ring power segments around the core must completly saturate the edges
in their segment direction. This is to prevent the global router to
use paths under the power/ground ring (may generate unsolvable configs).
- Change: In KiteEngine::annotateGloblalGraph(), when routing a full chip,
distinguish three areas: the core (65%), the corona (90%) and the pads
(100%). Capacities on the edges are sets accordingly.
- Change: In RoutingEvent, introduce an alternative algorithm for
conflictSolve1, FindPath which try to deduce the breakpoints from a
truly explorated path. Unfortunatly this gives worst results than the
Cs1Candidates method. The why should be investigated as it's a critical
point in the algorithm.
- Change: In Manipulator::ripupPerpandicular(), when a caged perpandicular
is encountered, instead of just "stopping", rip it up and change is
axis hint (actually increase) it's axis hint so it stands a chance to
go outside the track with an obstacle.
- Change: In RoutingEvent/State::slackenTopology(), allow move up of local
segments when they are tightly constrained *and* blocked (cageds).
Partial modification of functions calls from booleans to flags.
- Bug: In NegociateWindow::NegociateOverlapCost, check for fixed segments
before trying to get DataNegociate. The lack of DataNegociate cause the
TrackElement to be discarted. It's a failsafe behavior, but it leads to
overlaps.
- Bug: In ProtectRoutingPad, in Pad Cells only, *do not* protect RoutingPad
to avoid the edge capacity over the pad to decrease to zero. This is
due to unused RoutingPads being accounted as blockages.
2010-12-04 09:25:48 -06:00
|
|
|
+ " [" + ((_track) ? getString(_index) : "npos") + "] "
|
|
|
|
+ "F"
|
|
|
|
+ ((_isBlockage) ? "B" : "-");
|
2010-03-09 09:24:55 -06:00
|
|
|
s1.insert ( s1.size()-1, s2 );
|
|
|
|
|
|
|
|
return s1;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
Record* TrackFixedSegment::_getRecord () const
|
|
|
|
{
|
|
|
|
Record* record = TrackElement::_getRecord ();
|
|
|
|
record->add ( getSlot ( "_segment", _segment ) );
|
|
|
|
|
|
|
|
return record;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
} // End of Kite namespace.
|