\hypertarget{classpython_1_1CapacitorVRTracks_1_1VerticalRoutingTracks}{\section{Vertical\-Routing\-Tracks Class Reference}
\label{classpython_1_1CapacitorVRTracks_1_1VerticalRoutingTracks}\index{Vertical\-Routing\-Tracks@{Vertical\-Routing\-Tracks}}
}


Route two matched capacitors, C1 and C2, drawn in a capacitor matrix.  




Inherits Capacitor\-Unit, and Capacitor\-Stack.

\subsection*{Public Member Functions}
\begin{DoxyCompactItemize}
\item 
def \hyperlink{classpython_1_1CapacitorVRTracks_1_1VerticalRoutingTracks_a42e286a4157e638ddb3d96ce7c47dece}{\-\_\-\-\_\-set\-Stretching\-\_\-\-\_\-}
\begin{DoxyCompactList}\small\item\em Sets vertical stretching value considering spacing between elementary capacitors in the matrix. \end{DoxyCompactList}\item 
def \hyperlink{classpython_1_1CapacitorVRTracks_1_1VerticalRoutingTracks_a3b578035b1559391931dade7c2508105}{set\-Rules}
\begin{DoxyCompactList}\small\item\em Defines technology rules used to draw the layout. \end{DoxyCompactList}\item 
def \hyperlink{classpython_1_1CapacitorVRTracks_1_1VerticalRoutingTracks_ab509e7c1cfbf2826e4418a606c8982a3}{draw\-V\-Routing\-Tracks}
\begin{DoxyCompactList}\small\item\em Iteratively draws vertical routing tracks given the physical layer {\ttfamily v\-Routing\-Tracks\-Layer}. \end{DoxyCompactList}\end{DoxyCompactItemize}


\subsection{Detailed Description}
Route two matched capacitors, C1 and C2, drawn in a capacitor matrix. 

Connections are put in place with reference to a given matching scheme. Elementary capacitor units are connected to horizontal and vertical routing tracks that represent top plates and bottom plates nets of C1 and C2. Supported types of capacitors are Poly-\/\-Poly and Metal-\/\-Metal. Technologycal rules are provided by 350 nm A\-M\-S C\-M\-O\-S technology with three-\/four metal layers. Metal layers that are used for routeing are placed similarly to horziontal-\/vertical (H\-V) symbolic Alliance C\-A\-D tool router, where horizontal metal channels are drawn in metal 2 and the vertical ones are in metal 3. Given a matrix of dimensions $ R*C $, the total number of vertical tracks is $ 2C+2 $ equivalent to $ C+1 $ couples, ensuring that every elementary capacitor is positioned between four vertical tracks, two from each side. In fact, every adjacent couple of these tracks represent top plates and bottom plates of C1 or C2 as shown in Figure 1.



An elementary capacitor unit can be a part of C1 or C2 according to the matching scheme. However, to respect common-\/centroid layout specifications, for C1 and C2 to be equal, the matrix number of colums and number of rows must be both even. Addionnally, the number of elementary capacitors dedicated to C1 must be equal to those dedicated to C2. These two conditions are tested in one of the class methods. An exception is raised if at least one of the two is not respected. 

\subsection{Member Function Documentation}
\hypertarget{classpython_1_1CapacitorVRTracks_1_1VerticalRoutingTracks_a42e286a4157e638ddb3d96ce7c47dece}{\index{python\-::\-Capacitor\-V\-R\-Tracks\-::\-Vertical\-Routing\-Tracks@{python\-::\-Capacitor\-V\-R\-Tracks\-::\-Vertical\-Routing\-Tracks}!\-\_\-\-\_\-set\-Stretching\-\_\-\-\_\-@{\-\_\-\-\_\-set\-Stretching\-\_\-\-\_\-}}
\index{\-\_\-\-\_\-set\-Stretching\-\_\-\-\_\-@{\-\_\-\-\_\-set\-Stretching\-\_\-\-\_\-}!python::CapacitorVRTracks::VerticalRoutingTracks@{python\-::\-Capacitor\-V\-R\-Tracks\-::\-Vertical\-Routing\-Tracks}}
\subsubsection[{\-\_\-\-\_\-set\-Stretching\-\_\-\-\_\-}]{\setlength{\rightskip}{0pt plus 5cm}def \-\_\-\-\_\-set\-Stretching\-\_\-\-\_\- (
\begin{DoxyParamCaption}
\item[{}]{self}
\end{DoxyParamCaption}
)}}\label{classpython_1_1CapacitorVRTracks_1_1VerticalRoutingTracks_a42e286a4157e638ddb3d96ce7c47dece}


Sets vertical stretching value considering spacing between elementary capacitors in the matrix. 

\begin{DoxyReturn}{Returns}
stratching value. 
\end{DoxyReturn}


References Vertical\-Routing\-Tracks.\-abutment\-Box\-\_\-spacing, Capacitor\-Stack.\-abutment\-Box\-\_\-spacing, and Rout\-Matched\-Capacitor.\-abutment\-Box\-\_\-spacing.



Referenced by Rout\-Matched\-Capacitor.\-compute\-H\-R\-Layer\-Y\-Center(), and Vertical\-Routing\-Tracks.\-draw\-V\-Routing\-Tracks().

\hypertarget{classpython_1_1CapacitorVRTracks_1_1VerticalRoutingTracks_a3b578035b1559391931dade7c2508105}{\index{python\-::\-Capacitor\-V\-R\-Tracks\-::\-Vertical\-Routing\-Tracks@{python\-::\-Capacitor\-V\-R\-Tracks\-::\-Vertical\-Routing\-Tracks}!set\-Rules@{set\-Rules}}
\index{set\-Rules@{set\-Rules}!python::CapacitorVRTracks::VerticalRoutingTracks@{python\-::\-Capacitor\-V\-R\-Tracks\-::\-Vertical\-Routing\-Tracks}}
\subsubsection[{set\-Rules}]{\setlength{\rightskip}{0pt plus 5cm}def set\-Rules (
\begin{DoxyParamCaption}
\item[{}]{self}
\end{DoxyParamCaption}
)}}\label{classpython_1_1CapacitorVRTracks_1_1VerticalRoutingTracks_a3b578035b1559391931dade7c2508105}


Defines technology rules used to draw the layout. 

Some of the rules, namely those describing routeing layers and tracks are applicable for both M\-I\-M and P\-I\-P capacitors. However, cuts rules are different. \begin{DoxyParagraph}{Remark\-:}
All {\ttfamily Capacitor\-Stack} class rules are also reloaded in this class. An exception is raised if the entered capacitor type is unsupported. 
\end{DoxyParagraph}
\begin{DoxyReturn}{Returns}
a dictionary with rules labels as keys and rules content as values. 
\end{DoxyReturn}


References Vertical\-Routing\-Tracks.\-capacitors\-Number, Capacitor\-Stack.\-capacitors\-Number, Vertical\-Routing\-Tracks.\-compute\-V\-R\-T\-Dimensions(), Vertical\-Routing\-Tracks.\-draw\-V\-Routing\-Tracks(), Vertical\-Routing\-Tracks.\-min\-Enclosure\-\_\-h\-Routing\-Layer\-\_\-v\-Routing\-Track\-\_\-cut, Vertical\-Routing\-Tracks.\-min\-Enclosure\-\_\-h\-Routing\-Track\-Cut, Vertical\-Routing\-Tracks.\-minimize\-V\-R\-Ts(), Vertical\-Routing\-Tracks.\-min\-Spacing\-\_\-h\-Routing\-Track, Rout\-Matched\-Capacitor.\-min\-Spacing\-\_\-h\-Routing\-Track, Vertical\-Routing\-Tracks.\-min\-Width\-\_\-h\-Routing\-Layer, Vertical\-Routing\-Tracks.\-min\-Width\-\_\-h\-Routing\-Layer\-\_\-v\-Routing\-Track\-\_\-cut, Vertical\-Routing\-Tracks.\-min\-Width\-\_\-h\-Routing\-Track, Vertical\-Routing\-Tracks.\-min\-Width\-\_\-h\-Routing\-Track\-Cut, Vertical\-Routing\-Tracks.\-set\-Rules(), Capacitor\-Stack.\-set\-Rules(), Capacitor\-Unit.\-set\-Rules(), and Rout\-Matched\-Capacitor.\-set\-Rules().



Referenced by Vertical\-Routing\-Tracks.\-set\-Rules().

\hypertarget{classpython_1_1CapacitorVRTracks_1_1VerticalRoutingTracks_ab509e7c1cfbf2826e4418a606c8982a3}{\index{python\-::\-Capacitor\-V\-R\-Tracks\-::\-Vertical\-Routing\-Tracks@{python\-::\-Capacitor\-V\-R\-Tracks\-::\-Vertical\-Routing\-Tracks}!draw\-V\-Routing\-Tracks@{draw\-V\-Routing\-Tracks}}
\index{draw\-V\-Routing\-Tracks@{draw\-V\-Routing\-Tracks}!python::CapacitorVRTracks::VerticalRoutingTracks@{python\-::\-Capacitor\-V\-R\-Tracks\-::\-Vertical\-Routing\-Tracks}}
\subsubsection[{draw\-V\-Routing\-Tracks}]{\setlength{\rightskip}{0pt plus 5cm}def draw\-V\-Routing\-Tracks (
\begin{DoxyParamCaption}
\item[{}]{self, }
\item[{}]{v\-Routing\-Tracks\-Layer}
\end{DoxyParamCaption}
)}}\label{classpython_1_1CapacitorVRTracks_1_1VerticalRoutingTracks_ab509e7c1cfbf2826e4418a606c8982a3}


Iteratively draws vertical routing tracks given the physical layer {\ttfamily v\-Routing\-Tracks\-Layer}. 

Every elementary capacitor is consequently positioned between four routing tracks, two from each side. Each couple of adjacent routeing tracks represent top plate and bottom plate nets of Ci, where i is in \mbox{[}1,2\mbox{]}. As given in Figure 2, capacitor $ C_{ij} $ with an even j value situated in even columns have and inversely for odd columns numbers. 

References Vertical\-Routing\-Tracks.\-\_\-\-\_\-compute\-V\-R\-Ts\-Number\-\_\-\-\_\-(), Vertical\-Routing\-Tracks.\-\_\-\-\_\-find\-Cap\-Ids\-To\-Eliminate\-\_\-\-\_\-(), Vertical\-Routing\-Tracks.\-\_\-\-\_\-find\-Cap\-Ids\-To\-Eliminate\-Per\-Column\-\_\-\-\_\-(), Vertical\-Routing\-Tracks.\-\_\-\-\_\-find\-Used\-Cap\-Ids\-Per\-Column\-\_\-\-\_\-(), Vertical\-Routing\-Tracks.\-\_\-\-\_\-find\-V\-R\-Ts\-To\-Eliminate\-\_\-\-\_\-(), Vertical\-Routing\-Tracks.\-\_\-\-\_\-set\-Nets\-Distribution\-\_\-\-\_\-(), Vertical\-Routing\-Tracks.\-\_\-\-\_\-set\-Plates\-Distribution\-\_\-\-\_\-(), Vertical\-Routing\-Tracks.\-\_\-\-\_\-set\-Stretching\-\_\-\-\_\-(), Vertical\-Routing\-Tracks.\-\_\-\-\_\-set\-V\-R\-Ts\-Distribution\-\_\-\-\_\-(), Vertical\-Routing\-Tracks.\-abutment\-Box\-\_\-spacing, Capacitor\-Stack.\-abutment\-Box\-\_\-spacing, Rout\-Matched\-Capacitor.\-abutment\-Box\-\_\-spacing, Vertical\-Routing\-Tracks.\-capacitor\-Ids, Vertical\-Routing\-Tracks.\-capacitors\-Number, Capacitor\-Stack.\-capacitors\-Number, Vertical\-Routing\-Tracks.\-compute\-X\-Centers(), Vertical\-Routing\-Tracks.\-dummy\-Element, Capacitor\-Stack.\-dummy\-Element, Rout\-Matched\-Capacitor.\-dummy\-Element, Vertical\-Routing\-Tracks.\-dummy\-Ring, Capacitor\-Stack.\-dummy\-Ring, Rout\-Matched\-Capacitor.\-dummy\-Ring, Vertical\-Routing\-Tracks.\-get\-V\-Track\-Y\-Max(), Vertical\-Routing\-Tracks.\-get\-V\-Track\-Y\-Min(), Capacitor\-Unit.\-hpitch, Rout\-Matched\-Capacitor.\-h\-Routing\-Track\-\_\-width, Vertical\-Routing\-Tracks.\-h\-Routing\-Track\-\_\-width, Vertical\-Routing\-Tracks.\-matching\-Scheme, Capacitor\-Stack.\-matching\-Scheme, Capacitor\-Stack.\-matrix\-Dim, Vertical\-Routing\-Tracks.\-matrix\-Dim, Rout\-Matched\-Capacitor.\-maximum\-Position, Vertical\-Routing\-Tracks.\-maximum\-Position, Capacitor\-Unit.\-metal2\-Width, Vertical\-Routing\-Tracks.\-min\-Enclosure\-\_\-h\-Routing\-Track\-Cut, Vertical\-Routing\-Tracks.\-minimize\-V\-R\-T, Rout\-Matched\-Capacitor.\-minimum\-Position, Vertical\-Routing\-Tracks.\-minimum\-Position, Vertical\-Routing\-Tracks.\-min\-Width\-\_\-h\-Routing\-Track, Vertical\-Routing\-Tracks.\-min\-Width\-\_\-h\-Routing\-Track\-Cut, Vertical\-Routing\-Tracks.\-nets, Capacitor\-Stack.\-nets, Vertical\-Routing\-Tracks.\-plates\-Distribution, Vertical\-Routing\-Tracks.\-v\-Routing\-Track\-\_\-width, Capacitor\-Stack.\-v\-Routing\-Track\-\_\-width, Vertical\-Routing\-Tracks.\-v\-Routing\-Track\-Dict, Rout\-Matched\-Capacitor.\-v\-Routing\-Track\-Dict, Vertical\-Routing\-Tracks.\-v\-Routing\-Track\-X\-Center, Rout\-Matched\-Capacitor.\-v\-Routing\-Track\-X\-Center, Vertical\-Routing\-Tracks.\-v\-R\-Ts\-Distribution, Rout\-Matched\-Capacitor.\-v\-R\-Ts\-Distribution, and Vertical\-Routing\-Tracks.\-v\-R\-Ts\-To\-Eliminate.



Referenced by Vertical\-Routing\-Tracks.\-set\-Rules().



The documentation for this class was generated from the following file\-:\begin{DoxyCompactItemize}
\item 
Capacitor\-V\-R\-Tracks.\-py\end{DoxyCompactItemize}
