<?xml version="1.0" encoding="UTF-8"?>
<circuit name="inverter" techno="myTech">
  <parameters>
    <parameter   name="temp"    value="27.0"/>
    <parameter   name="Vdd"     value="1.2"/>
    <parameter   name="Vss"     value="0.0"/>
    <parameter   name="L"       value="0.10e-6"/>
    <parameter   name="Ids"     value="30e-6"/>
    <parameter   name="Veg"     value="0.12"/>
    <parameterEq name="complex" equation="myEq"/>
  </parameters>
  <netlist>
    <instances>
      <instance name="nmos1" model="Transistor" order="1" mostype="NMOS" sourceBulkConnected="True">
        <connectors>
          <connector name="G"/>
          <connector name="D"/>
          <connector name="S"/>
        </connectors>
        <transistors>
          <transistor name="m1">
            <connection gate="G" source="S" drain="D" bulk="S"/>
          </transistor>
        </transistors>
      </instance>
      <instance name="pmos1" model="Transistor" order="2" mostype="PMOS" sourceBulkConnected="True">
        <connectors>
          <connector name="G"/>
          <connector name="D"/>
          <connector name="S"/>
        </connectors>
        <transistors>
          <transistor name="m1">
            <connection gate="G" source="S" drain="D" bulk="S"/>
          </transistor>
        </transistors>
      </instance>
    </instances>
    <nets>
      <net name="vdd" type="power" isExternal="True">
        <connector instance="pmos1" name="S"/>
      </net>
      <net name="vss" type="ground" isExternal="True">
        <connector instance="nmos1" name="S"/>
      </net>
      <net name="in" type="logical" isExternal="True">
        <connector instance="nmos1" name="G"/>
        <connector instance="pmos1" name="G"/>
      </net>
      <net name="out" type="logical" isExternal="True">
        <connector instance="nmos1" name="D"/>
        <connector instance="pmos1" name="D"/>
      </net>
    </nets>
  </netlist>
  <schematic>
    <instance name="nmos1" x="2490" y="2600" orient="ID"/>
    <instance name="pmos1" x="2490" y="2490" orient="ID"/>
    <net name="vdd">
      <port type="inV" idx="0" x="2525" y="2430" orient="ID"/>
      <wire>
        <connector name="pmos1" plug="S"/>
        <!--point x="" y=""/-->
        <connector idx="0"/>
      </wire>
    </net>
    <net name="vss">
      <port type="inV" idx="0" x="2525" y="2740" orient="MY"/>
      <wire>
        <connector name="nmos1" plug="S"/>
        <connector idx="0"/>
      </wire>
    </net>
    <net name="in">
      <port type="inH" idx="0" x="2415" y="2520" orient="ID"/>
      <wire>
        <connector name="pmos1" plug="G"/>
        <connector name="nmos1" plug="G"/>
      </wire>
      <wire>
        <connector idx="0"/>
        <connector name="pmos1" plug="G"/>
      </wire>
    </net>
    <net name="out">
      <port type="outH" idx="0" x="2570" y="2590" orient="ID"/>
      <wire>
        <connector name="pmos1" plug="D"/>
        <connector name="nmos1" plug="D"/>
      </wire>
      <wire>
        <connector name="nmos1" plug="D"/>
        <connector idx="0"/>
      </wire>
    </net>
  </schematic>
  <sizing>
    <instance name="pmos1" operator="OPVG(Veg)" simulModel="BSIM3V3">
      <constraint param="Temp" ref="design" refParam="temp"/>
      <constraint param="Ids"  ref="design" refParam="Ids"/>
      <constraint param="L"    ref="design" refParam="L"/>
      <constraint param="Veg"  ref="design" refParam="Veg"/>
      <constraint param="Vd"   ref="design" refParam="Vdd" factor="0.5"/>
      <constraint param="Vs"   ref="design" refParam="Vdd"/>
    </instance>
    <instance name="nmos1" operator="OPW(Vg,Vs)" simulModel="BSIM3V3">
      <constraint param="Temp" ref="design" refParam="temp"/>
      <constraint param="Ids"  ref="design" refParam="Ids"/>
      <constraint param="L"    ref="design" refParam="L"/>
      <constraint param="Vs"   ref="design" refParam="Vdd"/>
      <constraint param="Vg"   ref="pmos1"  refParam="Vg"/>
      <constraint param="Vd"   ref="pmos1"  refParam="Vd"/>
      <constraint param="another" refEquation="myEq" factor="-2.5"/>
    </instance>
    <equations>
      <eq name="myEq" equation="A/more+complex*equation"/>
    </equations>
  </sizing>
  <layout>
    <instance name="pmos1" style="Common transistor"/>
    <instance name="nmos1" style="Rotate transistor"/>
    <hbtree>
      <group name="g1" align="vertical">
        <bloc name="nmos1">
          <bloc name="pmos1" position="top"/>
        </bloc>
      </group>
    </hbtree>
  </layout>
</circuit>
