caravel/verilog
Passant b463e533ec update caravel rtl/hierarchy:
+ add `mprj_io_buffer` module that is used to guide the router and buffer signals going to the IOs far from the housekeeping
+ add `caravel_core` rtl that includes all the macros of caravel
~ restructure caravel to `caravel_core` and `chip_io` that includes the padframe
~ update `caravel_clocking` rtl to include `porb` input reset signal from power-on-reset
~ update `gpio_control_block` rtl to buffer `serial_clock` and `serial_load` siganls
2023-02-26 13:43:37 +02:00
..
dv Update cocotb README file to include PDK export requirements 2022-10-30 01:47:46 -07:00
gl gpio_signal_buffering rtl decaps 2022-11-01 19:16:53 +02:00
rtl update caravel rtl/hierarchy: 2023-02-26 13:43:37 +02:00
stubs [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00