caravel/signoff/caravel
Passant 9fd3765224 ~ update caravel signoff summary 2023-04-26 09:18:18 -07:00
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openlane-signoff - remove outdated spef files 2023-03-14 15:09:42 -07:00
primetime ~ update caravel generated sdf and timing models 2023-04-21 07:31:00 -07:00
standalone_pvr updated physical verification reports 2023-04-26 17:33:44 +02:00
OPENLANE_VERSION reharden `caravel` 2023-03-26 02:58:37 -07:00
PDK_SOURCES reharden `caravel` using a newer OpenLane version 2023-04-10 07:17:02 -07:00
README.md [wip] caravel signoff results documentation 2022-11-11 09:37:59 -08:00
caravel.sdc add caravel (d5b286e) generated sdf and timing models 2023-04-02 08:05:37 -07:00
cmds.log reharden `caravel` using a newer OpenLane version 2023-04-10 07:17:02 -07:00
config.tcl reharden `caravel` using a newer OpenLane version 2023-04-10 07:17:02 -07:00
config_in.tcl reharden `caravel` 2023-03-27 04:46:50 -07:00
manufacturability.rpt reharden `caravel` using a newer OpenLane version 2023-04-10 07:17:02 -07:00
metrics.csv update the physical views of `caravel` after `caravel_core` update 2023-04-11 07:45:29 -07:00
openlane.log reharden `caravel` using a newer OpenLane version 2023-04-10 07:17:02 -07:00
runtime.yaml reharden `caravel` using a newer OpenLane version 2023-04-10 07:17:02 -07:00
signoff.rpt ~ update caravel signoff summary 2023-04-26 09:18:18 -07:00

README.md

Caravel Signoff

NOTE: This document is wip

Signoff Results

  • Summary of the signoff automation script could be found here
  • LVS: the full report could be found here
  • DRC: the total number of violations could be found here and the error database could be found here
  • STA:
    • Generated logs could be found here.
    • Generated reports could be found here.
    • For a summary of the results of each corner, check *global.rpt and *all_viol.rpt. The detailed timing paths and path groups could be found in the archive of each corner.
    • Sheet of the top-level and block-level results could be found here
  • CVC: the log could be found here
  • Antenna: the summary could be found here
  • Top-level wire length report could be found here

Signoff STA Constraints

Clock period: 25ns (40MHz)