caravel/verilog/gl
Tim Edwards 4cd9d9cf2a Added pins "vddio" and "vssio" to the openframe and openframe project
wrapper RTL netlists and and openframe project wrapper GL netlist.
2023-10-18 12:47:56 -04:00
..
__user_analog_project_wrapper.v Modified all of the Makefiles to better handle the GL netlist simulations, 2021-12-03 17:13:53 -05:00
__user_project_wrapper.v Modified all of the Makefiles to better handle the GL netlist simulations, 2021-12-03 17:13:53 -05:00
caravan-signoff.v signoff views for caravan 2022-10-22 07:01:29 -07:00
caravan.v changed `caravel_logo`, `caravel_motto`, `copyright_block` to `caravan_logo`, `caravan_motto`, `copyright_block_a` respectively in `verilog/gl/caravan.v` to match the layout 2023-06-01 13:46:47 -07:00
caravan_core-gl-ecos.txt add the analog connections in `caravan_core` GL 2023-05-24 00:42:28 -07:00
caravan_core-openlane.v swapped the left `vssd` and `vccd` rings in `caravan_core` to fix an LVS issue 2023-05-30 22:33:33 -07:00
caravan_core.v ~ update `caravan_core` to fix latch-up DRC violation (non MR) 2023-06-01 09:21:00 -07:00
caravan_signal_routing.v update `caravan_signal_routing` to get aligned with `caravan_core` 2023-05-23 03:19:33 -07:00
caravel.v reharden caravel using the modified chip_io. 2023-02-27 11:19:33 -08:00
caravel_clocking.v reharden caravel_clocking. 2023-02-27 10:26:19 -08:00
caravel_core.v reharden `caravel_core` using the updated `gpio_defaults_block` 2023-04-20 23:17:38 -07:00
caravel_logo.v add missing GLs. 2023-02-27 11:44:04 -08:00
caravel_motto.v add missing GLs. 2023-02-27 11:44:04 -08:00
caravel_openframe-example.v Added pins "vddio" and "vssio" to the openframe and openframe project 2023-10-18 12:47:56 -04:00
caravel_openframe.v Added pins "vddio" and "vssio" to the openframe and openframe project 2023-10-18 12:47:56 -04:00
chip_io.v ~ regenerate chip_io netlist to fix missing power pins from constant blocks 2022-10-12 11:40:05 -07:00
chip_io_alt.v Added gl netlists for chip_io_alt and gpio_signal_buffering_alt (#327) 2022-10-21 12:06:20 -07:00
chip_io_openframe.v After updating from the PR that adds the gate level chip_io_openframe.v, 2023-09-25 20:10:37 -04:00
constant_block.v Added constant block openlane files and powered gl and modified housekeeping config.tcl 2022-10-12 04:12:27 -07:00
copyright_block.v add missing GLs. 2023-02-27 11:44:04 -08:00
empty_macro.v Add empty_macro which acts as a placement obstruction. 2023-02-27 08:14:55 -08:00
empty_macro_1.v add `empty_macro_1` 2023-05-22 06:05:08 -07:00
gpio_defaults_block.v updated physical verification reports 2023-04-26 17:33:44 +02:00
gpio_defaults_block_0403.v Modified the GL netlists to match the layout for the GPIO defaults 2021-11-29 20:17:11 -05:00
gpio_defaults_block_0801.v Corrected the pull-up definition and revised the CSB definition to 2022-10-05 10:02:24 -04:00
gpio_defaults_block_1803.v Modified the GL netlists to match the layout for the GPIO defaults 2021-11-29 20:17:11 -05:00
gpio_logic_high.v reharden gpio_logic_high. 2023-02-27 10:29:46 -08:00
housekeeping.v reharden `housekeeping` using a newer OpenLane version 2023-04-10 07:13:48 -07:00
housekeeping_alt.v reharden `housekeeping_alt` 2023-05-24 02:34:43 -07:00
manual_power_connections.v Added manual_power_connections. 2023-02-27 08:15:35 -08:00
mgmt_protect.v Update Openlane views 2022-10-27 09:53:45 -07:00
mgmt_protect_hv.v Fix mgmt_protect_hv gate-level netlist 2021-12-07 13:38:30 +02:00
mprj2_logic_high.v [DATA] Add views for the mgmt_protect 2021-11-15 13:21:52 +02:00
mprj_io_buffer.v harden mprj_io_buffer. 2023-02-27 10:33:48 -08:00
mprj_logic_high.v [DATA] Add views for the mgmt_protect 2021-11-15 13:21:52 +02:00
open_source.v add missing GLs. 2023-02-27 11:44:04 -08:00
spare_logic_block.v reharden spare_logic_block. 2023-02-27 10:37:00 -08:00
user_id_programming.v [DATA] Add gds/lef/maglef/gl views for the user_id_programming block 2021-11-15 18:17:32 +02:00
user_id_textblock.v add missing GLs. 2023-02-27 11:44:04 -08:00
xres_buf.v [DATA] Add views for xres_buf 2021-11-15 18:07:02 +02:00