Tim Edwards ec93c72d18 Modified simple_por.v RTL to avoid the wire declaration that "cvc" ... doesn't like (even though it's perfectly legal).		2021-12-08 12:16:19 -05:00
..
dv	Fixed one bad error in clock_div which had been done without my	2021-12-06 21:37:51 -05:00
gl	Corrected an error in verilog/gl/chip_io_alt.v, which was missing	2021-12-07 10:06:35 -05:00
rtl	Modified simple_por.v RTL to avoid the wire declaration that "cvc"	2021-12-08 12:16:19 -05:00
stubs	[DATA] Add spare_logic_block	2021-11-24 20:36:23 +02:00