mirror of https://github.com/efabless/caravel.git
105 lines
4.0 KiB
Python
105 lines
4.0 KiB
Python
import random
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import cocotb
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from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
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import cocotb.log
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from cpu import RiskV
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from defsParser import Regs
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from cocotb.result import TestSuccess
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from tests.common_functions.test_functions import *
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from tests.bitbang.bitbang_functions import *
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from caravel import GPIO_MODE
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reg = Regs()
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"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI."""
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@cocotb.test()
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@repot_test
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async def mgmt_gpio_out(dut):
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caravelEnv = await test_configure(dut,timeout_cycles=18613481)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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cpu.cpu_release_reset()
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cocotb.log.info(f"[TEST] Start mgmt_gpio_out test")
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phases_fails = 2
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phases_passes = 0
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reg1 =0 # buffer
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reg2 = 0 #buffer
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while True:
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if reg2 != cpu.read_debug_reg2():
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reg2 = cpu.read_debug_reg2()
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if reg2 == 0xFF: # test finish
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break
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if reg1 != cpu.read_debug_reg1():
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reg1 = cpu.read_debug_reg1()
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cocotb.log.info(f"[TEST] waiting for {reg1} blinks")
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for i in range(reg1):
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while (True):
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if caravelEnv.monitor_mgmt_gpio() == 0:
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break
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if reg1 != cpu.read_debug_reg1():
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cocotb.log.error("[TEST] error failing to catch all blinking ")
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return
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await ClockCycles(caravelEnv.clk,10)
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while (True):
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if caravelEnv.monitor_mgmt_gpio() == 1:
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break
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if reg1 != cpu.read_debug_reg1():
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cocotb.log.error("[TEST] error failing to catch all blinking ")
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return
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await ClockCycles(caravelEnv.clk,10)
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cocotb.log.info("[TEST] passing sending {reg1} blinks ")
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phases_fails -=1
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await ClockCycles(caravelEnv.clk,10)
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if phases_fails != 0:
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cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
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else:
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cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
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@cocotb.test()
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@repot_test
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async def mgmt_gpio_in(dut):
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caravelEnv = await test_configure(dut,timeout_cycles=18613481)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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cpu.cpu_release_reset()
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cocotb.log.info(f"[TEST] Start mgmt_gpio_in test")
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phases_fails = 3
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phases_passes = 0
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pass_list = (0x1B,0x2B,0xFF)
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fail_list = tuple([0xEE])
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reg1 =0 # buffer
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reg2 = 0 #buffer
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while True:
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if reg2 != cpu.read_debug_reg2():
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reg2 = cpu.read_debug_reg2()
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if reg2 in pass_list:
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cocotb.log.info (f"[TEST] reg2 = {reg2}")
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phases_passes +=1
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phases_fails -=1
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if reg2 == 0xFF: # test finish
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break
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elif reg2 == 0x1B:
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cocotb.log.info(f"[TEST] pass sending 10 blink ")
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elif reg2 == 0x2B:
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cocotb.log.info(f"[TEST] pass sending 20 blink ")
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if reg2 in fail_list:
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cocotb.log.error(f"[TEST] gpio change without sending anything")
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if reg1 != cpu.read_debug_reg1():
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reg1 = cpu.read_debug_reg1()
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cocotb.log.info(f"[TEST] start sending {reg1} blinks")
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for i in range(reg1):
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caravelEnv.drive_mgmt_gpio(1)
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await wait_reg2(cpu,caravelEnv,0XAA)
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caravelEnv.drive_mgmt_gpio(0)
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await wait_reg2(cpu,caravelEnv,0XBB)
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cocotb.log.info(f"[TEST] finish sending {reg1} blinks ")
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await ClockCycles(caravelEnv.clk,10)
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if phases_fails != 0:
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cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
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else:
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cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") |