mirror of https://github.com/efabless/caravel.git
321 lines
5.6 KiB
Plaintext
321 lines
5.6 KiB
Plaintext
Definitions:
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caravel_openframe: Version with one wrapper for user
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project only.
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caravel_harness: Version with wrappers for user project
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area and management core.
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caravel_pico: PicoRV32, as a drop-in module for caravel_harness
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Harness definition:
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Management SoC and User Project are both wrappers for drop-in
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modules.
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The harness itself contains the clocking module, DLL, user ID,
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housekeeping SPI, POR, and GPIO control.
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GPIO handling moved out of management SoC and into SPI. SPI
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gets a wishbone interface; the management SoC talks to the SPI
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through wishbone, not by taking over the 4-pin SPI interface.
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(Maybe) New block like the ID has the mode at power-up for
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each GPIO. Can be configured with a text file. SPI pins are
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fixed for operation on startup.
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On power-up, the SPI automatically configures the GPIO. Manual
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load is possible from both the SPI and from the wishbone bus.
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Openframe definition:
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There is only one area which is the User Project, with a wrapper
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to take a drop-in module.
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The openframe module contains clocking, DLL, user ID, housekeeping
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SPI, POR, and GPIO control. Operation is essentially the same as
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the above (harness definition).
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MPW-one compatibility:
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Looks like the harness, but the logic analyzer and management-
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protect is part of the harness and the user area wrapper matches
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that for MPW-one.
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MPW-two compatibility:
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Looks like the harness, but the logic analyzer and management-
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protect is part of the harness and the user area wrapper matches
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that for MPW-two.
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Caravel-pico definition:
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Caravel-pico is a version of the PicoRV32 Management SoC from
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MPW-two, but without the GPIO control, clocking control, DLL,
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housekeeping SPI, and logic analyzer. It mainly just exports
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the Wishbone bus interface to the user project area.
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Pinouts for Caravel (any version)
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----------------------------------------------
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Power supplies:
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vddio, vssio, vdda, vssa, vccd, vssd,
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vdda1, vdda2, vssa1, vssa2,
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vccd1, vccd2, vssd1, vssd2
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Management SoC signals:
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debug (or JTAG, management)
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gpio
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clock
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resetb
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flash_csb
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flash_clk
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flash_io0
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flash_io1
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User area signals:
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mprj_io[37:0]
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User project area pinout (openframe)
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----------------------------------------------
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Power supplies:
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vddio, vssio, vdda, vssa, vccd, vssd,
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vdda1, vdda2, vssa1, vssa2,
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vccd1, vccd2, vssd1, vssd2
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Wishbone bus (exported to SPI):
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wb_clk_i
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wb_rst_i
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wbs_stb_i
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wbs_cyc_i
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wbs_we_i
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wbs_sel_i[3:0]
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wbs_dat_i[31:0]
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wbs_adr_i[31:0]
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wbs_ack_o
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wbs_dat_o[31:0]
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GPIO:
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io_in[37:0]
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io_out[37:0]
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io_oeb[37:0]
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GPIO (single):
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gpio_out
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gpio_in
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gpio_oeb
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gpio_ieb
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Flash controller:
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flash_clk
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flash_clk_oeb
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flash_csb
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flash_csb_oeb
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flash_io0_do
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flash_io1_do
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flash_io2_do
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flash_io3_do
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flash_io0_di
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flash_io1_di
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flash_io2_di
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flash_io3_di
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flash_io0_oeb
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flash_io1_oeb
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flash_io2_oeb
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flash_io3_oeb
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flash_io0_ieb
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flash_io1_ieb
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flash_io2_ieb
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flash_io3_ieb
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Essentials:
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resetb
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core_clk
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Miscellaneous:
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user_clock2
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user_irq[2:0]
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User project area pinout (harness)
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----------------------------------------------
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Power supplies:
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vdda1, vdda2, vssa1, vssa2,
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vccd1, vccd2, vssd1, vssd2
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Wishbone bus:
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wb_clk_i
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wb_rst_i
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wbs_stb_i
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wbs_cyc_i
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wbs_we_i
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wbs_sel_i[3:0]
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wbs_dat_i[31:0]
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wbs_adr_i[31:0]
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wbs_ack_o
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wbs_dat_o[31:0]
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GPIO:
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io_in[37:0]
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io_out[37:0]
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io_oeb[37:0]
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Miscellaneous:
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user_clock2
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user_irq[2:0]
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Management SoC pinout
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----------------------------------------------
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GPIO:
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gpio_out
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gpio_in
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gpio_oeb
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gpio_ieb
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Flash controller:
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flash_clk
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flash_csb
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flash_io0_do
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flash_io1_do
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flash_io2_do
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flash_io3_do
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flash_io0_di
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flash_io1_di
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flash_io2_di
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flash_io3_di
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flash_io0_oeb
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flash_io1_oeb
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flash_io2_oeb
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flash_io3_oeb
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Essentials:
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resetb
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core_clk
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Wishbone bus:
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mprj_ack_i
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mprj_dat_i[31:0]
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mprj_dat_o[31:0]
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mprj_cyc_o
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mprj_stb_o
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mprj_we_o
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mprj_sel_o[3:0]
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mprj_adr_o[31:0]
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Interface pinout (standard = pass-through)
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----------------------------------------------
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Clocking (DLL)
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clock
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porb
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resetb
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core_clk
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Housekeeping SPI
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SCK
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CSB
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SDI
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SDO
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sdo_enb
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Flash pass-through:
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flash_clk_oeb
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flash_csb_oeb
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flash_io0_ieb
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flash_io1_ieb
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flash_io2_ieb
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flash_io3_ieb
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(plus management flash signals in from SoC/out to pads)
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Wishbone bus:
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mprj_ack_i
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mprj_dat_i[31:0]
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mprj_dat_o[31:0]
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mprj_cyc_o
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mprj_stb_o
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mprj_we_o
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mprj_sel_o[3:0]
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mprj_adr_o[31:0]
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User ID programming
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mask_rev[31:0]
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Interface pinout (MPW-one compatibility level)
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----------------------------------------------
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Clocking (DLL)
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clock
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porb
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resetb
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core_clk
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GPIO controller
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serial_data
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serial_clock
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serial_reset
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Housekeeping SPI
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SCK
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CSB
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SDI
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SDO
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sdo_enb
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Flash pass-through:
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flash_clk_oeb
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flash_csb_oeb
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flash_io0_ieb
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flash_io1_ieb
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flash_io2_ieb
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flash_io3_ieb
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(plus management flash signals in from SoC/out to pads)
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Wishbone bus:
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mprj_ack_i
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mprj_dat_i[31:0]
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mprj_dat_o[31:0]
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mprj_cyc_o
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mprj_stb_o
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mprj_we_o
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mprj_sel_o[3:0]
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mprj_adr_o[31:0]
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User ID programming
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mask_rev[31:0]
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Logic Analyzer
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la_io[127:0]
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la_oenb[127:0]
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Interface pinout (MPW-two compatibility level)
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----------------------------------------------
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Clocking (DLL)
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clock
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porb
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resetb
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core_clk
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GPIO controller
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serial_data
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serial_clock
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serial_reset
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Housekeeping SPI
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SCK
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CSB
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SDI
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SDO
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sdo_enb
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Wishbone bus:
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mprj_ack_i
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mprj_dat_i[31:0]
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mprj_dat_o[31:0]
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mprj_cyc_o
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mprj_stb_o
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mprj_we_o
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mprj_sel_o[3:0]
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mprj_adr_o[31:0]
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User ID programming
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mask_rev[31:0]
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Logic Analyzer
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la_input[127:0]
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la_output[127:0]
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la_oenb[127:0]
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la_iena[127:0]
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