mirror of https://github.com/efabless/caravel.git
259 lines
16 KiB
Python
259 lines
16 KiB
Python
import random
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import cocotb
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from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
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import cocotb.log
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from interfaces.cpu import RiskV
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from interfaces.defsParser import Regs
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from cocotb.result import TestSuccess
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from tests.common_functions.test_functions import *
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from tests.bitbang.bitbang_functions import *
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from interfaces.caravel import GPIO_MODE
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reg = Regs()
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@cocotb.test()
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@repot_test
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async def bitbang_no_cpu_all_o(dut):
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caravelEnv,clock = await test_configure(dut,timeout_cycles=10206)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_37'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_36'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_35'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_34'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_33'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_32'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_31'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_30'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_29'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_28'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_27'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_26'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_25'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_24'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_23'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_22'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_21'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_20'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_19'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_18'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_17'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_16'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_15'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_14'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_13'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_12'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_11'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_10'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_9'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_8'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_7'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_6'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_5'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_4'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_3'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_2'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_1'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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#Configure all as output except reg_mprj_io_3
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await clear_registers(cpu)
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await clock_in_right_o_left_o_standard(cpu,0) # 18 and 19
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await clock_in_right_o_left_o_standard(cpu,0) # 17 and 20
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await clock_in_right_o_left_o_standard(cpu,0) # 16 and 21
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await clock_in_right_o_left_o_standard(cpu,0) # 15 and 22
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await clock_in_right_o_left_o_standard(cpu,0) # 14 and 23
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await clock_in_right_o_left_o_standard(cpu,0) # 13 and 24
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await clock_in_right_o_left_o_standard(cpu,0) # 12 and 25
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await clock_in_right_o_left_o_standard(cpu,0) # 11 and 26
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await clock_in_right_o_left_o_standard(cpu,0) # 10 and 27
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await clock_in_right_o_left_o_standard(cpu,0) # 9 and 28
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await clock_in_right_o_left_o_standard(cpu,0) # 8 and 29
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await clock_in_right_o_left_o_standard(cpu,0) # 7 and 30
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await clock_in_right_o_left_o_standard(cpu,0) # 6 and 31
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await clock_in_right_o_left_o_standard(cpu,0) # 5 and 32
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await clock_in_right_o_left_o_standard(cpu,0) # 4 and 33
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await clock_in_right_o_left_i_standard(cpu,0) # 3 and 34
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await clock_in_right_o_left_i_standard(cpu,0) # 2 and 35
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await clock_in_right_o_left_i_standard(cpu,0) # 1 and 36
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await clock_in_end_output(cpu) # 0 and 37 and load
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await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),0x0)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0)
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i= 0x20
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for j in range(5):
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await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),i)
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cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} int {caravelEnv.monitor_gpio((37,4)).integer} i = {i}')
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if caravelEnv.monitor_gpio((37,4)).integer != i << 28:
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cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,4))} instead of {bin(i << 28)}')
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# for k in range(250):
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await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0)
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if caravelEnv.monitor_gpio((37,4)).integer != 0:
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cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}')
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i = i >> 1
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i |= 0x20
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await ClockCycles(caravelEnv.clk, 1)
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i= 0x80000000
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for j in range(32):
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await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x3f)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),i)
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if caravelEnv.monitor_gpio((37,32)).integer != 0x3f:
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cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)}')
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if caravelEnv.monitor_gpio((31,4)).integer != i>>4 :
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cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,4))} instead of {i>>4}')
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cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} type {int(caravelEnv.monitor_gpio((37,4)))} i = {i}')
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await ClockCycles(caravelEnv.clk, 1)
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# await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),0x0)
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await ClockCycles(caravelEnv.clk, 1)
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if caravelEnv.monitor_gpio((37,4)).integer != 0:
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cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}')
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i = i >> 1
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i |= 0x80000000
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await ClockCycles(caravelEnv.clk, 1000)
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@cocotb.test()
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@repot_test
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async def bitbang_no_cpu_all_i(dut):
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caravelEnv,clock = await test_configure(dut,timeout_cycles=8005)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_37'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_36'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_35'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_34'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_33'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_32'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_31'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_30'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_29'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_28'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_27'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_26'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_25'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_24'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_23'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_22'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_21'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_20'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_19'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_18'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_17'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_16'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_15'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_14'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_13'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_12'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_11'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_10'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_9'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_8'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_7'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_6'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_5'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_4'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_3'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_2'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_1'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
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#Configure all as input except reg_mprj_io_3
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await clear_registers(cpu)
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await clock_in_right_i_left_i_standard(cpu,0) # 18 and 19
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await clock_in_right_i_left_i_standard(cpu,0) # 17 and 20
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await clock_in_right_i_left_i_standard(cpu,0) # 16 and 21
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await clock_in_right_i_left_i_standard(cpu,0) # 15 and 22
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await clock_in_right_i_left_i_standard(cpu,0) # 14 and 23
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await clock_in_right_i_left_i_standard(cpu,0) # 13 and 24
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await clock_in_right_i_left_i_standard(cpu,0) # 12 and 25
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await clock_in_right_i_left_i_standard(cpu,0) # 11 and 26
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await clock_in_right_i_left_i_standard(cpu,0) # 10 and 27
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await clock_in_right_i_left_i_standard(cpu,0) # 9 and 28
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await clock_in_right_i_left_i_standard(cpu,0) # 8 and 29
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await clock_in_right_i_left_i_standard(cpu,0) # 7 and 30
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await clock_in_right_i_left_i_standard(cpu,0) # 6 and 31
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await clock_in_right_i_left_i_standard(cpu,0) # 5 and 32
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await clock_in_right_i_left_i_standard(cpu,0) # 4 and 33
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await clock_in_right_i_left_i_standard(cpu,0) # 3 and 34
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await clock_in_right_i_left_i_standard(cpu,0) # 2 and 35
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await clock_in_right_i_left_i_standard(cpu,0) # 1 and 36
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await clock_in_right_i_left_i_standard(cpu,0) # 0 and 37
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await load(cpu) # load
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caravelEnv.drive_gpio_in((31,0),0x8F66FD7B)
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await ClockCycles(caravelEnv.clk, 100)
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reg_mprj_datal = await cpu.read_address(reg.get_addr('reg_mprj_datal'))
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# value_masked = reg_mprj_datal & mask_input
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if reg_mprj_datal == 0x8F66FD7B:
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cocotb.log.info(f'[TEST] Passed with value 0x8F66FD7B')
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else:
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cocotb.log.error(f'[TEST] fail with value mprj = {bin(reg_mprj_datal)} instead of {bin(0x8F66FD7B)}')
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await ClockCycles(caravelEnv.clk, 100)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x1B)
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x = caravelEnv.monitor_gpio((37,32))
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print(f"xxxxxxxx {x}")
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await ClockCycles(caravelEnv.clk, 100)
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caravelEnv.drive_gpio_in((31,0),0xFFA88C5A)
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await ClockCycles(caravelEnv.clk, 100)
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reg_mprj_datal = await cpu.read_address(reg.get_addr('reg_mprj_datal'))
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# value_masked = reg_mprj_datal & mask_input
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if reg_mprj_datal == 0xFFA88C5A:
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cocotb.log.info(f'[TEST] Passed with value 0xFFA88C5A')
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else:
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cocotb.log.error(f'[TEST] fail with value mprj = {bin(reg_mprj_datal)} instead of {bin(0xFFA88C5A)}')
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await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x2B)
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await ClockCycles(caravelEnv.clk, 100)
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caravelEnv.drive_gpio_in((31,0),0xC9536346)
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await ClockCycles(caravelEnv.clk, 100)
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reg_mprj_datal = await cpu.read_address(reg.get_addr('reg_mprj_datal'))
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# value_masked = reg_mprj_datal & mask_input
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if reg_mprj_datal == 0xC9536346:
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cocotb.log.info(f'[TEST] Passed with value 0xC9536346')
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else:
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cocotb.log.error(f'[TEST] fail with value mprj = {bin(reg_mprj_datal)} instead of {bin(0xC9536346)}')
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await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x3B)
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await ClockCycles(caravelEnv.clk, 100)
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"""Testbench of GPIO configuration through bit-bang method using the housekeeping SPI."""
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@cocotb.test()
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@repot_test
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async def io_ports(dut):
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caravelEnv,clock = await test_configure(dut)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_1'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_2'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_3'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_4'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_5'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_6'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_io_7'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
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|
|
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# Apply configuration
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await cpu.drive_data2address(reg.get_addr('reg_mprj_xfer'),1)
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|
|
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while True:
|
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if await cpu.read_address(reg.get_addr('reg_mprj_xfer')) != 1 :
|
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break
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