mirror of https://github.com/efabless/caravel.git
171 lines
10 KiB
Tcl
171 lines
10 KiB
Tcl
if {\
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[catch {
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##PT script
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# Adding SCL and IO link libraries based on the PDK and process corner specified
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if {[string match gf180* $::env(PDK)]} {
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source ./gf180_libs.tcl
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} elseif {[string match sky130* $::env(PDK)]} {
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source ./sky130_libs.tcl
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}
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# Reading design netlist
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set search_path "$::env(CARAVEL_ROOT)/verilog/gl $::env(MCW_ROOT)/verilog/gl $::env(UPRJ_ROOT)/verilog/gl"
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if {$::env(UPRJ_ROOT) == $::env(CARAVEL_ROOT)} {
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set verilogs [concat [glob $::env(CARAVEL_ROOT)/verilog/gl/*.v]]
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} elseif {$::env(MCW_ROOT) == $::env(CARAVEL_ROOT)} {
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set verilogs [concat [glob $::env(CARAVEL_ROOT)/verilog/gl/*.v] \
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[glob $::env(UPRJ_ROOT)/verilog/gl/*.v]]
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} elseif {$::env(UPRJ_ROOT) == $::env(CARAVEL_ROOT)} {
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set verilogs [concat [glob $::env(CARAVEL_ROOT)/verilog/gl/*.v] \
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[glob $::env(MCW_ROOT)/verilog/gl/*.v]]
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} else {
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set verilogs [concat [glob $::env(CARAVEL_ROOT)/verilog/gl/*.v] \
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[glob $::env(MCW_ROOT)/verilog/gl/*.v] \
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[glob $::env(UPRJ_ROOT)/verilog/gl/*.v]]
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}
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set verilog_exceptions [concat [glob $::env(CARAVEL_ROOT)/verilog/gl/*-signoff.v] \
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[glob $::env(CARAVEL_ROOT)/verilog/gl/__*.v]]
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# remove empty wrapper when including non-empty wrapper only
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if {!($::env(UPW))} {
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if {$::env(DESIGN) == $::env(CHIP_CORE) || $::env(DESIGN) == $::env(CHIP)} {
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set verilogs [concat $verilogs "$::env(CARAVEL_ROOT)/verilog/gl/__user_project_wrapper.v"]
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set verilogs [concat $verilogs "$::env(CARAVEL_ROOT)/verilog/gl/__user_analog_project_wrapper.v"]
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set verilog_exceptions [concat $verilog_exceptions "$::env(UPRJ_ROOT)/verilog/gl/user_project_wrapper.v"]
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set verilog_exceptions [concat $verilog_exceptions "$::env(UPRJ_ROOT)/verilog/gl/user_analog_project_wrapper.v"]
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}
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}
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foreach verilog_exception $verilog_exceptions {
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puts "verilog exception: $verilog_exception"
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set match_idx [lsearch $verilogs $verilog_exception]
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if {$match_idx} {
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puts "removing $verilog_exception from verilogs list"
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set verilogs [lreplace $verilogs $match_idx $match_idx]
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}
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}
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puts "list of verilog files:"
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foreach verilog $verilogs {
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puts $verilog
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read_verilog $verilog
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}
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current_design $::env(DESIGN)
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link
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# Reading constraints (signoff)
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read_sdc $::env(ROOT)/signoff/$::env(DESIGN)/$::env(DESIGN).sdc
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# debug interface input for swift
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if {$::env(DEBUG) && $::env(DESIGN) == $::env(CHIP)} {
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reset_path -from [get_ports mprj_io[0]]
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}
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# Reading parasitics based on the RC corner specified
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proc read_spefs {design rc_corner} {
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if {[string match gf180* $::env(PDK)]} {
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source ./gf180_spef_mapping.tcl
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} elseif {[string match sky130* $::env(PDK)]} {
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source ./sky130_spef_mapping.tcl
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}
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foreach key [array names spef_mapping] {
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read_parasitics -keep_capacitive_coupling -path $key $spef_mapping($key)
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}
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# add -complete_with wlm to let PT complete incomplete RC networks at the top-level
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read_parasitics -keep_capacitive_coupling $::env(ROOT)/signoff/${design}/openlane-signoff/spef/${design}.${rc_corner}.spef -pin_cap_included
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# read_parasitics -keep_capacitive_coupling $::env(ROOT)/signoff/${design}/openlane-signoff/spef/${design}.${rc_corner}.spef -pin_cap_included -complete_with wlm
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}
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proc report_results {design rc_corner proc_corner} {
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report_global_timing -separate_all_groups -significant_digits 4 > $::env(OUT_DIR)/reports/${proc_corner}${proc_corner}/${design}.${rc_corner}-global.rpt
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report_analysis_coverage -significant_digits 4 -nosplit -status_details {untested} > $::env(OUT_DIR)/reports/${proc_corner}${proc_corner}/${design}.${rc_corner}-coverage.rpt
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report_constraint -all_violators -significant_digits 4 -nosplit > $::env(OUT_DIR)/reports/${proc_corner}${proc_corner}/${design}.${rc_corner}-all_viol.rpt
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report_timing -unique_pins -delay min -path_type full_clock_expanded -transition_time -capacitance -nets -crosstalk_delta -derate -nosplit \
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-max_paths 1000 -slack_lesser_than 10 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${proc_corner}${proc_corner}/${design}.${rc_corner}-min_timing.rpt
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report_timing -unique_pins -delay max -path_type full_clock_expanded -transition_time -capacitance -nets -crosstalk_delta -derate -nosplit \
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-max_paths 1000 -slack_lesser_than 20 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${proc_corner}${proc_corner}/${design}.${rc_corner}-max_timing.rpt
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report_si_bottleneck -significant_digits 4 -nosplit -slack_lesser_than 10 -all_nets > $::env(OUT_DIR)/reports/${proc_corner}${proc_corner}/${design}.${rc_corner}-si_bottleneck.rpt
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if {$design == $::env(CHIP) | $design == $::env(CHIP_CORE)} {
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if {$::env(UPW) && $design == $::env(CHIP)} {
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report_timing -unique_pins -delay min -through [get_cells chip_core/mprj] -path_type full_clock_expanded -transition_time -capacitance -nets -crosstalk_delta -derate -nosplit \
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-max_paths 1000 -slack_lesser_than 100 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${proc_corner}${proc_corner}/${design}.${rc_corner}-mprj-min_timing.rpt
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report_timing -unique_pins -delay max -through [get_cells chip_core/mprj] -path_type full_clock_expanded -transition_time -capacitance -nets -crosstalk_delta -derate -nosplit \
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-max_paths 1000 -slack_lesser_than 100 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${proc_corner}${proc_corner}/${design}.${rc_corner}-mprj-max_timing.rpt
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}
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if {$::env(DEBUG)} {
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report_timing -unique_pins -delay min -path_type full_clock_expanded -transition_time -capacitance -nets -crosstalk_delta -derate -nosplit -group debug_clk \
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-max_paths 1000 -slack_lesser_than 10 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${proc_corner}${proc_corner}/${design}.${rc_corner}-debug_clk-min_timing.rpt
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report_timing -unique_pins -delay max -path_type full_clock_expanded -transition_time -capacitance -nets -crosstalk_delta -derate -nosplit -group debug_clk \
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-max_paths 1000 -slack_lesser_than 10 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${proc_corner}${proc_corner}/${design}.${rc_corner}-debug_clk-max_timing.rpt
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} else {
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report_timing -unique_pins -delay max -path_type full_clock_expanded -transition_time -capacitance -nets -crosstalk_delta -derate -nosplit -group hkspi_clk \
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-max_paths 1000 -slack_lesser_than 10 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${proc_corner}${proc_corner}/${design}.${rc_corner}-hkspi_clk-max_timing.rpt
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report_timing -unique_pins -delay min -path_type full_clock_expanded -transition_time -capacitance -nets -crosstalk_delta -derate -nosplit -group hkspi_clk \
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-max_paths 1000 -slack_lesser_than 10 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${proc_corner}${proc_corner}/${design}.${rc_corner}-hkspi_clk-min_timing.rpt
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}
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report_timing -unique_pins -delay min -path_type full_clock_expanded -transition_time -capacitance -nets -crosstalk_delta -derate -nosplit -group clk \
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-max_paths 1000 -slack_lesser_than 10 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${proc_corner}${proc_corner}/${design}.${rc_corner}-clk-min_timing.rpt
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report_timing -unique_pins -delay max -path_type full_clock_expanded -transition_time -capacitance -nets -crosstalk_delta -derate -nosplit -group clk \
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-max_paths 1000 -slack_lesser_than 10 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${proc_corner}${proc_corner}/${design}.${rc_corner}-clk-max_timing.rpt
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report_timing -unique_pins -delay min -path_type full_clock_expanded -transition_time -capacitance -nets -crosstalk_delta -derate -nosplit -group hk_serial_clk \
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-max_paths 1000 -slack_lesser_than 10 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${proc_corner}${proc_corner}/${design}.${rc_corner}-hk_serial_clk-min_timing.rpt
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report_timing -unique_pins -delay max -path_type full_clock_expanded -transition_time -capacitance -nets -crosstalk_delta -derate -nosplit -group hk_serial_clk \
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-max_paths 1000 -slack_lesser_than 10 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${proc_corner}${proc_corner}/${design}.${rc_corner}-hk_serial_clk-max_timing.rpt
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report_case_analysis -nosplit > $::env(OUT_DIR)/reports/${design}.case_analysis.rpt
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report_exceptions -nosplit > $::env(OUT_DIR)/reports/${design}.false_paths.rpt
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}
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if {$::env(REPORTS_ONLY) == 0} {
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write_sdf -compress gzip $::env(OUT_DIR)/sdf/${proc_corner}${proc_corner}/${design}.${rc_corner}.sdf.gz
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# Extract timing model
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set extract_model_clock_transition_limit 0.75
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set extract_model_data_transition_limit 0.75
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set_app_var extract_model_capacitance_limit 1.0
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set extract_model_num_capacitance_points 7
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set extract_model_num_clock_transition_points 7
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set extract_model_num_data_transition_points 7
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set extract_model_use_conservative_current_slew true
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set extract_model_enable_report_delay_calculation true
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set extract_model_with_clock_latency_arcs true
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# remove boundary constraints
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reset_timing_derate
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remove_input_delay [all_inputs]
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remove_output_delay [all_outputs]
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remove_capacitance [all_outputs]
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extract_model -output $::env(OUT_DIR)/lib/${proc_corner}${proc_corner}/${design}.${rc_corner} -format {lib}
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}
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}
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# set timing_report_unconstrained_paths TRUE
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set parasitics_log_file $::env(OUT_DIR)/logs/$::env(RC_CORNER)-parasitics.log
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set si_enable_analysis TRUE
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# set si_enable_analysis FALSE
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set sh_message_limit 1500
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read_spefs $::env(DESIGN) $::env(RC_CORNER)
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set parasitics_log_file $::env(OUT_DIR)/logs/$::env(RC_CORNER)-unannotated.log
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report_annotated_parasitics -list_not_annotated -max_nets 5000
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update_timing
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report_results $::env(DESIGN) $::env(RC_CORNER) $::env(PROC_CORNER)
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exit
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} err]
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} {
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puts stderr $err
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exit 1
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} |