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riscv
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caravel
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e6c6f3e22b
caravel
/
verilog
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mo-hosni
e25997cc3b
swapped the left `vssd` and `vccd` rings in `caravan_core` to fix an LVS issue
2023-05-30 22:33:33 -07:00
..
dv
Update cocotb README file to include PDK export requirements
2022-10-30 01:47:46 -07:00
gl
swapped the left `vssd` and `vccd` rings in `caravan_core` to fix an LVS issue
2023-05-30 22:33:33 -07:00
rtl
add `/// sta-blackbox` in the modules that will be blackboxed in STA
2023-05-22 05:52:27 -07:00
stubs
[DATA] Add spare_logic_block
2021-11-24 20:36:23 +02:00