mirror of https://github.com/efabless/caravel.git
84 lines
2.8 KiB
Bash
Executable File
84 lines
2.8 KiB
Bash
Executable File
#!/bin/bash
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#
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# Run LVS on the Openframe layout and verilog.
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# If the layout netlist does not exist, then generate it from the
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# extracted .mag layout of the caravel_openframe top level. The
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# LVS script for netgen will read both top level netlists and then
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# compare the padframe cell.
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#
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# Run this script in the mag/ directory.
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#
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echo ${PDK_ROOT:=/usr/share/pdk} > /dev/null
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echo ${PDK:=sky130A} > /dev/null
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if [ ! -f caravel_openframe.spice ]; then
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magic -dnull -noconsole -rcfile $PDK_ROOT/$PDK/libs.tech/magic/$PDK.magicrc << EOF
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drc off
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crashbackups stop
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load caravel_openframe
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select top cell
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expand
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extract do local
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# Maybe not do parasitic extraction for LVS??
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extract no all
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extract all
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ext2spice lvs
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ext2spice
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EOF
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rm -f *.ext
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fi
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# Set the USE_POWER_PINS definition, which is not set anywhere else.
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cat > local_defs.v << EOF
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\`define USE_POWER_PINS 1
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EOF
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# Generate script for netgen
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cat > netgen.tcl << EOF
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# Load top level netlists
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puts stdout "Reading layout netlist:"
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set circuit1 [readnet spice caravel_openframe.spice]
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puts stdout "Reading verilog and schematic netlists:"
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puts stdout "Reading SPICE netlists of I/O:"
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set circuit2 [readnet spice $PDK_ROOT/$PDK/libs.ref/sky130_fd_io/spice/sky130_fd_io.spice]
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readnet spice $PDK_ROOT/$PDK/libs.ref/sky130_fd_io/cdl/sky130_ef_io.cdl \$circuit2
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readnet spice $PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice \$circuit2
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readnet spice $PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice \$circuit2
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readnet spice $PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice \$circuit2
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readnet spice ../xschem/simple_por.spice \$circuit2
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puts stdout "Reading all gate-level verilog submodules:"
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readnet verilog local_defs.v \$circuit2
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readnet verilog ../verilog/rtl/defines.v \$circuit2
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readnet verilog ../verilog/rtl/pads.v \$circuit2
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# NOTE: __openframe_project_wrapper.v is empty.
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readnet verilog ../verilog/rtl/__openframe_project_wrapper.v \$circuit2
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readnet verilog ../verilog/gl/user_id_programming.v \$circuit2
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readnet verilog ../verilog/gl/constant_block.v \$circuit2
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readnet verilog ../verilog/gl/xres_buf.v \$circuit2
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# ALSO NOTE: Top-level modules are in the RTL directory but are purely gate level.
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readnet verilog ../verilog/rtl/chip_io_openframe.v \$circuit2
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readnet verilog ../verilog/rtl/caravel_openframe.v \$circuit2
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puts stdout "Done reading netlists."
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# Temporary: Flatten the user project wrapper in the verilog netlist (better solution is to
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# abstract the user project wrapper in the layout and re-extract).
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flatten class "\$circuit2 openframe_project_wrapper"
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# Run LVS on the chip_io_openframe cells in layout and verilog.
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lvs "\$circuit1 caravel_openframe" "\$circuit2 caravel_openframe" \
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$PDK_ROOT/$PDK/libs.tech/netgen/${PDK}_setup.tcl \
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caravel_openframe_comp.out
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EOF
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export NETGEN_COLUMNS=60
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netgen -batch source netgen.tcl
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rm local_defs.v
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rm netgen.tcl
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