caravel/verilog/rtl
Tim Edwards e6169aaf8c Copied files from the original pull request into a new one. Includes
a few layout updates since the original pull request.  The openframe
design matches the user example in caravel_openframe_project.
2023-05-08 16:29:24 -04:00
..
__openframe_project_wrapper.v Copied files from the original pull request into a new one. Includes 2023-05-08 16:29:24 -04:00
__uprj_analog_netlists.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
__uprj_netlists.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
__user_analog_project_wrapper.v cocotb - updates related to enable simulating caraval using iverilog (#320) 2022-10-21 07:43:34 -07:00
__user_project_gpio_example.v Add gpio_all_bidir_user test 2022-10-10 15:59:20 -07:00
__user_project_la_example.v add test la test 2022-10-08 06:25:26 -07:00
__user_project_wrapper.v fix bug of wrapper ack 2022-10-11 06:02:44 -07:00
buff_flash_clkrst.v connected rest of buffers to power 2022-10-17 01:15:46 +02:00
caravan.v fixed documentation for gpio's used in caravan 2022-11-11 08:22:20 -08:00
caravan_netlists.v Added buffers to the top level, inside a macro called 2022-10-13 13:29:27 -04:00
caravan_openframe.v Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped" 2021-10-31 21:43:09 -04:00
caravan_power_routing.v Caravan redesign (#321) 2022-10-21 07:37:41 -07:00
caravel.v reharden caravel. 2023-02-27 10:39:51 -08:00
caravel_clocking.v update caravel rtl/hierarchy: 2023-02-26 13:43:37 +02:00
caravel_core.v update caravel rtl/hierarchy: 2023-02-26 13:43:37 +02:00
caravel_logo.v reharden: caravel 2022-10-16 15:44:27 -07:00
caravel_motto.v reharden: caravel 2022-10-16 15:44:27 -07:00
caravel_netlists.v Added buffers to the top level, inside a macro called 2022-10-13 13:29:27 -04:00
caravel_openframe.v Copied files from the original pull request into a new one. Includes 2023-05-08 16:29:24 -04:00
caravel_power_routing.v reharden!: caravel 2022-10-10 04:51:05 -07:00
chip_io.v some rtl changes 2022-10-10 05:13:48 -07:00
chip_io_alt.v Caravan redesign (#321) 2022-10-21 07:37:41 -07:00
chip_io_openframe.v Copied files from the original pull request into a new one. Includes 2023-05-08 16:29:24 -04:00
clock_div.v Fixed one bad error in clock_div which had been done without my 2021-12-06 21:37:51 -05:00
constant_block.v Modified the GPIO control block to buffer the constant high/low outputs. 2022-09-20 17:49:08 -04:00
copyright_block.v reharden: caravel 2022-10-16 15:44:27 -07:00
debug_regs.v Add gpio_all_o_user test 2022-10-09 07:53:25 -07:00
defines.v Copied files from the original pull request into a new one. Includes 2023-05-08 16:29:24 -04:00
digital_pll.v reharden!: digital_pll 2022-10-17 10:56:01 -07:00
digital_pll_controller.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
empty_macro.v Add empty_macro which acts as a placement obstruction. 2023-02-27 08:14:55 -08:00
gpio_control_block.v update caravel rtl/hierarchy: 2023-02-26 13:43:37 +02:00
gpio_defaults_block.v Fix issues with port definitions 2023-01-05 20:53:17 +11:00
gpio_logic_high.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
gpio_signal_buffering.v bugfix: remove extra comma after the last port in the decaps declaration 2022-11-07 13:00:00 +02:00
gpio_signal_buffering_alt.v bugfix: remove extra comma after the last port in the decaps declaration 2022-11-07 13:00:00 +02:00
housekeeping.v Merge pull request #391 from efabless/fix_housekeeping_serial_fsm 2023-01-05 22:19:18 -08:00
housekeeping_spi.v Syntax changes that are non-functional from a synthesis perspective. (#324) 2022-10-21 10:10:20 -07:00
manual_power_connections.v Added manual_power_connections. 2023-02-27 08:15:35 -08:00
mgmt_protect.v Fix issues with port definitions 2023-01-05 20:53:17 +11:00
mgmt_protect_hv.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
mprj2_logic_high.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
mprj_io.v Fix typo at mprj_io (#168) 2022-10-10 12:11:05 -07:00
mprj_io_buffer.v update caravel rtl/hierarchy: 2023-02-26 13:43:37 +02:00
mprj_logic_high.v Revised the management protect block to include protections against 2021-10-27 19:36:43 -04:00
open_source.v reharden: caravel 2022-10-16 15:44:27 -07:00
openframe_netlists.v Copied files from the original pull request into a new one. Includes 2023-05-08 16:29:24 -04:00
pads.v Modified the GPIO control block to buffer the constant high/low outputs. 2022-09-20 17:49:08 -04:00
ring_osc2x13.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
simple_por.v Modified simple_por.v RTL to avoid the wire declaration that "cvc" 2021-12-08 12:16:19 -05:00
spare_logic_block.v Fix issues with port definitions 2023-01-05 20:53:17 +11:00
user_defines.v Fixes the user defines configuration values for pullup and pulldown 2022-11-16 09:36:01 -05:00
user_id_programming.v Fix issues with port definitions 2023-01-05 20:53:17 +11:00
user_id_textblock.v reharden: caravel 2022-10-16 15:44:27 -07:00
xres_buf.v Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped" 2021-10-31 21:43:09 -04:00