riscv
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caravel
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caravel/verilog/dv
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Tim Edwards 1526214cc1 Modifications to some of the Makefiles to make the specific RISC-V 
architecture type passed to gcc as the value to the '-march='
option an environment variable, setting that environment variable
to "rv32imc" by default, and overriding it with "rv32ic" specifically
for the new caravel_pico without the multiplier and divider option,
on testbenches "mem" and "storage" which both have multiplies in the
C code.
 		2021-12-24 13:42:36 -05:00
..
caravel Modifications to some of the Makefiles to make the specific RISC-V 2021-12-24 13:42:36 -05:00
wb_utests Corrected the two failing testbenches (which needed fixing because 2021-10-28 22:20:46 -04:00
README.md adding user_project_wrapper empty files -- gds & lef 2021-12-16 12:29:35 -08:00
dummy_slave.v adding user_project_wrapper empty files -- gds & lef 2021-12-16 12:29:35 -08:00

README.md

DV Tests

Organized into two subdirectories:

  • caravel: contains tests for both the mangement SoC and an example user project.
  • wb_utests: contains unit tests for the wishbone components residing at the management SoC private bus
├── caravel
│   ├── mgmt_soc
│   ├── user_proj_example
└── wb_utests