mirror of https://github.com/efabless/caravel.git
51 lines
2.1 KiB
Python
51 lines
2.1 KiB
Python
import random
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import cocotb
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from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
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import cocotb.log
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from interfaces.cpu import RiskV
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from interfaces.defsParser import Regs
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from cocotb.result import TestSuccess
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from tests.common_functions.test_functions import *
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from tests.bitbang.bitbang_functions import *
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from interfaces.caravel import GPIO_MODE
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reg = Regs()
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"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI."""
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@cocotb.test()
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@repot_test
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async def IRQ_timer(dut):
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caravelEnv,clock = await test_configure(dut,timeout_cycles=166519)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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cpu.cpu_release_reset()
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cocotb.log.info(f"[TEST] Start IRQ_timer test")
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pass_list = (0x1B,0x2B)
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fail_list = (0x1E,0x2E)
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phases_fails = 2
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phases_passes = 0
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reg1 =0 # buffer
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while True:
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if cpu.read_debug_reg2() == 0xFF: # test finish
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break
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if reg1 != cpu.read_debug_reg1():
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reg1 = cpu.read_debug_reg1()
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if reg1 in pass_list: # pass phase
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phases_passes +=1
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phases_fails -=1
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if reg1 == 0x1B:
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cocotb.log.info(f"[TEST] Pass interrupt is detected when timer is used")
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elif reg1 == 0x2B:
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cocotb.log.info(f"[TEST] Pass interrupt isn't detected when timer isnt used")
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elif reg1 in fail_list: # pass phase
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if reg1 == 0x1E:
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cocotb.log.info(f"[TEST] Failed interrupt isn't detected when timer is used")
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elif reg1 == 0x2E:
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cocotb.log.error(f"[TEST] Failed interrupt is detected when timer isnt used")
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else:
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cocotb.log.error(f"[TEST] debug register 1 has illegal value")
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await ClockCycles(caravelEnv.clk,10)
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if phases_fails != 0:
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cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
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else:
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cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") |