caravel/verilog
Kareem Farid d14035d8a2 gpio_signal_buffering rtl decaps
+ add sky130_ef_sc_hd__decap_12 decaps in the rtl of gpio_signal_buffering
+ add sky130_ef_sc_hd__decap_12 stub file for openlane; there is no
yosys-parseable verilog model for sky130_ef_sc_hd__decap_12
~ change config of gpio_signal_buffering* to add sky130_ef_sc_hd__decap_12
~ regenerate the gl netlist based on the above changes
2022-11-01 19:16:53 +02:00
..
dv Update cocotb README file to include PDK export requirements 2022-10-30 01:47:46 -07:00
gl gpio_signal_buffering rtl decaps 2022-11-01 19:16:53 +02:00
rtl gpio_signal_buffering rtl decaps 2022-11-01 19:16:53 +02:00
stubs [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00