mirror of https://github.com/efabless/caravel.git
49 lines
1.5 KiB
Verilog
Executable File
49 lines
1.5 KiB
Verilog
Executable File
// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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`default_nettype none
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module dummy_slave(
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input wb_clk_i,
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input wb_rst_i,
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input wb_stb_i,
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input wb_cyc_i,
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input wb_we_i,
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input [3:0] wb_sel_i,
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input [31:0] wb_adr_i,
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input [31:0] wb_dat_i,
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output reg [31:0] wb_dat_o,
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output reg wb_ack_o
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);
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reg [31:0] store;
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wire valid = wb_cyc_i & wb_stb_i;
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always @(posedge wb_clk_i) begin
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if (wb_rst_i == 1'b 1) begin
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wb_ack_o <= 1'b 0;
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end else begin
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if (wb_we_i == 1'b 1) begin
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if (wb_sel_i[0]) store[7:0] <= wb_dat_i[7:0];
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if (wb_sel_i[1]) store[15:8] <= wb_dat_i[15:8];
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if (wb_sel_i[2]) store[23:16] <= wb_dat_i[23:16];
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if (wb_sel_i[3]) store[31:24] <= wb_dat_i[31:24];
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end
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wb_dat_o <= store;
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wb_ack_o <= valid & !wb_ack_o;
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end
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end
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endmodule |