mirror of https://github.com/efabless/caravel.git
de9605a01b
zero level outputs when the user project area is powered down. That allows the synthesis tools to buffer these outputs. The protection from floating inputs is left as-is, but all logic that was unnecessary to be specified by gate instances has been changed to RTL. This leaves only a handful of signals (logic analyzer input, user IRQ, and wishbone data out and acknowledge out) to be handled by explicit logic gate instances. |
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| dv | ||
| gl | ||
| rtl | ||
| stubs | ||