mirror of https://github.com/efabless/caravel.git
799 lines
20 KiB
Plaintext
799 lines
20 KiB
Plaintext
VERSION 5.7 ;
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NOWIREEXTENSIONATPIN ON ;
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DIVIDERCHAR "/" ;
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BUSBITCHARS "[]" ;
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MACRO gpio_control_block
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CLASS BLOCK ;
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FOREIGN gpio_control_block ;
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ORIGIN 0.000 0.000 ;
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SIZE 170.000 BY 65.000 ;
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PIN gpio_defaults[0]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 4.690 61.000 4.970 65.000 ;
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END
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END gpio_defaults[0]
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PIN gpio_defaults[10]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 27.690 61.000 27.970 65.000 ;
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END
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END gpio_defaults[10]
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PIN gpio_defaults[11]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 29.990 61.000 30.270 65.000 ;
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END
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END gpio_defaults[11]
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PIN gpio_defaults[12]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 32.290 61.000 32.570 65.000 ;
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END
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END gpio_defaults[12]
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PIN gpio_defaults[1]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 6.990 61.000 7.270 65.000 ;
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END
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END gpio_defaults[1]
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PIN gpio_defaults[2]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 9.290 61.000 9.570 65.000 ;
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END
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END gpio_defaults[2]
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PIN gpio_defaults[3]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 11.590 61.000 11.870 65.000 ;
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END
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END gpio_defaults[3]
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PIN gpio_defaults[4]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 13.890 61.000 14.170 65.000 ;
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END
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END gpio_defaults[4]
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PIN gpio_defaults[5]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 16.190 61.000 16.470 65.000 ;
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END
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END gpio_defaults[5]
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PIN gpio_defaults[6]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 18.490 61.000 18.770 65.000 ;
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END
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END gpio_defaults[6]
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PIN gpio_defaults[7]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 20.790 61.000 21.070 65.000 ;
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END
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END gpio_defaults[7]
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PIN gpio_defaults[8]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 23.090 61.000 23.370 65.000 ;
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END
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END gpio_defaults[8]
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PIN gpio_defaults[9]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 25.390 61.000 25.670 65.000 ;
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END
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END gpio_defaults[9]
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PIN mgmt_gpio_in
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 4.120 170.000 4.720 ;
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END
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END mgmt_gpio_in
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PIN mgmt_gpio_oeb
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 8.200 170.000 8.800 ;
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END
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END mgmt_gpio_oeb
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PIN mgmt_gpio_out
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 10.240 170.000 10.840 ;
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END
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END mgmt_gpio_out
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PIN one
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 6.160 170.000 6.760 ;
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END
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END one
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PIN pad_gpio_ana_en
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 12.280 170.000 12.880 ;
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END
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END pad_gpio_ana_en
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PIN pad_gpio_ana_pol
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 14.320 170.000 14.920 ;
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END
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END pad_gpio_ana_pol
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PIN pad_gpio_ana_sel
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 16.360 170.000 16.960 ;
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END
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END pad_gpio_ana_sel
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PIN pad_gpio_dm[0]
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 18.400 170.000 19.000 ;
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END
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END pad_gpio_dm[0]
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PIN pad_gpio_dm[1]
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 20.440 170.000 21.040 ;
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END
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END pad_gpio_dm[1]
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PIN pad_gpio_dm[2]
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 22.480 170.000 23.080 ;
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END
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END pad_gpio_dm[2]
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PIN pad_gpio_holdover
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 24.520 170.000 25.120 ;
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END
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END pad_gpio_holdover
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PIN pad_gpio_ib_mode_sel
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 26.560 170.000 27.160 ;
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END
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END pad_gpio_ib_mode_sel
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PIN pad_gpio_in
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 28.600 170.000 29.200 ;
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END
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END pad_gpio_in
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PIN pad_gpio_inenb
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 30.640 170.000 31.240 ;
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END
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END pad_gpio_inenb
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PIN pad_gpio_out
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 32.680 170.000 33.280 ;
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END
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END pad_gpio_out
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PIN pad_gpio_outenb
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 34.720 170.000 35.320 ;
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END
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END pad_gpio_outenb
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PIN pad_gpio_slow_sel
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 36.760 170.000 37.360 ;
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END
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END pad_gpio_slow_sel
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PIN pad_gpio_vtrip_sel
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 38.800 170.000 39.400 ;
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END
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END pad_gpio_vtrip_sel
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PIN resetn
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 40.840 170.000 41.440 ;
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END
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END resetn
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PIN resetn_out
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 42.880 170.000 43.480 ;
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END
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END resetn_out
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PIN serial_clock
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 44.920 170.000 45.520 ;
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END
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END serial_clock
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PIN serial_clock_out
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 46.960 170.000 47.560 ;
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END
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END serial_clock_out
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PIN serial_data_in
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 49.000 170.000 49.600 ;
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END
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END serial_data_in
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PIN serial_data_out
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 51.040 170.000 51.640 ;
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END
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END serial_data_out
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PIN serial_load
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 53.080 170.000 53.680 ;
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END
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END serial_load
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PIN serial_load_out
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 55.120 170.000 55.720 ;
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END
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END serial_load_out
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PIN user_gpio_in
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 57.160 170.000 57.760 ;
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END
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END user_gpio_in
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PIN user_gpio_oeb
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 59.200 170.000 59.800 ;
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END
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END user_gpio_oeb
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PIN user_gpio_out
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 61.240 170.000 61.840 ;
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END
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END user_gpio_out
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PIN vccd
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DIRECTION INOUT ;
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USE POWER ;
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PORT
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LAYER met4 ;
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RECT 12.800 2.480 14.400 60.080 ;
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END
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PORT
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LAYER met4 ;
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RECT 37.800 2.480 39.400 60.080 ;
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END
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PORT
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LAYER met5 ;
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RECT 4.360 5.900 51.760 7.500 ;
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END
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PORT
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LAYER met5 ;
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RECT 4.360 22.800 51.760 24.400 ;
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END
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PORT
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LAYER met5 ;
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RECT 4.360 39.700 51.760 41.300 ;
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END
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PORT
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LAYER met5 ;
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RECT 4.360 56.600 51.760 58.200 ;
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END
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END vccd
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PIN vccd1
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DIRECTION INOUT ;
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USE POWER ;
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PORT
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LAYER met4 ;
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RECT 17.800 2.480 19.400 60.080 ;
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END
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PORT
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LAYER met4 ;
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RECT 42.800 2.480 44.400 60.080 ;
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END
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PORT
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LAYER met5 ;
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RECT 4.360 11.140 51.760 12.740 ;
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END
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PORT
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LAYER met5 ;
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RECT 4.360 28.040 51.760 29.640 ;
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END
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PORT
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LAYER met5 ;
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RECT 4.360 44.940 51.760 46.540 ;
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END
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END vccd1
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PIN vssd
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DIRECTION INOUT ;
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USE GROUND ;
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PORT
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LAYER met4 ;
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RECT 25.300 2.480 26.900 60.080 ;
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END
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PORT
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LAYER met5 ;
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RECT 4.360 14.350 51.760 15.950 ;
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END
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PORT
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LAYER met5 ;
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RECT 4.360 31.250 51.760 32.850 ;
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END
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PORT
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LAYER met5 ;
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RECT 4.360 48.150 51.760 49.750 ;
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END
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END vssd
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PIN vssd1
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DIRECTION INOUT ;
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USE GROUND ;
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PORT
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LAYER met4 ;
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RECT 30.300 2.480 31.900 60.080 ;
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END
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PORT
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LAYER met5 ;
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RECT 4.360 19.590 51.760 21.190 ;
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END
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PORT
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LAYER met5 ;
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RECT 4.360 36.490 51.760 38.090 ;
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END
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PORT
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LAYER met5 ;
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RECT 4.360 53.390 51.760 54.990 ;
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END
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END vssd1
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PIN zero
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 2.080 170.000 2.680 ;
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END
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END zero
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OBS
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LAYER li1 ;
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RECT 0.000 64.930 4.265 65.070 ;
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LAYER li1 ;
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RECT 4.265 64.930 169.810 65.000 ;
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LAYER li1 ;
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RECT 0.000 64.845 49.815 64.930 ;
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LAYER li1 ;
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RECT 49.815 64.845 169.810 64.930 ;
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LAYER li1 ;
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RECT 0.000 59.925 169.810 64.845 ;
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RECT 0.000 59.755 4.745 59.925 ;
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LAYER li1 ;
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RECT 4.745 59.755 169.810 59.925 ;
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LAYER li1 ;
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RECT 0.000 59.585 169.810 59.755 ;
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RECT 0.000 57.645 6.100 59.585 ;
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LAYER li1 ;
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RECT 6.100 57.645 169.810 59.585 ;
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LAYER li1 ;
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RECT 0.000 57.405 8.925 57.645 ;
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LAYER li1 ;
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RECT 8.925 57.405 169.810 57.645 ;
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LAYER li1 ;
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RECT 0.000 30.025 4.265 57.405 ;
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LAYER li1 ;
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RECT 4.265 30.025 169.810 57.405 ;
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LAYER li1 ;
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RECT 0.000 30.005 16.795 30.025 ;
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LAYER li1 ;
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RECT 16.795 30.005 169.810 30.025 ;
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LAYER li1 ;
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RECT 0.000 29.835 4.745 30.005 ;
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LAYER li1 ;
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RECT 4.745 29.835 169.810 30.005 ;
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LAYER li1 ;
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RECT 0.000 29.665 16.795 29.835 ;
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LAYER li1 ;
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RECT 16.795 29.665 169.810 29.835 ;
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LAYER li1 ;
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RECT 0.000 27.455 6.065 29.665 ;
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LAYER li1 ;
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RECT 6.065 27.455 169.810 29.665 ;
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LAYER li1 ;
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RECT 0.000 27.285 16.795 27.455 ;
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LAYER li1 ;
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RECT 16.795 27.285 169.810 27.455 ;
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LAYER li1 ;
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RECT 0.000 27.115 4.745 27.285 ;
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LAYER li1 ;
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RECT 4.745 27.115 169.810 27.285 ;
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LAYER li1 ;
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RECT 0.000 26.945 16.795 27.115 ;
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LAYER li1 ;
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RECT 16.795 26.945 169.810 27.115 ;
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LAYER li1 ;
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RECT 0.000 26.185 16.905 26.945 ;
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LAYER li1 ;
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RECT 16.905 26.185 169.810 26.945 ;
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LAYER li1 ;
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RECT 0.000 26.015 17.450 26.185 ;
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LAYER li1 ;
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RECT 17.450 26.015 169.810 26.185 ;
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LAYER li1 ;
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RECT 0.000 25.835 16.795 26.015 ;
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LAYER li1 ;
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RECT 16.795 25.835 169.810 26.015 ;
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LAYER li1 ;
|
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RECT 0.000 25.465 16.645 25.835 ;
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LAYER li1 ;
|
|
RECT 16.645 25.465 169.810 25.835 ;
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LAYER li1 ;
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RECT 0.000 25.285 16.795 25.465 ;
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LAYER li1 ;
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RECT 16.795 25.285 169.810 25.465 ;
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LAYER li1 ;
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RECT 0.000 25.115 17.450 25.285 ;
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LAYER li1 ;
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RECT 17.450 25.115 169.810 25.285 ;
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LAYER li1 ;
|
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RECT 0.000 24.735 16.905 25.115 ;
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LAYER li1 ;
|
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RECT 16.905 24.735 169.810 25.115 ;
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LAYER li1 ;
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RECT 0.000 24.565 16.795 24.735 ;
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LAYER li1 ;
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RECT 16.795 24.565 169.810 24.735 ;
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LAYER li1 ;
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RECT 0.000 24.395 15.325 24.565 ;
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LAYER li1 ;
|
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RECT 15.325 24.395 169.810 24.565 ;
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LAYER li1 ;
|
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RECT 0.000 24.225 16.795 24.395 ;
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LAYER li1 ;
|
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RECT 16.795 24.225 169.810 24.395 ;
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LAYER li1 ;
|
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RECT 0.000 22.015 16.645 24.225 ;
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LAYER li1 ;
|
|
RECT 16.645 22.015 169.810 24.225 ;
|
|
LAYER li1 ;
|
|
RECT 0.000 21.845 16.795 22.015 ;
|
|
LAYER li1 ;
|
|
RECT 16.795 21.845 169.810 22.015 ;
|
|
LAYER li1 ;
|
|
RECT 0.000 21.675 15.325 21.845 ;
|
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LAYER li1 ;
|
|
RECT 15.325 21.675 169.810 21.845 ;
|
|
LAYER li1 ;
|
|
RECT 0.000 20.865 16.950 21.675 ;
|
|
LAYER li1 ;
|
|
RECT 16.950 20.865 169.810 21.675 ;
|
|
LAYER li1 ;
|
|
RECT 0.000 20.365 16.795 20.865 ;
|
|
LAYER li1 ;
|
|
RECT 16.795 20.365 169.810 20.865 ;
|
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END
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END gpio_control_block
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END LIBRARY
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