mirror of https://github.com/efabless/caravel.git
97 lines
3.1 KiB
Tcl
97 lines
3.1 KiB
Tcl
# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
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## This should be changed to point at Caravel root
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set ::env(CARAVEL_ROOT) $::env(DESIGN_DIR)/../..
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set ::env(STA_WRITE_LIB) 0
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set ::env(DESIGN_NAME) "housekeeping"
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set ::env(ROUTING_CORES) 12
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set ::env(RUN_KLAYOUT) 0
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set ::env(PDK) "sky130A"
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set ::env(VERILOG_FILES) "$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
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$::env(CARAVEL_ROOT)/verilog/rtl/housekeeping.v \
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$::env(CARAVEL_ROOT)/verilog/rtl/housekeeping_spi.v"
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set ::env(CLOCK_PORT) ""
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set ::env(CLOCK_NET) "wb_clk_i csclk mgmt_gpio_in\[4\]"
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set ::env(CLOCK_TREE_SYNTH) 1
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set ::env(BASE_SDC_FILE) [glob $::env(DESIGN_DIR)/base.sdc]
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## Synthesis
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set ::env(NO_SYNTH_CELL_LIST) [glob $::env(DESIGN_DIR)/no_synth.list]
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# set ::env(DRC_EXCLUDE_CELL_LIST) [glob $::env(DESIGN_DIR)/drc_exclude.list]
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set ::env(SYNTH_STRATEGY) "AREA 0"
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set ::env(SYNTH_MAX_FANOUT) 20
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set ::env(SYNTH_BUFFERING) 0
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## Floorplan
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set ::env(FP_SIZING) absolute
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set ::env(DIE_AREA) "0 0 370.230 550.950"
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set ::env(FP_PIN_ORDER_CFG) [glob $::env(DESIGN_DIR)/pin_order.cfg]
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set ::env(FP_IO_MIN_DISTANCE) 2
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set ::env(CELL_PAD) 0
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set ::env(FP_PDN_HPITCH) 153.18
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set ::env(FP_PDN_HSPACING) 74.99
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set ::env(FP_PDN_HOFFSET) 16.41
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## Placement
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set ::env(PL_TARGET_DENSITY) 0.31
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set ::env(PL_TIME_DRIVEN) 1
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set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
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set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1
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# set ::env(PL_RESIZER_MAX_WIRE_LENGTH) 250
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set ::env(PL_RESIZER_SETUP_SLACK_MARGIN) 0.4
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set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.1
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set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "50"
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set ::env(PL_RESIZER_MAX_CAP_MARGIN) "50"
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# set ::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT) 50
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# set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) 1
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set ::env(CLOCK_TREE_SYNTH) 1
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## Routing
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set ::env(GLB_ADJUSTMENT) 0.2
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set ::env(GLB_OVERFLOW_ITERS) 100
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set ::env(GRT_ALLOW_CONGESTION) 1
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set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 1
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set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.4
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# set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) 250
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# set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) "30"
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# set ::env(GLB_RESIZER_MAX_CAP_MARGIN) "30"
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set ::env(GLB_RESIZER_SETUP_SLACK_MARGIN) 0.2
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## Diode Insertion
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set ::env(DIODE_INSERTION_STRATEGY) 3
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set ::env(GRT_ANT_ITERS) 10
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set ::env(GRT_MAX_DIODE_INS_ITERS) 10
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# set ::env(USE_ARC_ANTENNA_CHECK) 0
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## clock buffering
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# set ::env(CTS_CLK_BUFFER_LIST) {sky130_fd_sc_hd__clkbuf_8 sky130_fd_sc_hd__clkbuf_4}
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# set ::env(CTS_ROOT_BUFFER) {sky130_fd_sc_hd__clkbuf_8}
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# set ::env(CTS_CLK_MAX_WIRE_LENGTH) 120
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set ::env(CTS_MAX_CAP) 0.25
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set ::env(MAGIC_DEF_LABELS) 0 |