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caravel/verilog/rtl
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Tim Edwards 184f4a637c Added the rest of the testbenches: mprj_bitbang, perf, pll, qspi, and 
storage.  Not all of these pass simulation checks.  Added back the
bit-bang control of the GPIO programming.  Added back the read-only
interface between the housekeeping module and the SRAM 2nd port.
Revised the memory map text document to reflect the addition of the
SRAM ports.  There is not yet a testbench for the SRAM read-only
interface.
 		2021-10-19 19:05:47 -04:00
..
__uprj_analog_netlists.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
__uprj_netlists.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
__user_analog_project_wrapper.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
__user_project_wrapper.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
caravan.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
caravan_netlists.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
caravel.v Added the rest of the testbenches: mprj_bitbang, perf, pll, qspi, and 2021-10-19 19:05:47 -04:00
caravel_clocking.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
caravel_netlists.v First major update; current code passes syntax checks in iverilog 2021-10-15 21:49:49 -04:00
caravel_openframe.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
chip_io.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
chip_io_alt.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
clock_div.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
defines.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
digital_pll.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
digital_pll_controller.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
gpio_control_block.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
gpio_logic_high.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
housekeeping.v Added the rest of the testbenches: mprj_bitbang, perf, pll, qspi, and 2021-10-19 19:05:47 -04:00
housekeeping_spi.v First major update; current code passes syntax checks in iverilog 2021-10-15 21:49:49 -04:00
mgmt_protect.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
mgmt_protect_hv.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
mprj2_logic_high.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
mprj_io.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
mprj_logic_high.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
pads.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
ring_osc2x13.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
simple_por.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00
user_id_programming.v Seeding with documentation of pinout and verilog RTL (mostly unchanged 2021-10-12 16:31:42 -04:00