mirror of https://github.com/efabless/caravel.git
38 lines
1.3 KiB
Tcl
38 lines
1.3 KiB
Tcl
# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
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package require openlane
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set script_dir [file dirname [file normalize [info script]]]
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## ORIGINAL FLOORPLAN FOR CONNECTIVITY INFO
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set ::env(CONNECTIVITY_RUN) 1
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prep -design $script_dir -tag caravel_lvs -overwrite
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set top_rtl $script_dir/../../verilog/rtl/caravel.v
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set ::env(SYNTH_DEFINES) "USE_POWER_PINS"
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verilog_elaborate
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logic_equiv_check -lhs $top_rtl -rhs $::env(yosys_result_file_tag).v
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init_floorplan
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if { [info exists ::env(LVS_RUN_DIR)] } {
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file copy -force $::env(CURRENT_DEF) $::env(LVS_RUN_DIR)/lvs.def
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file copy -force $::env(CURRENT_NETLIST) $::env(LVS_RUN_DIR)/lvs.v
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file copy -force $::env(MERGED_LEF_UNPADDED) $::env(LVS_RUN_DIR)/lvs.lef
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} else {
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puts "Warning: LVS_RUN_DIR not defined"
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}
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