mirror of https://github.com/efabless/caravel.git
263 lines
7.4 KiB
Verilog
263 lines
7.4 KiB
Verilog
// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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`default_nettype none
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`timescale 1 ns / 1 ps
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`define UNIT_DELAY #1
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`define USE_POWER_PINS
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`define SIM_TIME 100_000
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`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
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`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
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`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
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`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
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`include "defines.v"
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`ifdef GL
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// Assume default net type to be wire because GL netlists don't have the wire definitions
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`default_nettype wire
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`include "gl/mprj_logic_high.v"
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`include "gl/mprj2_logic_high.v"
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`include "gl/mgmt_protect.v"
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`include "gl/mgmt_protect_hv.v"
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`else
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`include "mprj_logic_high.v"
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`include "mprj2_logic_high.v"
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`include "mgmt_protect.v"
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`include "mgmt_protect_hv.v"
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`endif
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module mgmt_protect_tb;
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reg caravel_clk;
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reg caravel_clk2;
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reg caravel_rstn;
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reg mprj_cyc_o_core;
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reg mprj_stb_o_core;
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reg mprj_we_o_core;
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reg [31:0] mprj_adr_o_core;
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reg [31:0] mprj_dat_o_core;
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reg [3:0] mprj_sel_o_core;
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wire [127:0] la_data_in_mprj;
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reg [127:0] la_data_out_mprj;
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reg [127:0] la_oenb_mprj;
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reg [127:0] la_iena_mprj;
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reg [127:0] la_data_out_core;
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wire [127:0] la_data_in_core;
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wire [127:0] la_oenb_core;
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wire user_clock;
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wire user_clock2;
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wire user_reset;
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wire mprj_cyc_o_user;
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wire mprj_stb_o_user;
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wire mprj_we_o_user;
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wire [3:0] mprj_sel_o_user;
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wire [31:0] mprj_adr_o_user;
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wire [31:0] mprj_dat_o_user;
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wire user1_vcc_powergood;
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wire user2_vcc_powergood;
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wire user1_vdd_powergood;
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wire user2_vdd_powergood;
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always #12.5 caravel_clk <= (caravel_clk === 1'b0);
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always #12.5 caravel_clk2 <= (caravel_clk2 === 1'b0);
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initial begin
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caravel_clk = 0;
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caravel_clk2 = 0;
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caravel_rstn = 0;
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mprj_cyc_o_core = 0;
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mprj_stb_o_core = 0;
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mprj_we_o_core = 0;
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mprj_adr_o_core = 0;
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mprj_dat_o_core = 0;
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mprj_sel_o_core = 0;
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la_data_out_mprj = 0;
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la_oenb_mprj = 0;
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la_data_out_core = 0;
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end
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reg USER_VDD3V3;
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reg USER_VDD1V8;
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reg VDD3V3;
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reg VDD1V8;
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wire VCCD; // Management/Common 1.8V power
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wire VSSD; // Common digital ground
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wire VCCD1; // User area 1 1.8V power
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wire VSSD1; // User area 1 digital ground
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wire VCCD2; // User area 2 1.8V power
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wire VSSD2; // User area 2 digital ground
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wire VDDA1; // User area 1 3.3V power
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wire VSSA1; // User area 1 analog ground
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wire VDDA2; // User area 2 3.3V power
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wire VSSA2; // User area 2 analog ground
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assign VCCD = VDD1V8;
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assign VSSD = 1'b0;
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assign VCCD1 = USER_VDD1V8;
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assign VSSD1 = 1'b0;
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assign VCCD2 = USER_VDD1V8;
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assign VSSD2 = 1'b0;
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assign VDDA1 = USER_VDD3V3;
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assign VSSA1 = 1'b0;
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assign VDDA2 = USER_VDD3V3;
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assign VSSA2 = 1'b0;
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initial begin // Power-up sequence
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VDD1V8 <= 1'b0;
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USER_VDD3V3 <= 1'b0;
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USER_VDD1V8 <= 1'b0;
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#200;
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VDD1V8 <= 1'b1;
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#200;
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USER_VDD3V3 <= 1'b1;
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#200;
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USER_VDD1V8 <= 1'b1;
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end
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initial begin
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$dumpfile("mgmt_protect.vcd");
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$dumpvars(0, mgmt_protect_tb);
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#(`SIM_TIME);
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$display("%c[1;31m",27);
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$display ("Monitor: Timeout, Test Management Protect Failed");
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$display("%c[0m",27);
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$finish;
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end
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integer i;
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initial begin
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caravel_rstn = 1'b1;
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mprj_cyc_o_core = 1'b1;
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mprj_stb_o_core = 1'b1;
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mprj_we_o_core = 1'b1;
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mprj_sel_o_core = 4'b1010;
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mprj_adr_o_core = 32'hF0F0;
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mprj_dat_o_core = 32'h0F0F;
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la_data_out_mprj = 128'hFFFF_FFFF_FFFF_FFFF;
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la_oenb_mprj = 128'h0000_0000_0000_0000;
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la_data_out_core = 128'h0F0F_FFFF_F0F0_FFFF;
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la_iena_mprj = 128'hFFFF_FFFF_FFFF_FFFF;
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wait(user1_vdd_powergood === 1'b1);
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wait(user2_vdd_powergood === 1'b1);
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wait(user1_vcc_powergood === 1'b1);
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wait(user2_vcc_powergood === 1'b1);
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#25;
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if (user_reset !== ~caravel_rstn) begin
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$display("Monitor: Error on user_reset. "); $finish;
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end
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if (mprj_cyc_o_user !== mprj_cyc_o_core) begin
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$display("Monitor: Error on mprj_cyc_o_user. "); $finish;
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end
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if (mprj_stb_o_user !== mprj_stb_o_core) begin
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$display("Monitor: Error on mprj_stb_o_user. "); $finish;
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end
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if (mprj_we_o_user !== mprj_we_o_core) begin
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$display("Monitor: Error on mprj_we_o_user. "); $finish;
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end
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if (mprj_sel_o_user !== mprj_sel_o_core) begin
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$display("Monitor: Error on mprj_sel_o_user. "); $finish;
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end
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if (mprj_adr_o_user !== mprj_adr_o_core) begin
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$display("Monitor: Error on mprj_adr_o_user. "); $finish;
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end
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if (la_data_in_core !== la_data_out_mprj) begin
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$display("%0h", la_data_in_core);
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$display("Monitor: Error on la_data_in_core. "); $finish;
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end
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if (la_oenb_core !== la_oenb_mprj) begin
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$display("Monitor: Error on la_oenb_core. "); $finish;
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end
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if (la_data_in_mprj !== la_data_out_core) begin
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$display("%0h , %0h", la_data_in_mprj, la_data_out_core);
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$display("Monitor: Error on la_data_in_mprj. "); $finish;
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end
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$display ("Success!");
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$display ("Monitor: Test Management Protect Passed");
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$finish;
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end
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mgmt_protect uut (
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`ifdef USE_POWER_PINS
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.vccd(VCCD),
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.vssd(VSSD),
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.vccd1(VCCD1),
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.vssd1(VSSD1),
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.vccd2(VCCD2),
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.vssd2(VSSD2),
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.vdda1(VDDA1),
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.vssa1(VSSA1),
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.vdda2(VDDA2),
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.vssa2(VSSA2),
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`endif
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.caravel_clk (caravel_clk),
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.caravel_clk2(caravel_clk2),
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.caravel_rstn(caravel_rstn),
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.mprj_cyc_o_core(mprj_cyc_o_core),
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.mprj_stb_o_core(mprj_stb_o_core),
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.mprj_we_o_core (mprj_we_o_core),
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.mprj_sel_o_core(mprj_sel_o_core),
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.mprj_adr_o_core(mprj_adr_o_core),
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.mprj_dat_o_core(mprj_dat_o_core),
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.la_data_out_core(la_data_out_core),
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.la_data_in_core (la_data_in_core),
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.la_oenb_core(la_oenb_core),
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.la_data_in_mprj(la_data_in_mprj),
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.la_data_out_mprj(la_data_out_mprj),
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.la_oenb_mprj(la_oenb_mprj),
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.la_iena_mprj(la_iena_mprj),
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.user_clock (user_clock),
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.user_clock2(user_clock2),
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.user_reset (user_reset),
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.mprj_cyc_o_user(mprj_cyc_o_user),
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.mprj_stb_o_user(mprj_stb_o_user),
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.mprj_we_o_user (mprj_we_o_user),
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.mprj_sel_o_user(mprj_sel_o_user),
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.mprj_adr_o_user(mprj_adr_o_user),
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.mprj_dat_o_user(mprj_dat_o_user),
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.user1_vcc_powergood(user1_vcc_powergood),
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.user2_vcc_powergood(user2_vcc_powergood),
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.user1_vdd_powergood(user1_vdd_powergood),
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.user2_vdd_powergood(user2_vdd_powergood)
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);
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endmodule |